|CPU||Quad-Core ARM Cortex-A53|
|Memory||up to 4 GB DDR4 / DDR3 / DDR3L / LPDDR3 / LPDDR4|
HDMI 2.0a up to 4K @ 60Hz|
CVBS with PAL or NTSC
|Audio||I2S, S/PDIF, HDMI audio|
1x 10/100M MAC with PHY|
1x GBit MAC with RGMII
|USB||USB2.0: 1x OTG + 3x Host|
IOMMU, 3x SDIO, 2x SPI,|
6x UART, 6x I2C, 4x PWM,
TFBGA284, 0.65mm pitch, 0.35mm ball size, 14x12mm
Allwinner H616 (sun50iw9p1) is a SoC that features a Quad-Core Cortex-A53 ARM CPU, and a Mali-G31 MP2 GPU from ARM. The H618 is a minor update with a larger (1MB) L2 cache. The T507 uses the same die, but routes out additional pins, to expose LCD and camera functionality.
There seem to be at least two different die revisions, which use a different CPUX_CFG IP block. See below for more details.
Compared to the H6 SoC, it lacks USB 3.0 and PCIe, but adds a second Ethernet interface (100Mbit/s only). Apparently it has no CPUS (ARISC management processor) anymore, also is missing the associated SRAM A2.
The memory map extends beyond 4GB, to accommodate a full 4GB of DRAM. However the DMA controller in the EMAC network device still only contain 32 bits worth of a physical memory address, which prevents DMA buffers to be located beyond 3GB. This is not a problem, because the Ethernet driver knows about this and will ask the kernel for the DMA buffers to be located within the first 4GB of physical address space only. The MMC controller has been somewhat hacked to support up to 15 GB of DRAM, so SD card or eMMC DMA can use the whole DRAM as a target.
VER_REG register at address
0x3000024 encodes the die revision in its lowest 8 bits. The BSP code differentiates between
- The older, original die revision 0 has the CPUX_CFG IP block as documented in the H616 user manual, located at address
- Chips with die revision 2 have a different IP block providing that same functionality, at address
This IP block is relevant to U-Boot and Trusted Firmware only, and is detected and handled there automatically in later releases. The kernel itself is not affected by this change.
Most chips labelled H616 seem to ship in die revision 0, although there have been reports of both H616 and H313 chips in die revision 2 as well. The T507 also ships in both die revisions. All H618 chips so far seem to be die revision 2. It is yet unconfirmed, but likely that the die revision also corresponds to the L2 cache size change (512KB for revision 0, 1MB for revision 2).
- File:H616 Datasheet V1.0 cleaned.pdf
- File:H616 User Manual V1.0 cleaned.pdf
- File:H616 USB module manual.pdf
- File:H616 Android Q OTA Development and Use Guide.pdf
U-Boot and Trusted-Firmware-A support have been merged into the official repositories, please use the latest master branch and refer to the respective documentation for building the firmware.
Basic Linux support is mainline since v6.0, the essential pinctrl and clock drivers were merged already into v5.12.
The Xunlong Orange Pi Zero2 was used as the primary bringup device.
The H618 is fully compatible from a kernel point of view, but does require extra support in U-Boot, TF-A and sunxi-fel. Support for that has been merged in mainline releases.
- https://www.cnx-software.com/2020/02/27/allwinner-h616-tv-box-processor-comes-with-mali-g31-gpu-supports-android-10/ Allwinner H616 TV Box Processor Comes with Mali G31 GPU, Supports Android 10