D1s
Jump to navigation
Jump to search
| D1s | |
|---|---|
 | |
| Manufacturer | Allwinner |
| Process | 22nm[1] |
| CPU |
XuanTie C906 RISC-V [1] |
| Extensions | RV64IMAFDCVU |
| Memory |
DDR2 64 MB [2] |
| VPU |
Decoding: 1080p @ 60 FPS H265 / H264 / MPEG / JPEG / VC1 / MJPEG Encoding: 1080p @ 60 FPS JPEG / MJPEG [2] |
| Connectivity | |
| Video |
Out: MIPI / LVDS / LCD / CVBS In: CSI / CVBS [2][1] |
| Audio |
DAC / ADC / CODEC / I2S-PCM / DMIC [2] |
| Network | 10/100/1000M EMAC[2] |
| Storage | SDIO 3.0, eMMC 5.0, SPI NOR/NAND Flash[1] |
| USB | USB2.0: 1x OTG + 1x Host[2] |
| Other |
G2D[2] Display Engine[2] SDIO, 2x SPI, 6x UART, 4x I2C, PWM, IR, LRADC, GPADC, TPADC LFBGA, 337 pins[1] |
This page is still under construction.
Allwinner D1s (also known as F133) is based on a RISC-V core, and is a cheaper version of the D1 with the following differences:
- 64 MB of DDR2 memory included in the same package, instead of requiring external memory.
- No Tensilica HiFi4 DSP.
- No HDMI output.
- One less I2S port.
The D1s features a single RV64GCV[3] core XuanTie C906 from T-Head Semiconductor (subsidiary of Alibaba).
Overview
The T113-s3 is a pin-compatible variant with dual Cortex-A7 cores, all peripherals being identical.
Documentation
- D1s brief v1.0
- D1s Datasheet v1.0
- DIs User Manual v1.0 (github) DIs User Manual v1.0 (backup)
- Xuantie C906 R1S0 RISC-V core User Manual (玄铁C906_R1S0用户手册) (chinese)
- Specification of the DE2.0 Display Engine used in the D1s
- Xuantie C906 core RTL