T113-s3

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T113-s3
T113-s3.jpg
Manufacturer Allwinner
Process 22 nm
CPU Dual-Core ARM Cortex-A7 @ 1.2 GHz
Extensions Thumb-2, Jazelle RCT, NEOS, VFPv4, LPAE
Memory 128MB(-S3)/256MB(-S4) DDR3 SIP
GPU N/A
VPU SmartColor 2.0, hardware encode/decode
Connectivity
Video SPI DBI, RGB, LVDS, MIPI DSI
Audio I2S, PCM
Network Ethernet MAC, 2x CAN bus
Storage MMC, eMMC, Nor Flash
USB 1x OTG, 1x Host
Other HiFi4 DSP, SDIO 3.0 (Wireless), crypto engine
Release Date 2021(-S3)/2023(-S4)
Website https://www.allwinnertech.com/index.php?c=product&a=index&pid=9

Overview

The Allwinner T113-s3 (sun8i) SoC features a Dual-Core Cortex-A7 ARM CPU and 128MB of DDR3 memory. It supports industrial temperature ranges and is targeted at the automotive sector. The ARTINCHIP AIC600E3 (Known as T113-s4) is using the same die, but comes with 256MB of DDR3 memory instead.

The D1s is a pin-compatible variant with a single RISC-V core, all peripherals being identical except the CAN bus controller, exclusive to this chip.

Mainline Linux is work in progress. Most of the peripherals are already supported, by the virtue of being compatible with the D1.

AWBoot and XBoot are the only supported bootloaders at the moment, but U-Boot support is work in progress, with the DRAM driver being an important part.

Allwinner maintains a 5.4/5.10 branch for it, with their Tina-Linux distribution.

T113-s3 SoC Features

  • CPU
    • ARM Cortex-A7 Dual-Core
    • 256 KB L2-Cache (shared between both cores)
    • 32 KB (Instruction) / 32 KiB (Data) L1-Cache per core
    • SIMD NEON, VFP4
    • Large Physical Address Extensions (LPAE) 1 TB
  • Memory
    • 128MB(-S3)/256MB(-S4) DDR3 SIP
  • Storage
    • QSPI NOR and NAND, eMMC 5.0, SD 3.0
  • Video
    • decoding MPEG-1/2/3/4, MJPEG, H.264, H.265, VC-1 1080p @ 60 fps
    • encoding MJPEG 1080p @ 60 fps
  • Display
    • Maximum resolution 2048x2048
    • CPU/RGB/LVDS LCD interface 1920x1080@60fps
    • MIPI 4 lane DSI interface up to 1920x1200@60fps
    • TV out: 1-ch CVBS
  • Camera
    • 1-channel CVBS
    • 8 bit parallel
  • Network
    • Gigabyte MAC with RMII/RGMII interfaces
    • 2x CAN 2.0 B controllers

Documentation

Software

Source code and instructions are here

See also

References


External links