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Allwinner A20.png
Manufacturer Allwinner
Process 40nm
CPU Dual-Core ARM Cortex-A7
GPU Mali400 MP2
Audio I2S, PCM, AC97
USB OTG, 2x Host
Release Date December 2012
Website Product Page

Allwinner A20 (sun7i) SoC features a Dual-Core Cortex-A7 ARM CPU, and a Mali400 MP2 GPU from ARM.

Allwinner A20 is a low-end (budget) version of the A31. It shares its Cortex-A7 ARM CPU architecture, but at the same time it is also pin-to-pin compatible with A10.

A20 is fully supported by the community from linux-sunxi 3.4 kernel and later.


A20 CPU consists of dual ARM Cortex-A7 cores, and integrates the Mali400 MP2 GPU. Together with Cedar Engine multimedia processing unit that is capable of up to 2160p ([email protected] 4k resolution or 1080p 3D decoding) video decoding, with integrated HDMI 1.4 output support, and H.264 HP (High Profile) in 1080p at 30fps video encoding.

Main components of the A20

  • CPU: Dual-Core ARM Cortex-A7 1GHz Processor (r0p4, revidr=0x0) which have both VFP4 and NEON SIMD co-processors that share 32 floating point double-precision registers together[1]:
    • FPU: standard ARM VFPv4-D32 FPU Floating Point Unit
    • SIMD: NEON (ARM's extended general-purpose SIMD vector processing extension engine)
  • GPU: Mali400 MP2
  • VPU: Cedar Engine (Video Processor Unit for audio and video hardware decoding or encoding)
  • HDMI-transmitter: HDMI CEC (Consumer Electronics Control)


Cortex-A7 is 100% ISA compatible with the Cortex-A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration.[2][3][4]


Cortex A7 and A15 includes hardware virtualization support.

On the kvm branch of kernel.org, there is description of Cortex-A15 Virtualization extensions VGIC registers :

After the ARM Cortex-A7 documentation:

  • GIC memory MAP on Cortex-A7[5]:
0x4000-0x4FFF	Virtual interface control, common base address
0x5000-0x5FFF	Virtual interface control, processor-specific base address
0x6000-0x7FFF	Virtual CPU interface
  • Virtual Maintenance Interrupt (PPI6)[6]
  • 2 virtual interrupt signals, nVIRQ and nVFIQ[7]
  • With MMU-400, Intermediate Physical Address (IPA) ca be used by guest OS[8]

A20 SoC Features

A20 SoC on a Cubieboard2
  • CPU
    • ARM Cortex-A7 Dual-Core (revision r0p4)
    • 256KiB L2-Cache (shared between two cores)
    • 32KiB (Instruction) / 32KiB (Data) L1-Cache per core
    • Virtualization
    • Large Physical Address Extensions (LPAE) 1TB
  • GPU
    • ARM Mali400 MP2
    • Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).
    • Complies with OpenGL ES 2.0
  • Memory
    • LPDDR2/DDR3/DDR3L controller
    • NAND Flash controller and 64-bit ECC
  • Video
    • HD H.264 2160P video decoding
    • Full HD video decoding
    • BD Directory, BD ISO and BD m2ts video decoding
    • H.264 High Profile [email protected] encoding
    • 3840×[email protected] 3D decoding
    • Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol
  • Display
    • Support multi-channel HD display
    • Integrated HDMI 1.4
    • CPU/RGB/LVDS LCD interface 1920×1080 resolution
    • CVBS/YPbPr/VGA support
    • Integrated TV decoder
    • 4 × up to 8096×8096 bitmaps layers
    • 32 × 32bits aRGB or 8bpp palette sprites blocks of up to 4096 (12 bits)×4096 size.
  • Camera
    • Integrated parallel 8-bit I/F YUV sensor
    • Integrated 24-bit parallel YUV 444 I/F
    • 5M/8M CMOS sensor support
    • Dual-sensor support
  • Audio
    • Integrated HI-FI 100dB Audio Codec
    • Dual MIC noise cancellation
  • package: BGA441 19 mm × 19 mm (0.80 mm Pitch)



The A20 SoC supports dynamic voltage & frequency scaling. Below are the DVFS operating points, as documented in the A20 SDK (lichee-v2.0.tar.gz):

; dvfs voltage-frequency table configuration
; max_freq: cpu maximum frequency, based on Hz, can not be more than 1008MHz
; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz
; LV_count: count of LV_freq/LV_volt, must be < 16
; LV1: core vdd is 1.45v if cpu frequency is (912Mhz, 1008Mhz]
; LV2: core vdd is 1.40v if cpu frequency is (864Mhz, 912Mhz]
; LV3: core vdd is 1.30v if cpu frequency is (792Mhz, 864Mhz]
; LV4: core vdd is 1.25v if cpu frequency is (720Mhz, 792Mhz]
; LV5: core vdd is 1.20v if cpu frequency is (624Mhz, 720Mhz]
; LV6: core vdd is 1.15v if cpu frequency is (528Mhz, 624Mhz]
; LV7: core vdd is 1.10v if cpu frequency is (312Mhz, 528Mhz]
; LV8: core vdd is 1.05v if cpu frequency is ( 60Mhz, 312Mhz]


Original SDKs

We have made some SDKs available on our server:

GPL Violations

See CedarX violations.


See also


  1. Cortex-A7 MPCore Technical Reference Manual — 1.3. Features
  2. http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices
  3. http://en.wikipedia.org/wiki/ARM_Cortex-A7_MPCore
  4. http://www.arm.com/products/processors/cortex-a/cortex-a7.php
  5. Cortex-A7 MPCore Technical Reference Manual - 8.2.1. GIC memory-map
  6. Cortex-A7 MPCore Technical Reference Manual - 8.2.2. Interrupt sources
  7. Cortex-A7 MPCore Technical Reference Manual - 8.2.4. GIC configuration
  8. CoreLink MMU-400 System Memory Management Unit Technical Reference Manual - 1.1. About the MMU-400

External links