H6-generation and newer Allwinner SoCs feature a PPU power domain controller that contains controls for major hardware blocks, such as the GPU and Video Engine. On the D1, the PPU replaces the CPUIDLE block for hardware power sequencing of CPU idle states.
Power Domain List
D1/R528/T113
| ID |
Description
|
| 0 |
CPU
|
| 1 |
VE
|
| 2 |
DSP
|
TV303
| ID |
Description
|
| 0 |
GPU
|
| 1 |
TVFE
|
| 2 |
TVCAP
|
| 3 |
VE
|
| 4 |
AV1
|
Registers
Base Address
| SoC |
Base Address
|
| (all known) |
0x7001000
|
Register Layout (A100/A133)
See the BSP driver source. This version has a different register layout and only controls the GPU power domain. This might be specific to PowerVR versions of the SoC.
Register Layout (D1/R528/T113/TV303)
| Register |
Offset
|
| PD_WAIT_MODE_REGn |
0x14 + 0x80 * n
|
| PD_PWR_OFF_DELAY_REGn |
0x18 + 0x80 * n
|
| PD_PWR_ON_DELAY_REGn |
0x1c + 0x80 * n
|
| PD_COMMAND_REGn |
0x20 + 0x80 * n
|
| PD_STATUS_REGn |
0x24 + 0x80 * n
|
| PD_ACTIVE_CTRL_REG |
0x2c
|
The "n" refers to the power domain ID (see above).
See also the BSP driver source.
Register Descriptions
PD_WAIT_MODE_REGn
| Offset |
0x14 |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| PD_WAIT_MODE |
31:0 |
RW |
0 |
0x8
|
The BSP sets this register to a fixed value. |
PD_PWR_OFF_DELAY_REGn
| Offset |
0x18 |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| PD_PWR_OFF_DELAY |
31:0 |
RW |
0 |
0x00080808
|
The BSP sets this register to a fixed value. |
PD_PWR_ON_DELAY_REGn
| Offset |
0x1c |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| PD_PWR_ON_DELAY |
31:0 |
RW |
0 |
0x00080808
|
The BSP sets this register to a fixed value. |
PD_COMMAND_REGn
| Offset |
0x20 |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| / |
31:2 |
/ |
/ |
|
|
| PD_COMMAND |
1:0 |
R/WAC |
0 |
0: No action
1: Turn the power domain on
2: Turn the power domain off
3: /
|
Only write this field when the power domain controller is idle. |
PD_STATUS_REGn
| Offset |
0x24 |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| / |
31:18 |
/ |
/ |
|
|
| PD_STATE |
17:16 |
RO |
/ |
0: /
1: The power domain is on
2: The power domain is off
3: /
|
|
| / |
15:4 |
/ |
/ |
|
|
| PD_IDLE |
3 |
R/W1C |
/ |
0: The power domain controller is idle
1: The power domain controller is busy
|
|
| ??? |
2 |
R/W1C |
/ |
|
|
| PD_TRANS_COMPLETE |
1 |
R/W1C |
/ |
0: No state transition has completed
1: A state transition has completed
|
|
| ??? |
0 |
R/W1C |
/ |
|
|
PD_ACTIVE_CTRL_REG
This register likely only exists for the CPU power domain.
| Offset |
0x2c |
| Name |
Bits |
R/W |
Default |
Values |
Description |
| / |
31:1 |
/ |
/ |
|
|
| PD_ACTIVE_CTRL |
0 |
RW |
0 |
0: CPU will not power down
1: CPU will power down when it enters WFI
|
This bit controls automatic CPU power-down for idle states. |