Allwinner SoCs have a bespoke interrupt controller. It was originally the only interrupt controller on the chip. On SoCs with a GIC (sun6i and newer), it sits between the NMI pin and a GIC input. It is responsible for controlling the NMI trigger type (high/low/rising/falling). On SoCs with an AR100, it serves as the interrupt controller for that CPU.
This interrupt controller uses the drivers/irqchip/irq-sun4i.c driver in Linux.
After Allwinner switched to using a GIC, but before they added a power management coprocessor, there was no need for a full INTC. SoCs like the A20 have a stripped-down version of the hardware, that only manages the trigger type for the NMI.
This interrupt controller uses the drivers/irqchip/irq-sunxi-nmi.c driver in Linux.
The R_INTC is the secondary interrupt controller in sun8i/sun50i SoCs that contain the AR100 coprocessor. It is closely related to the original sun4i INTC. While stripped down some, it is much closer to the original feature set than it is to the A20 NMI controller.
See the A13 manual for register descriptions. Only the first register of each type is implemented, so a maximum of 32 IRQs are supported (but see below). The priority logic appears not to be implemented, as setting any bit in the RESP register stops the AR100 from receiving interrupt exceptions from all IRQs.
The image below shows how the various registers control the IRQ flow. Note that the NMI IRQ has a latch (separate from any rising/falling trigger) that must be ACKed before the signal to the GIC will be deasserted.
The first IRQ is always the NMI. The order of the next 15 IRQs matches the order the corresponding inputs to the GIC. Then there is a region of uncertainty, containing at least the MSGBOX IRQ. The remainder of the IRQs are multiplexed from the same sources as the first hundred or so SPI IRQs.
The multiplexing of the individual IRQs in each "SPI IRQ" group is controlled by bits in registers 0xc0-0xcc, with one bit for each IRQ. There is no way (from R_INTC) to get the status of one of these multiplexed IRQs. If the CPU cluster is powered on, you can read the GICD ISPENDRs. Otherwise, you will have to check each IRQ source individually.
Same as A64 and H5. Verified with HSTIMER (SPI 51) => bit 25.
|7||R_RSB||Not present on H-series SoCs|
|19||SPI 0-7||Verified with I2C0 (6)|
|22||SPI 24-31||Verified with THS (31)|
|23||N/A||SPI 32-39 are the same as bits 0-7|
|24||N/A||SPI 40-47 are the same as bits 8-15|
|25||SPI 51-55||The bits in 0xc4 for SPI 48-50 are forced low|
|28||SPI 72-79||Verified with OHCI0 (75)|
|31||SPI 96-99||The bits in 0xcc for SPI 100-103 are forced low|
|0x40.16||CPUIDLE||From arisc BSP source|
|0x40.17||GIC_OUT||From arisc BSP source|
|0x40.18||SPINLOCK||From arisc BSP source|
|0x40.19||MSGBOX||From arisc BSP source|
|0x40.20||DMA||From arisc BSP source|
|0x40.21||SPI 0-7||Verified with I2C3 (7)|
|0x40.22||SPI 8-15||Verified with THS (15)|
|0x40.23||SPI 16-23||Verified with I2S2 (20)|
|0x40.24||SPI 24-31||Verified with OHCI3 (29)|
|0x40.26||SPI 40-47||Verified with HSTIMER (46)|
|0x40.27||SPI 48-55||Verified with TIMER0 (48), TIMER1 (49), GPIOF (53)|
|0x40.28||SPI 56-63||Verified with GPIOH (59)|
|0x40.31||SPI 80-87||Verified with IRQMMU (85)|
This interrupt controller currently uses the drivers/irqchip/irq-sunxi-nmi.c driver in Linux as well, but a new driver is needed to support preconfiguring the wakeup IRQs for the AR100.