|CPU||Quad-Core ARM Cortex-A7 @ 1.296GHz|
|GPU||Mali400 MP2 @ 600Mhz|
|Video||HDMI 1.4 with HDCP 1.2, TV CVBS|
|Audio||I2S, PCM, AC97|
|Network||GBit MAC, integrated 10/100M PHY|
|USB||1x OTG, 3x Host, all with integrated PHY|
|Release Date||October 2014|
Allwinner H3 (sun8iw7p1) SoC features a Quad-Core Cortex-A7 ARM CPU, and a Mali400 MP2 GPU from ARM. The Allwinner H3 is a highly cost-efficient quad-core OTT box processor, primarily marketed as being for "home entertainment" systems.
It has a nearly-compatible variant known now, H2+.
It's rated to run at 1.296GHz, anything higher is overclocking (and usually overvolting). If you run it without heatsink, fan and proper dvfs settings, you risk overheating.
See Mainlining Effort and Mainline U-Boot for support status.
H3 SoC Features
- ARM Cortex-A7 Quad-Core
- 512KB L2-Cache (shared between four cores)
- 32 KB (Instruction) / 32KiB (Data) L1-Cache per core
- SIMD NEON, VFP4
- Large Physical Address Extensions (LPAE) 1TB
- ARM Mali400 MP2
- Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).
- Complies with OpenGL ES 2.0
- DDR2/DDR2L-DDR3/DDR3L controller
- NAND Flash controller and 64-bit ECC
- Ultra HD 4k and Full HD 1080p video decoding of MPEG-2, MPEG-4 SP/ASP GMC, H.263, H.264, H.265, WMV9/VC-1, and VP8
- BD Directory, BD ISO and BD m2ts video decoding
- H.264 High Profile [email protected] encoding
- 3840×1080,1920x2160 3D decoding
- Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol
- Integrated HDMI V1.4 with HDCP1.2 [email protected]
- TV CVBS output
- Integrated parallel 8-bit I/F YUV422 sensor
- Support CCIR656 protocol fot NTSC and PAL
- 5M CMOS sensor support
- Support video capture resolution up to [email protected]
- Two audio digital-to-analog(DAC) channels 92dB SNR
- Two differential microphone inputs (one low-noise)
- Stereo Linein input
- Embedded Controller:
- AR100, an OpenRISC controller. Manages deep powersave modes.
- Thermal Sensor Controller (TSC) providing over-temperature protection interrupt and over-temperature alarm interrupt
- no PMU (According to arisc_dvfs.c pmuic_type defines 0~2, 0:none, 1:gpio, 2:i2c)
- package: FBGA347, 14 mm x 14 mm, 0.65 mm Pitch
H2+ is a variant of H3, targeted at low-end OTT boxes, which lacks Gigabit MAC and 4K HDMI output support.
H3 images are proven to run on H2+.
According to the source code of BSP, variants differ by the last byte of the first word of SID. 0x42 and 0x83 indicates H2+, 0x00 and 0x81 indicates H3, and 0x58 indicates H3D (a still unknown variant).
- File:Allwinner H3 Datasheet V1.2.pdf - 614 pages, 7MB, 2015-04-23
- Allwinner_H3_Datasheet_V1.1.pdf - 616 pages, 7MB, 2015-01-26
- Allwinner_H3_Datasheet_V1.0.pdf - 618 pages, 7MB, 2014-11-18
- Some 'confidental' documentation in Chinese
- File:Allwinner DE2.0 Spec V1.0.pdf - 147 pages, 2.9MB, 18-01-2018
- Display Engine 2.0 Register Guide
- Allwinner H3 Development Kit (Original name: 全志H3开发资料包)
Starting with version 2016.01, the official mainline U-Boot has supported the H3 SoC and various boards with it. This is the recommended way of booting boards when not using BSP kernels.
U-Boot defconfigs still missing for these H3 boards:
* Orange Pi Mini 2 (as a workaround, please use orangepi_2 defconfig) * Orange Pi Plus 2 (as a workaround, please use orangepi_plus defconfig) * pcDuino4 Nano (as a workaround, please use orangepi_one defconfig)
The mainline Linux kernel supports the H3 SoC quite well. For a more comprehensive list of supported features, see the status matrix for mainline kernels.
Device tree configs still missing for these H3 boards:
* Orange Pi Mini 2 (as a workaround, please use sun8i-h3-orangepi-2.dtb) * Orange Pi Plus 2 (as a workaround, please use sun8i-h3-orangepi-plus.dtb) * pcDuino4 Nano (as a workaround, please use sun8i-h3-orangepi-one.dtb)