B288/Clocks
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PLLs
Common bit definitions for PLL registers:
| Bit | R/W | default | description |
|---|---|---|---|
| 31 | R/W | 0x0 | PLL_ENABLE 0: Disable 1: Enable |
| 30-29 | / | / | / |
| 28 | R | 0x0 | LOCK 0: Unlocked 1: Locked (stable) |
| 27-25 | / | / | / |
| 24 | R/W | 0x0 | SDM_ENABLE 0: Disable 1: Enable |
| 23-21 | / | / | / |
| 20-16 | R/W | ? | PLL_DIVIDER_P PLL output external divider P |
| 15-8 | R/W | ? | PLL_FACTOR_N |
| 7-4 | R/W | ? | PLL_FACTOR_K |
| 3-0 | R/W | ? | PLL_FACTOR_M |
Available PLLs and their specific configuration:
| PLL name | reg offset | P divider | N factor | K factor | M divider |
|---|---|---|---|---|---|
| PLL_CPUX | 0x000 | [17:16] | [12:8] | [5:4] | [2:0] |
| PLL_AUDIO | 0x008 | [19:16] | [15:8] | - | [4:0] |
| PLL_VIDEO0 | 0x010 | - | [15:8] | - | [3:0] |
| PLL_DDR0 | 0x020 | - | [15:8] | - | [1:0] |
| PLL_PERIPH0 | 0x028 | - | [12:8] | [5:4] | - |
| PLL_VIDEO1 | 0x030 | - | [15:8] | - | [3:0] |
| PLL_24M | 0x034 | [20:16] | [15:8] | [7:4] | [1:0] |
| PLL_PERIPH1 | 0x044 | - | [12:8] | [5:4] | - |
| PLL_DE | 0x048 | - | [15:8] | - | [3:0] |
| PLL_DDR1 | 0x04c | - | [15:8] | - | [1:0] |
Bus clock gating and bus software reset registers
as extracted from clk-sun8iw10.c:
| 0x0060: BUS_CLK_GATING_REG0 | Bit | BUS_SOFT_RST_REG0: 0x02c0 |
|---|---|---|
| / | 31:30 | / |
| USBOHCI0_GATING | 29 | USBOHCI0_RST |
| / | 28:27 | / |
| USBEHCI0_GATING | 26 | USBEHCI0_RST |
| / | 25 | / |
| USBOTG_GATING | 24 | USBOTG_RST |
| / | 23 | / |
| SPI2_GATING | 22 | SPI2_RST |
| SPI1_GATING | 21 | SPI1_RST |
| SPI0_GATING | 20 | SPI0_RST |
| / | 19:16 | / |
| PSRAM_GATING | 15 | PSRAM_RST |
| SDRAM_GATING | 14 | SDRAM_RST |
| NAND_GATING | 13 | NAND_RST |
| / | 12 | / |
| SDC3_GATING | 11 | SDC3_RST |
| SDC2_GATING | 10 | SDC2_RST |
| SDC1_GATING | 9 | SDC1_RST |
| SDC0_GATING | 8 | SDC0_RST |
| / | 7 | / |
| DMA_GATING | 6 | DMA_RST |
| / | 5:0 | / |
| 0x0064: BUS_CLK_GATING_REG1 | Bit | BUS_SOFT_RST_REG1: 0x02c4 |
|---|---|---|
| / | 31:14 | / |
| EE_GATING | 13 | EE_RST |
| DE_GATING | 12 | DE_RST |
| / | 11:9 | / |
| CSI_GATING | 8 | CSI_RST |
| / | 7:5 | / |
| TCON_GATING | 4 | TCON_RST |
| / | 3:2 | / |
| / | 1 | WLAN_RST |
| / | 0 | / |
| 0x0068: BUS_CLK_GATING_REG2 | Bit | BUS_SOFT_RST_REG2: 0x02c8 |
|---|---|---|
| / | 31:14 | / |
| I2S1_GATING | 13 | I2S1_RST |
| I2S0_GATING | 12 | I2S0_RST |
| / | 11:9 | / |
| GPADC_GATING | 10 | GPADC_RST |
| KEYADC_GATING | 9 | KEYADC_RST |
| THS_GATING | 8 | THS_RST |
| / | 7 | / |
| PIO_GATING | 5 | / |
| / | 4 | / |
| DMIC_GATING | 3 | DMIC_RST |
| DSD_GATING | 2 | DSD_RST |
| SPDIF_GATING | 1 | SPDIF_RST |
| ADDA_GATING | 0 | ADDA_RST |
| 0x006c: BUS_CLK_GATING_REG3 | Bit | BUS_SOFT_RST_REG3: 0x02cc |
|---|---|---|
| / | 31:22 | / |
| UART5_GATING | 21 | UART5_RST |
| UART4_GATING | 20 | UART4_RST |
| UART3_GATING | 19 | UART3_RST |
| UART2_GATING | 18 | UART2_RST |
| UART1_GATING | 17 | UART1_RST |
| UART0_GATING | 16 | UART0_RST |
| / | 15:3 | / |
| TWI2_GATING | 2 | TWI2_RST |
| TWI1_GATING | 1 | TWI1_RST |
| TWI0_GATING | 0 | TWI0_RST |