Xunlong Orange Pi Prime
|Xunlong Orange Pi Prime|
|Dimensions||98mm x 60mm|
|Release Date||April 2017|
|Website||Orange Pi Prime Product Page|
|SoC||H5 @ XGhz|
|DRAM||2GiB DDR3 @ xxxMHz|
|Power||DC 5V @ 3A,|
|Video||HDMI (Type A/B/C - full), VGA|
|Audio||3.5mm headphone plug, 3.5mm microphone plug, HDMI, internal microphone|
|Network||WiFi 802.11 b/g/n (Realtek RTL8723BS), 10/100/1000Mbps Ethernet (Realtek RTL8211E)|
|Storage||µSD, optional SPI NOR Flash on board|
|USB||X USB2.0 Host, X USB2.0 OTG|
The PCB has the following silkscreened on it:
Orange Pi Prime v1.0
The H5 SoC support has matured since its introduction in kernel 4.12. Most of the board functionality for boards such as Orange Pi Prime are available with current mainline kernels. Some features (hw accelerated crypto, hw spinlocks, and thermal) are still being worked on and the status of some features (video engine) is still unknown due to the lack of testing. For a more comprehensive list of supported features, see the status matrix for mainline kernels.
See the Manual build section for more details.
It seems no device settings are contained and the BSP is broken anyway at least with regard to voltage regulation (that's also the reason vendor OS images seem to be limited to 1008 MHz since at this cpufreq those Orange Pi do not immediately crash with BSP kernel).
You can build things for yourself by following our Manual build howto and by choosing from the configurations available below.
Use the orangepi_prime_defconfig (supported since v2017.07) build target.
The H5 SoC has support in the mainline kernels.
The development process, links to patches and links to kernel fork repositories are listed on the Linux mainlining effort page. Patches can also be found from the arm-linux mailing list.
Repositories with H5 patches:
- Ondřej Jirman's branch for H5 based orange Pi (kernel 4.19) (work-in-progress DVFS)
- Thermal regulation (if CPU heats above certain temperature, it will try to cool itself down by reducing CPU frequency)
- HDMI audio support (from Jernej Skrabec)
- Configure on-board micro-switches to perform system power off function
- Wireguard (https://www.wireguard.com/)
Use the sun50i-h5-orangepi-prime.dtb device-tree binary.
The Orange Pi Prime has a Raspberry Pi model B+ compatible 40-pin, 0.1" connector with several low-speed interfaces.
|3||PA12 with 2k pullup (TWI0_SDA/DI_RX/PA_EINT12)||4||5V|
|5||PA11 with 2k pullup (TWI0_SCK/DI_TX/PA_EINT11)||6||GND|
|7||PA6 (SIM_PWREN/PWM1/PA_EINT6)||8||PA13 (SPI1_CS/UART3_TX/PA_EINT13)|
|21||PC1 (SPI0_MISO)||22||PA2 (UART2_RTS/JTAG_DO/PA_EINT2)|
|23||PC2 (SPI0_CLK)||24||PC3 (SPI0_CS)|
|27||PA19 with 2k pullup (PCM0_CLK/TWI1_SDA/PA_EINT19)||28||PA18 with 2k pullup (PCM0_SYNC/TWI1_SCK/PA_EINT18)|
|31||PA8 (SIM_DATA/PA_EINT8)||32||PG8 (UART1_RTS/PG_EINT8)|
|35||PA10 (SIM_DET/PA_EINT10)||36||PG9 (UART1_CTS/PG_EINT9)|
|37||PA20 (PCM0_DOUT/SIM_VPPEN/PA_EINT20)||38||PG6 (UART1_TX/PG_EINT6)|
Tips, Tricks, Caveats
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The something button triggers FEL mode.
Device specific topic
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ESD & over-current protections
Based on the schematic Rev 1.0 (September 29, 2016) the board incorporates the following protections:
x - no protection, ESD - Electrostatic Discharge, OC - Over-current
|1||Power jack||ESD (1)||x||Uses TVS diode, power supply bypass.|
|5||Dual USB1||ESD (1)||OC (1.1A)||Over-current protection provided by SY6280, 1.1A shared for both ports, power supply bypass.|
|6||USB2||ESD (1)||OC (1.1A)||Over-current protection provided by SY6280, power supply bypass.|
|6||Micro USB||ESD (1)||OC (680mA)||Over-current protection provided by SY6280, power supply bypass.|
|8||Ethernet||x||N/A||Over-current protection is not applicable|
|11||Audio jack||x||N/A||Output current is internally limited by SoC|
- On online OrangePi Prime pictures as well as on personal pictures it can be noticed that manufacturer has removed all ESD protection components on all USB ports and on I2C bus of HDMI port.
Adding a serial port
The board exposes Debug serial 3-pin port which is located between Reset and Power switches (see picture on the right). The 3-pin port layout is the following:
- CPU RX
- CPU TX
This connector is connected to UART0 using pins PA4 (TX) and PA5 (RX). Please refer to our UART howto for further details.
Also known as
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