Xunlong Orange Pi Prime

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Xunlong Orange Pi Prime
Orange Pi Prime top.jpg
Manufacturer OrangePi
Dimensions 98mm x 60mm
Release Date April 2017
Website Orange Pi Prime Product Page
Specifications
SoC H5 @ XGhz
DRAM 2GiB DDR3 @ xxxMHz
Power DC 5V @ 3A,
Features
Video HDMI (Type A/B/C - full), VGA
Audio 3.5mm headphone plug, 3.5mm microphone plug, HDMI, internal microphone
Network WiFi 802.11 b/g/n (Realtek RTL8723BS), 10/100/1000Mbps Ethernet (Realtek RTL8211E)
Storage µSD, optional SPI NOR Flash on board
USB X USB2.0 Host, X USB2.0 OTG
Camera CSI connector

Orange Pi Prime is H5 based development board produced by Xunlong. It comes with onboard gigabit Ethernet, 802.11 b/g/n WiFi + Bluetooth 4.0, HDMI, three USB 2.0 HOST, one USB 2.0 OTG.

This page needs to be properly filled according to the New Device Howto and the New Device Page guide.

Contents

Identification

The PCB has the following silkscreened on it:

Orange Pi
Prime v1.0

Sunxi support

Current status

The H5 SoC support has matured since its introduction in kernel 4.12. Most of the board functionality for boards such as Orange Pi Prime are available with current mainline kernels. Some features (hw accelerated crypto, hw spinlocks, and thermal) are still being worked on and the status of some features (video engine) is still unknown due to the lack of testing. For a more comprehensive list of supported features, see the status matrix for mainline kernels.

See the Manual build section for more details.


BSP

There are some somewhat abandoned 3.10 BSP code drops available in 'OrangePiLibra' and FriendlyELEC's github repos. Check the orangepi-xunlong and OrangePiLibra repositories in case of interest.

It seems no device settings are contained and the BSP is broken anyway at least with regard to voltage regulation (that's also the reason vendor OS images seem to be limited to 1008 MHz since at this cpufreq those Orange Pi do not immediately crash with BSP kernel).

Manual build

You can build things for yourself by following our Manual build howto and by choosing from the configurations available below.

U-Boot

Mainline U-Boot

Use the orangepi_prime_defconfig (supported since v2017.07) build target.

Linux Kernel

Sunxi/Legacy Kernel

Mainline kernel

The H5 SoC has support in the mainline kernels.

The development process, links to patches and links to kernel fork repositories are listed on the Linux mainlining effort page. Patches can also be found from the arm-linux mailing list.

Repositories with H5 patches:


Use the sun50i-h5-orangepi-prime.dtb device-tree binary.

Expansion Port

The Orange Pi Prime has a Raspberry Pi model B+ compatible 40-pin, 0.1" connector with several low-speed interfaces.

2x20 Header
1 3.3V 2 5V
3 PA12 with 2k pullup (TWI0_SDA/DI_RX/PA_EINT12) 4 5V
5 PA11 with 2k pullup (TWI0_SCK/DI_TX/PA_EINT11) 6 GND
7 PA6 (SIM_PWREN/PWM1/PA_EINT6) 8 PA13 (SPI1_CS/UART3_TX/PA_EINT13)
9 GND 10 PA14 (SPI1_CLK/UART3_RX/PA_EINT14)
11 PA1 (UART2_RX/JTAG_CK/PA_EINT1) 12 PD14
13 PA0 (UART2_TX/JTAG_MS/PA_EINT0) 14 GND
15 PA3 (UART2_CTS/JTAG_DI/PA_EINT3) 16 PC4
17 3.3V 18 PC7
19 PC0 (SPI0_MOSI) 20 GND
21 PC1 (SPI0_MISO) 22 PA2 (UART2_RTS/JTAG_DO/PA_EINT2)
23 PC2 (SPI0_CLK) 24 PC3 (SPI0_CS)
25 GND 26 PA21 (PCM0_DIN/SIM_VPPPP/PA_EINT21)
27 PA19 with 2k pullup (PCM0_CLK/TWI1_SDA/PA_EINT19) 28 PA18 with 2k pullup (PCM0_SYNC/TWI1_SCK/PA_EINT18)
29 PA7 (SIM_CLK/PA_EINT7) 30 GND
31 PA8 (SIM_DATA/PA_EINT8) 32 PG8 (UART1_RTS/PG_EINT8)
33 PA9 (SIM_RST/PA_EINT9) 34 GND
35 PA10 (SIM_DET/PA_EINT10) 36 PG9 (UART1_CTS/PG_EINT9)
37 PA20 (PCM0_DOUT/SIM_VPPEN/PA_EINT20) 38 PG6 (UART1_TX/PG_EINT6)
39 GND 40 PG7 (UART1_RX/PG_EINT7)

Tips, Tricks, Caveats

Add MANUFACTURER DEVICE specific tips, tricks, Caveats and nice to have changes here.

FEL mode

The something button triggers FEL mode.

Device specific topic

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ESD & over-current protections

Based on the schematic Rev 1.0 (September 29, 2016) the board incorporates the following protections:

Protections

x - no protection, ESD - Electrostatic Discharge, OC - Over-current

Comments
1 Power jack ESD (1) x Uses TVS diode, power supply bypass.
2 Micro SD x x
4 Camera x x
5 Dual USB1 ESD (1) OC (1.1A) Over-current protection provided by SY6280, 1.1A shared for both ports, power supply bypass.
6 USB2 ESD (1) OC (1.1A) Over-current protection provided by SY6280, power supply bypass.
6 Micro USB ESD (1) OC (680mA) Over-current protection provided by SY6280, power supply bypass.
7 HDMI ESD (1) x
8 Ethernet x N/A Over-current protection is not applicable
9 GPIO x x
10 Debug UART x  ?
11 Audio jack x N/A Output current is internally limited by SoC

Notes:

  1. On online OrangePi Prime pictures as well as on personal pictures it can be noticed that manufacturer has removed all ESD protection components on all USB ports and on I2C bus of HDMI port.

Adding a serial port

UART pins

The board exposes Debug serial 3-pin port which is located between Reset and Power switches (see picture on the right). The 3-pin port layout is the following:

  1. GND
  2. CPU RX
  3. CPU TX

This connector is connected to UART0 using pins PA4 (TX) and PA5 (RX). Please refer to our UART howto for further details.

Pictures

Also known as

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See also

OrangePi Prime Schematic V1.0

Add some nice to have links here. This includes related devices, and external links.

Manufacturer images

Optional. Add non-sunxi images in this section.

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