User:Ssvb/Primo73 DRAM Calibration

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Default DRAM settings for MSI Primo73, which are used in the stock Android firmware

static struct dram_para dram_para = {
	.clock = 384,
	.type = 3,
	.rank_num = 1,
	.density = 4096,
	.io_width = 16,
	.bus_width = 32,
	.cas = 9,
	.zq = 0x7f,
	.odt_en = 0,
	.size = 1024,
	.tpr0 = 0x42d899b7,
	.tpr1 = 0xa090,
	.tpr2 = 0x22a00,
	.tpr3 = 0,
	.tpr4 = 0,
	.tpr5 = 0,
	.emr1 = 0x4,
	.emr2 = 0x10,
	.emr3 = 0,
};

Trying low dcdc3 voltage and DRAM clocked up to 480MHz

dcdc3_vol = 1200
dram_clk = 480
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7b (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x30927790
dram_tpr1 = 0xa0b0
dram_tpr2 = 0x23200
dram_tpr3 = 0x0
dram_emr1 = 0x0
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=3]

Total number of successful memtester runs: 657

Best luminance at the height 0.5 is above 0x081111, score = 0.923
Best luminance at the height 1.0 is above 0x081111, score = 0.888
Best luminance at the height 2.0 is above 0x081111, score = 0.842
Best luminance at the height 4.0 is above 0x001111, score = 0.788

Read errors per lane: [0, 2, 1, 0]. Lane 2 is the most noisy/problematic.
Errors from the lane 1 are not intersecting with the errors from the worst lane 2.

Write errors per lane: [0, 0, 0, 0]. Lane 3 is the most noisy/problematic.

Searching for optimal "dram_emr1"

Primo73, 540MHz, emr1=0x00 (Rtt_Nom=disabled)

dcdc3_vol = 1250
dram_clk = 540
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7b (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x36948890
dram_tpr1 = 0xa0c0
dram_tpr2 = 0x23600
dram_tpr3 = 0x0
dram_emr1 = 0x0
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=21]

Total number of successful memtester runs: 330

Best luminance at the height 0.5 is above 0x002222, score = 0.651
Best luminance at the height 1.0 is above 0x002222, score = 0.541
Best luminance at the height 2.0 is above 0x002222, score = 0.458
Best luminance at the height 4.0 is above 0x002222, score = 0.403

Read errors per lane: [0, 1, 3, 0]. Lane 1 is the most noisy/problematic.
Errors from the lane 2 are not intersecting with the errors from the worst lane 1.

Write errors per lane: [0, 16, 1, 0]. Lane 2 is the most noisy/problematic.
Errors from the lane 1 are not intersecting with the errors from the worst lane 2.

Primo73, 540MHz, emr1=0x40 (Rtt_Nom=RZQ/2)

dcdc3_vol = 1250
dram_clk = 540
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7b (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x36948890
dram_tpr1 = 0xa0c0
dram_tpr2 = 0x23600
dram_tpr3 = 0x0
dram_emr1 = 0x40
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=7]

Total number of successful memtester runs: 447

Best luminance at the height 0.5 is above 0x022222, score = 0.812
Best luminance at the height 1.0 is above 0x022222, score = 0.733
Best luminance at the height 2.0 is above 0x022222, score = 0.646
Best luminance at the height 4.0 is above 0x012222, score = 0.569

Read errors per lane: [0, 2, 2, 2]. Lane 2 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 2.
Errors from the lane 1 are not intersecting with the errors from the worst lane 2.

Write errors per lane: [0, 0, 1, 0]. Lane 1 is the most noisy/problematic.

Primo73, 540MHz, emr1=0x04 (Rtt_Nom=RZQ/4)

dcdc3_vol = 1250
dram_clk = 540
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7b (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x36948890
dram_tpr1 = 0xa0c0
dram_tpr2 = 0x23600
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=8]

Total number of successful memtester runs: 430

Best luminance at the height 0.5 is above 0x022222, score = 0.807
Best luminance at the height 1.0 is above 0x022222, score = 0.726
Best luminance at the height 2.0 is above 0x022222, score = 0.636
Best luminance at the height 4.0 is above 0x012222, score = 0.554

Read errors per lane: [0, 2, 3, 2]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 1.
Errors from the lane 2 are not intersecting with the errors from the worst lane 1.

Write errors per lane: [0, 0, 1, 0]. Lane 1 is the most noisy/problematic.

Primo73, 540MHz, emr1=0x44 (Rtt_Nom=RZQ/6)

dcdc3_vol = 1250
dram_clk = 540
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7b (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x36948890
dram_tpr1 = 0xa0c0
dram_tpr2 = 0x23600
dram_tpr3 = 0x0
dram_emr1 = 0x44
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=5]

Total number of successful memtester runs: 412

Best luminance at the height 0.5 is above 0x022222, score = 0.797
Best luminance at the height 1.0 is above 0x022222, score = 0.713
Best luminance at the height 2.0 is above 0x022222, score = 0.621
Best luminance at the height 4.0 is above 0x022222, score = 0.538

Read errors per lane: [0, 2, 1, 2]. Lane 2 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 2.
Errors from the lane 1 are not intersecting with the errors from the worst lane 2.

Write errors per lane: [0, 0, 0, 0]. Lane 3 is the most noisy/problematic.

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