Xunlong Orange Pi Plus
|Xunlong Orange Pi Plus|
|Dimensions||108mm x 60mm|
|Release Date||February 2015|
|Website||Orange Pi Plus Product Page|
|SoC||H3 @ 1.3GHz|
|DRAM||1GiB DDR3 @ 672MHz (K4B4G1646Q-HYK0)|
|NAND||8GB EMMC Flash|
|Power||DC 5V @ 2A (4.0mm/1.7mm barrel plug - centre positive)|
|Video||HDMI (HDCP, CEC), CVBS|
|Audio||3.5 mm Jack, HDMI, Microphone|
|Network||10/100/1000Mbps Ethernet (Realtek RTL8211E), WiFi 802.11 b/g/n (Realtek RTL8189ETV)|
|Storage||µSD (max 64GB), SATA 2.0 (via GL830 USB-to-SATA bridge, +5V power on JST XH 2.5mm connector)|
|USB||4 USB 2.0 Host (via FE1.1s hub), 1 USB 2.0 OTG|
Orange Pi Plus is a H3 based development board produced by Xunlong, released in February 2015. It comes with onboard 8 GB eMMC flash, gigabit Ethernet, and 802.11 b/g/n WiFi, Video Outputs (HDMI with CEC, CVBS, simultaneous output to both) and a Raspberry Pi A+/B+ style 40 pin GPIO header. An upgraded version Orange Pi Plus 2 with twice the RAM and onboard flash was later released.
- 1 Identification
- 2 Sunxi support
- 3 Expansion Port
- 4 Tips, Tricks, Caveats
- 5 Adding a serial port
- 6 Pictures
- 7 Variants
- 8 Also known as
- 9 See also
The PCB has the following silkscreened on it:
Orange Pi Plus
The H3 SoC support has matured since its introduction in kernel 4.2. Most of the board functionality for boards such as Orange Pi Plus are available with current mainline kernels. Some features (hw accelerated crypto, hw spinlocks, and thermal) are still being worked on. For a more comprehensive list of supported features, see the status matrix for mainline kernels. In addition, legacy 3.4 kernels are available in various work-in-progress git branches.
See the Manual build section for more details.
You can build things for yourself by following our Manual build howto and by choosing from the configurations available below.
Use the orangepi_plus (supported since v2016.01) build target. The U-Boot repository and toolchain is described in the Mainline U-Boot howto.
The H3 boards can boot from SD cards, eMMC, NAND or SPI NOR flash (if available), and via FEL using the OTG USB port. In U-Boot, loading the kernel is also supported from USB or ethernet (netboot). HDMI support in U-Boot is still WIP.
- Siarhei Siamashka's branch '20151207-embedded-lima-memtester-h3'
- Yann Dirson's fork added a few more fixes and adopted most of
- Boris Lovosevic' great initial work on Allwinner's H3 kernel
Configure this kernel using sun8i_h3_defconfig, the rest is explained in the kernel compilation guide.
Use the .fex file for generating script.bin.
When booting the legacy 3.4 kernel with the mainline U-Boot, add the following line to boot.cmd:
setenv machid 1029 setenv bootm_boot_mode sec
Some other legacy kernel repositories:
- 3.4-lichee-based kernel, based on work by ssvb and loboris
- Yocto support here glues together all the required parts to get this kernel to work with mainline u-boot, as well as accelerated X11/GLES support
- A newer H3 BSP variant appeared with tons of fixes which has been made available by FriendlyARM.
- A cleaned up fork has been adopted by Armbian project. On top of that Armbian maintains a bunch of 3.4.x patches for H3 devices.
The mainline kernel has good support for the H3 SoC. Please refer to the status matrix for a more detailed list of the development process, links to patches and links to kernel fork repositories. Minor drivers that are currently work-in-progress may require a) third party patches (see also arm-linux mailing list) or b) a pre-patched distro (e.g. Armbian).
Repositories with H3 patches:
- Ondřej Jirman's branch for H3 based orange Pi (kernel 4.19) (work-in-progress DVFS)
- Thermal regulation (if CPU heats above certain temperature, it will try to cool itself down by reducing CPU frequency)
- HDMI audio support (from Jernej Skrabec)
- Configure on-board micro-switches to perform system power off function
- Wireguard (https://www.wireguard.com/)
- Philipp Rossak's THS patches (in the sunxi-ths- branches)
- Corentin Labbe's HW Crypto and spinlock patches (in respective branches)
Use the sun8i-h3-orangepi-plus.dtb device-tree binary.
The Orange Pi Plus has a Raspberry Pi model B+ compatible 40-pin, 0.1" connector with several low-speed interfaces.
|7||PA6 (SIM_PWREN/PWM1/PA_EINT6)||8||PA13 (SPI1_CS/UART3_TX/PA_EINT13)|
|21||PC1 (SPI0_MISO)||22||PA2 (UART2_RTS/JTAG_DO/PA_EINT2)|
|23||PC2 (SPI0_CLK)||24||PC3 (SPI0_CS)|
|27||PA19 (PCM0_CLK/TWI1_SDA/PA_EINT19)||28||PA18 (PCM0_SYNC/TWI1_SCK/PA_EINT18)|
|31||PA8 (SIM_DATA/PA_EINT8)||32||PG8 (UART1_RTS/PG_EINT8)|
|35||PA10 (SIM_DET/PA_EINT10)||36||PG9 (UART1_CTS/PG_EINT9)|
|37||PA20 (PCM0_DOUT/SIM_VPPEN/PA_EINT20)||38||PG6 (UART1_TX/PG_EINT6)|
Tips, Tricks, Caveats
The button marked SW3, located between the HDMI and SATA, triggers FEL mode when pressed during boot. (SW3 pulls the H3 BOOTSEL pin to low level.)
To verify you have successfully entered FEL mode, check the output of
fel version. For the Orange Pi Plus, it should look like:
AWUSBFEX soc=00001680(unknown) 00000001 ver=0001 44 08 scratchpad=00007e00 00000000 00000000
For those with a transparent case (or no case at all) the Orange Pi Plus's LED activity is good. The red power LED (D7) can be turned off.
Be aware that the H3 SoC used on the Orange Pi Plus isn't SATA capable and therefore the SATA port is provided by a slow USB-to-SATA-bridge (especially write speeds are substandard and do not exceed 15 MB/s). This means you can neither expect SATA performance nor full SATA functionality. While the used GL830 bridge supports S.M.A.R.T. attributes it does not support S.M.A.R.T. status notification (overall health indicator of the disk – instead of PASSED or FAILED you will only get SMART Status not supported: Incomplete response, ATA output registers missing).
If you wish to connect a SATA drive (2.5" mobile harddisk or SSD) to the Orange Pi Plus: Make sure your power supply is connected to the "DC-IN" port, and can deliver sufficient current (e.g. 5V/2000mA). Using the OTG port or an inadequate power supply might result in your board not being working. You should also note that the board's SATA-power connector uses the same polarity as other Orange or Banana Pis. Therefore cable kits from CubieTech and LinkSprite that use the same jack are incompatible due to inverted polarity.
DRAM clock speed limit
DRAM is clocked at 672 MHz by the hardware vendor. But the reliability still needs to be verified. One of the ways of doing reliability tests may be https://github.com/ssvb/lima-memtester/releases/tag/20151207-orange-pi-pc-fel-test (it checks the Orange Pi PC DRAM setup in the current mainline U-Boot v2016.01-rc2 + a bugfix).
NOTE: While this test image was made for the Orange Pi PC, it also runs on the Orange Pi Plus.
|Hardware||Diagnostic software||lima-memtester passes (survives until the red LED)||lima-memtester fails||Notes|
|User:Camh's Orange Pi Plus 1||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||720 MHz||744 MHz||Heatsink (35mmx25mm) covering SoC and RAM. 744MHz only failed when left running overnight. It made it to the red LED.|
|User:Camh's Orange Pi Plus 2||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||696 MHz||720 MHz||Heatsink (35mmx25mm) covering SoC and RAM. 720MHz failed in < 30s.|
|User:Camh's Orange Pi Plus 3||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||720 MHz||744 MHz||Heatsink (35mmx25mm) covering SoC and RAM. 744MHz failed in < 30s.|
|User:Camh's Orange Pi Plus 4||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||672 MHz||696 MHz||Heatsink (35mmx25mm) covering SoC and RAM. 696MHz failed in > 4 hrs. It made it to the red LED.|
|User:Jemk's Orange Pi Plus||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||768 MHz||792 MHz||Small Heatsink (15mmx15mm). 792 MHz fails in SPL, but 768 MHz passes overnight run. I don't know if these results can be trusted.|
|User:Rellla's Orange Pi Plus||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||720 MHz||744 MHz||No Heatsink. Up to 720 MHz passed until red led.|
|User:von fritz's Orange Pi Plus||fel-boot-lima-memtester-on-orange-pi-pc-v3.tar.gz||768 MHz||792 MHz||Heatsink (20mmx20mm). Up to 768 MHz passed until red led, 792 MHz fails with libusb usb_bulk_send error -9.|
See the Orange Pi PC DRAM clock speed limit for how to perform an analysis of these results.
DRAM clock speed limit (automated statistical analysis)Updating the analysis report:
wget https://raw.githubusercontent.com/ssvb/lima-memtester/master/lima-memtester-genchart ruby lima-memtester-genchart https://linux-sunxi.org/Xunlong_Orange_Pi_Plus # copy/paste the script output into the linux-sunxi wiki
|DRAM clock speed||Percentage of boards failing the lima-memtester test||Theoretical pessimistic upper bound of the failure percentage using Chebyshev's inequality for lower semivariance ||Histogram|
|Experimental results||Theoretical prediction (assuming Gaussian distribution) |
|528 MHz||0.00 % (0/7)||0.00 %||1.33 %|
|552 MHz||0.00 % (0/7)||0.00 %||1.70 %|
|576 MHz||0.00 % (0/7)||0.00 %||2.25 %|
|600 MHz||0.00 % (0/7)||0.01 %||3.12 %|
|624 MHz||0.00 % (0/7)||0.08 %||4.61 %|
|648 MHz||0.00 % (0/7)||0.64 %||7.48 %|
|672 MHz||0.00 % (0/7)||3.55 %||14.22 %|
|696 MHz||14.29 % (1/7)||13.09 %||36.80 %||*|
|720 MHz||28.57 % (2/7)||33.03 %||100.00 %||*|
|744 MHz||71.43 % (5/7)||59.64 %||100.00 %||***|
|768 MHz||71.43 % (5/7)||82.31 %||100.00 %|
|792 MHz||100.00 % (7/7)||94.63 %||100.00 %||**|
|816 MHz||100.00 % (7/7)||98.91 %||100.00 %|
|840 MHz||100.00 % (7/7)||99.85 %||100.00 %|
- If nothing is known about the distribution of samples, then at least Chebyshev's inequality can be used to get a rough idea about the probabilities of encountering reliability problems at different DRAM clock speeds. But this method is very conservative and substantially overestimates probabilities (being too generic has its price).
We can assume that the Gaussian distribution
is a good approximation for our experimental data, calculate theoretical probabilities and do an
exact test of goodness-of-fit
to see if the experimental data does not contradict with the theory.
There is a nice XNomial
library for R, which can do the job:
P value (LLR) = 0.5425 P value (Prob) = 0.5506 P value (Chisq) = 0.6407
Adding a serial port
TODO: The section is mostly a copy&paste from the "Banana Pi" page. Some of it may be incorrect, or might not apply to this device. Please review / rework the information, and remove this reminder when done.
While the GPIO pinout of the Orange Pi Plus is designed to be compatible to the Raspberry Pi, it's important to notice subtle differences in the serial ports. The Orange Pi Plus has some additional pins that already provide two more serial ports.
The default serial port /dev/ttyS0, used for (bootstrap) debugging and the serial console, is located at J11 - refer to the picture and instructions below. The Raspberry's "original" serial port on GPIO 14 and 15 (CON3, pins 8 and 10) can usually be accessed as /dev/ttyS2 on the Orange Pi Plus. J12 also provides another serial port on pins 4 (RX) and 6 (TX), which should map to /dev/ttyS3.
Note: The actual mapping between physical pins, UART numbers and/or device names may depend on the specific kernel and configuration used. If in doubt, check the boot messages:
dmesg | grep -i uart
Locating the UART
The UART pins are located between MIC and audio input of the board. They are marked as TX, RX and GND on the PCB. Just attach some leads according to our UART Howto.
- The original Orange Pi was released in November 2014. The Orange Pi features a standard TF card slot and a 26 pin GPIO connector (similar to the Raspberry Pi A/B).
- An upgraded version Orange Pi Plus 2 with twice the RAM and onboard flash was later released.
Also known as
There are several websites about Orange Pi Plus and claiming to support it. It has to be clarified, what is "official" and who is behind this sites.
- Xunlong Orange Pi site
- "Official" Github Repository.
- "Official" Orange Pi Form.
A various amount of prebuilt images is provided via OrangePi's Website.