V853

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V853
V853.PNG
Manufacturer Allwinner
Process 22nm
CPU ARM Cortex-A7
RISC-V E907 RV32IMA
Extensions NEON, VFPv4
Memory 16bit DDR3,DDR3L
VPU Decoding: 5M @ 25 FPS
H264
Encoding: 5M @ 25 FPS
H.265/H.264
Connectivity
Video Out: MIPI / RGB LCD
In: MIPI CSI / DVP /
Parallel CSI up to 16 bit
ISP 5M @ 30FPS
VIPP 5M @ 30FPS
Audio DAC / ADC / CODEC / 2x I2S-PCM / DMIC
Network 10/100/1000M EMAC
Storage SDIO 3.0, eMMC 5.1, SPI NOR/NAND Flash
USB USB2.0 DRD
Other 1T NPU, Support TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, and so on...
G2D, Display Engine
SDIO, 4x SPI, 4x UART, 5x I2C, PWM, WIEGAND IN, GPADC
LFBGA, 318 pins

This page is still under construction.

Overview

V853 is a new generation of high-performance and low-power processor SoC targeted for the field of intelligent vision. It can be widely used in intellectually upgraded industries such as intelligent door lock, intelligent attendance and access control, webcam, tachograph, and intelligent desk lamp. V853 integrates the single Cortex-A7 core and RISC-V core. It is also designed with a new generation of high-performance ISP image processor and Allwinner Smart video engine with maximum [email protected] H.265/H.264 encoding and [email protected] H.264 decoding to achieve professional picture effect. It has built-in NPU with maximum 1T computing power and supports INT8/INT16 hybrid operation and typical network models such as TensorFlow/MXNet/PyTorch/Caffe. V853 has advanced 22nm technics to support product miniaturization design. It also supports various special video input and output interfaces such as 1*4-lane MIPI/DVP/MIPI-DSI/RGB to meet the needs of all AI visual products. V853 supports 16-bit DDR3/DDR3L to meet the requirements of various products on high bandwidth.

V853 SoC Features

  • CPU Architecture
    • Cortex-A7 CPU core, supporting 32 KB I-cache, 32 KB D-cache, and 128 KB L2 cache
    • RISC-V core, supporting 16 KB I-cache and 16 KB D-cache
  • NPU Architecture
    • Maximum performance up to 1 Tops for V853 and 0.8 Tops for V853S
    • Embedded 128KB internal buffer
    • Supports deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, and so on
  • Video Encoding/Decoding Performance
    • H.264 BP/MP/HP encoding
    • H.265 MP encoding
    • H.264/H.265 supports I/P frame type
    • MJPEG/JPEG baseline encoding
    • H.264/JPEG decoding
    • Maximum resolution for H.264/H.265 decoding is 16 megapixels (4096x4096)
    • A maximum of eight ROIs
    • CBR, VBR and FIXEDQP modes
    • JPEG encder supports [email protected]@400MHz
    • H.264/H.265 encoder supports [email protected]@400MHz
    • H.264/H.265 multi-stream real-time encoding capability: [email protected] + [email protected]
  • Video Output
    • MIPI DSI
      • Compliance with MIPI DSI V1.02 and MIPI DPHY V1.2
      • Supports 4-lane MIPI DSI, up to 1920 x [email protected]
      • Supports normal mode and burst mode
      • Up to 1.0 Gbps/Lane
    • TCONLCD
  • Video Input
    • ISP
      • Supports 1 individual image signal processor(ISP), with maximum resolution of 3072 x 3072 (online mode)
      • Maximum frame rate of [email protected]
      • Supports offline mode
      • Supports WDR spilt, 2F-WDR line-based stitch, dynamic range compression (DRC), tone mapping, digital gain, gamma correction, defect pixel correction (DPC), cross talk correction (CTC), and chromatic aberration correction (CAC)
      • Supports 2D/3D noise reduction, bayer interpolation, sharpen, white balance, and color enhancement
      • Adjustable 3A funtions: automatic white balance (AWB), automatic exposure (AE), and automatic focus (AF)
      • Supports anti-flick detection statistics, and histogram statistics
      • Supports graphics mirror and flip
    • VIPP
      • Four VIPP YUV422 or YUV420 outputs
      • Maximum resolution of 3072x3072
      • Each VIPP has one sub-VIPP in online mode
      • Each VIPP has maximum four sub-VIPPs for time division multiplexing in offline mode
      • Functions for each Sub-VIPP
        • Crop
        • 1 to 1/16 scaling for height and width
        • 16 ORLs
    • Parallel CSI
      • Supports 8/10/12/16-bit width
      • Supports BT.656, BT.601, BT.1120 interface
      • Maximum pixel clock for parallel to 148.5MHz
      • Supports ITU-R BT.656 up to 4*[email protected]
      • Supports ITU-R BT.1120 up to 4*[email protected]
    • MIPI CSI
      • Supports one 4-lane MIPI CSI input or two 2-lane MIPI CSI inputs
      • Compliant with MIPI CSI2 V1.1 and MIPI DPHY V1.1
      • Up to 1.2 Gbps/Lane
      • maximum video capture resolution for serial interface up to [email protected]
  • Audio Subsystem
    • Audio Codec
      • One audio digital-to-analog converter (DAC) channels
        • Supports 16-bit and 20-bit sample resolution
        • 8 kHz to 192 kHz DAC sample rate
        • 95 ± 2 dB [email protected], -85 ± 3 dB THD+N
      • Two audio analog-to-digital converter (ADC) channels
        • Supports 16-bit and 20-bit sample resolution
        • 8 kHz to 48 kHz ADC sample rate
        • 95 ± 3dB [email protected], -80 ± 3dB THD+N
      • Two audio inputs:
        • Two differential microphone inputs: MICIN1P/N, MICIN2P/N
      • One audio output:
        • One differential lineout output (LINEOUTP/LINEOUTN)
      • Supports Dynamic Range Controller adjusting the DAC playback and ADC recording
      • One 128x20-bits FIFO for DAC data transmit, one 128x20-bits FIFO for ADC data receive
      • Programmable FIFO thresholds
      • Supports interrupts and DMA
  • I2S
    • Two I2S/PCM external interfaces (I2S0, I2S1) for connecting external power amplifier and MIC ADC
    • Compliant with standard Philips Inter-IC sound (I2S) bus specification
      • Left-justified, Right-justified, PCM mode, and Time Division Multiplexing (TDM) format
      • Programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)
    • Transmit and Receive data FIFOs
      • Programmable FIFO thresholds
      • 128 depth x 32-bit width TXFIFO and 64 depth x 32-bit width RXFIFO
    • Supports multiple function clock
      • Clock up to 24.576 MHz Data Output of I2S/PCM in Master mode (Only if the IO PAD and Peripheral I2S/PCM satisfy Timing Parameters)
      • Clock up to 12.288 MHz Data Input of I2S/PCM in Master mode
    • Supports TX/RX DMA Slave interface
    • Supports multiple application scenarios
      • Up to 16 channels (fs = 48 kHz) which has adjustable width from 8-bit to 32-bit
      • Sample rate from 8 kHz to 384 kHz (CHAN = 2)
      • 8-bit u-law and 8-bit A-law companded sample
    • Supports master/slave mode
    • DMIC
      • Supports maximum 8 digital PDM microphones
      • Supports sample rate from 8 kHz to 48 kHz
  • External Peripherals
    • Five TWI interfaces
    • Four UART interfaces
    • Four SPI interfaces
    • Eight GPIO interfaces
    • Four channels general purpose analog-to-digital converter(GPADC)
    • One PWM controller(12-ch)

Documentation

Devices

References

External Links