User:Xalius

From linux-sunxi.org
Jump to navigation Jump to search

Allwinner SoC Camera Interfaces

TODO: Write intro here

Overview

Allwinner SoC can provide a camera interface (CSI) with different physical layers as well an Image Signal Processor (ISP) and a Camera Control Interface (CCI). Documentation is only partly available, see below.

  • A10
    • "Dual Camera Sensor Interface (CSI0 supports ISP function)"
      • CSI0 (Register Info available)
        • 8 bit input data
        • Support CCIR656 protocol for NTSC and PAL
        • 3 parallel data paths for image stream parsing
        • Received data double buffer support
        • Parsing BAYER data into planar R, G, B output to memory
        • Parsing interlaced data into planar or tie-based YCbCr output to memory
        • Pass raw data direct to memory
        • All data transmit timing can be adjusted by software
        • support multi-channel ITU-R BT.656 time-multiplexed format
        • luminance statistical value
        • support 8-bit raw data input
        • support 16-bit YUV422 data input
      • ISP FE (Register Info available)
        • Digital clamp with horizontal/vertical offset compensation
        • Lens shading correction
        • Color dependent gain control and black level offset control
        • Dark frame subtract of raw image stored
        • AE/AF/AWB statistics
        • Histogram statistics
        • DC subtract for Y channel
        • LUT Defect Pixel correction
        • Double buffer for enable and output address registers
      • CSI1 (Register Info available)
        • 8 bits input data
        • Support CCIR656 protocol for NTSC and PAL
        • 3 parallel data paths for image stream parsing
        • Received data double buffer support
        • Parsing BAYER data into planar R, G, B output to memory
        • Parsing interlaced data into planar or tie-based YCbCr output to memory
        • Pass raw data direct to memory
        • All data transmit timing can be adjusted by software
        • support multi-channel ITU-R BT.656 time-multiplexed format
        • luminance statistical value
        • support 10-bit raw data input
        • support 24-bit RGB/YUV 444 input, interlace/progressive mode, pixel clock up to 148.5(1080p)
  • A13
    • "Support 8bit CMOS sensor parallel interface"
    • "Support CCIR656 protocol for NTSC and PAL"
      • CSI (Register Info available)
        • 8-bit input data
        • Support CCIR656 protocol for NTSC and PAL
        • 3 parallel data paths for image stream parsing
        • Support Received data double buffer
        • Parsing bayer data into planar R, G, B output to memory
        • Parsing interlaced data into planar or MB Y, Cb, Cr output to memory
        • Pass raw data direct to memory
        • All data transmit timing can be adjusted by software
        • Luminance statistical value
  • A20
    • "Dual CMOS sensor parallel interfaces that support YUV format only"
    • "CSI0 up to 1080p@30fps"
    • "CSI1 up to 720p@30fps"
      • CSI0 (Register Info available, seems same as A10 without ISP)
        • 8 bits input data
        • Support CCIR656 protocol for NTSC and PAL
        • 3 parallel data paths for image stream parsing
        • Received data double buffer support
        • Parsing bayer data into planar R, G, B output to memory
        • Parsing interlaced data into planar or tiled Y, Cb, Cr output to memory
        • Pass raw data direct to memory
        • All data transmit timing can be adjusted by software
        • Support multi-channel ITU-R BT656 time-multiplexed format
        • Luminance statistical value
        • Support 8-bit raw data input
        • Support 16-bit YUV422 data input
      • CSI1 (Register Info available, seems same as A10)
        • 8 bits input data
        • Support CCIR656 protocol for NTSC and PAL
        • 3 parallel data paths for image stream parsing
        • Received data double buffer support
        • Parsing bayer data into planar R, G, B output to memory
        • Parsing interlaced data into planar or tiled Y, Cb, Cr output to memory
        • Pass raw data direct to memory
        • All data transmit timing can be adjusted by software
        • Support multi-channel ITU-R BT.656 time-multiplexed format
        • Luminance statistical value
        • Support 10-bit raw data input
        • Support 24-bit RGB/YUV 444 input, interlace/progressive mode, pixel clock up to 148.5(1080p)
  • A31
    • "Support 4 lanes MIPI CSI, 1G bps per lane (up to 12M pixels still image or 1080p@60fps video)
    • "Support parallel 12bits CSI"
    • "Image Signal Processor"
      • CSI0 (Register Info available)
        • Support CMOS-sensor parallel interface with HREF and VSYNC
        • Support CCIR656 protocol for NTSC and PAL
        • Support multi-channel ITU-R BT.656 time-multiplexed format
        • Support 8/10/12bit raw data input
        • Support 8/10 bit yuv422 data input
        • Pass raw data direct to memory or to ISP
        • Parsing YUV data into planar or semi-planar output to memory
        • Support CMOS-sensor and TV decoder
        • Support up to 1080p@30fps or 5M@15fps using SOC CMOS-sensor with YUV format
        • Support up to 1080p@60fps or 5M@30fps using CMOS-sensor with RAW format
      • CSI1 (Register Info available)
        • Support CMOS-sensor parallel interface with HREF and VSYNC
        • Support CCIR656 protocol for NTSC and PAL
        • Support multi-channel ITU-R BT.656 time-multiplexed format
        • Support 8/10/12bit raw data input
        • Support 8/10 bit yuv422 data input
        • Pass raw data direct to memory or to ISP
        • Parsing YUV data into planar or semi-planar output to memory
        • Support CMOS-sensor and TV decoder
        • Support up to 1080p@30fps or 5M@15fps using SOC CMOS-sensor with YUV format
        • Support up to 1080p@60fps or 5M@30fps using CMOS-sensor with RAW format
      • MIPI-CSI (Register Info available)
        • Comply with MIPI SPEC for D-PHY v0.90.00
        • Comply with MIPI SPEC for Camera Serial Interface 2(CSI-2) v1.01.00
        • 1/2/3/4 Data Lanes Configuration
        • Up to 1Gbps per Lane in HS Transmission at 1 or 2 data lane mode
        • Up to 600Mbps per lane in HS Transmission at 4 data lane mode
        • SupportYUV422-8bit/10bit,YUV420-8bit/10bit,RAW-8,RAW-10,RAW-12,RGB888,RGB565 formats
        • Support up to 12M CMOS-sensor
        • Up to 720p@30fps or 1080p@15fps with one data Lane
        • Up to 1080p@30fps or 5M@15fps with two data Lanes
        • Up to 1080p@60fps or 5M@30fps with four data Lanes
        • Maximum to 4 data type interleaving in one channel
        • Maximum to 4 virtual channel interleaving with one data type
      • ISP (No register info available)
        • Support multiple input formats, including 8/10/12 bits RAM RGB, 8/10 bits YCbCr
        • Support multiple output formats, includingYCbCr 420 semi-planar, YCrCb 420 semi-planar, YCbCr 422 semi-planar, YCrCb 422 semi-planar, YUV 420 planar, YUV 422 planar
        • Support image mirror flip and rotation;
        • Support thumb image generation;
        • Support two channels output;
        • Support valid picture size up to 4096x4096;
        • Support speed up to 250Mpixel/s;
        • ISP for YCbCr input
        • ISP for RAW RGB input
        • YCbCr gain and offset control
        • DRC(dynamic range compression)
        • Anti-flick detection statistics
        • Histogram statistics
        • Black clamp with horizontal/vertical offset compensation
        • Window capture
        • Static/dynamic defect pixel correction
        • Super lens shading correction
        • Super lens flare correction
        • Color dependent gain and offset control
        • Anisotropic non-linear bayer interpolation with false color suppression
        • Programmable color correction
        • Programmable gamma correction
        • DRC(dynamic range compression)
        • RGB2YCbCr
        • Non-linear 2D sharpening
        • Advanced contrast enhancement
        • Advanced spatial (2D) de-noise filter
        • Zone-based AE/AF/AWB statistics
        • Anti-flick detection statistics
        • Histogram statistics


Interface/Block A10 A13 A20 A31 A33
CSI0 yes yes yes yes
parallel yes yes yes yes
MIPI-CSI2 no no no yes
CSI1 yes no yes yes
parallel yes no yes yes
MIPI-CSI2 no no no yes
CCI no no no no yes
ISP yes no no yes

Current Development Efforts

MIPI-CSI2 Register Info

ISP Register Info

Retrieved from "https://linux-sunxi.org/index.php?title=User:Xalius&oldid=21715"