Contents
- 1 DRAM clock speed limit with the default settings
- 1.1 #1 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]
- 1.2 #2 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]
- 1.3 #3 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]
- 1.4 #4 pcDuino2, NANYA DDR3 432MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]
- 2 DRAM clock speed limit with tuned settings
- 2.1 Tests with 480MHz DRAM clock speed
- 2.2 #1 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.3 #2 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.4 #3 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.5 #4 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.6 Tests with 504MHz DRAM clock speed
- 2.7 #1 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.8 #2 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.9 #3 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
- 2.10 #4 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
DRAM clock speed limit with the default settings
Below are a10-tpr3-scan results from four LinkSprite pcDuino2 boards with NANYA DDR3 chips. Three boards (#1, #2 and #3) fail the lima-memtester check at 456MHz and one board (#4) fails it at just 432MHz. It means that the 408MHz DRAM clock speed, selected by LinkSprite for this board can be considered a safe choice.
#1 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]
dcdc3_vol = 1250 dram_clk = 456 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 6 dram_zq = 0x7b (0x6b96900) dram_odt_en = 0 dram_tpr0 = 0x30926692 dram_tpr1 = 0x1090 dram_tpr2 = 0x1a0c8 dram_tpr3 = 0x0 dram_emr1 = 0x0 dram_emr2 = 0x0 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 0 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
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0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=60, solidbits=2]
Total number of successful memtester runs: 186
Best luminance at the height 0.5 is above 0x052222, score = 0.713 Best luminance at the height 1.0 is above 0x051111, score = 0.593 Best luminance at the height 2.0 is above 0x051111, score = 0.459 Best luminance at the height 4.0 is above 0x051111, score = 0.333
Read errors per lane: [10, 3, 4, 8]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are 12.5% eclipsed by the worst lane 3. Errors from the lane 1 are 25.0% eclipsed by the worst lane 3. Errors from the lane 2 are not intersecting with the errors from the worst lane 3.
Write errors per lane: [7, 27, 15, 16]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 25.0% eclipsed by the worst lane 2. Errors from the lane 1 are 33.3% eclipsed by the worst lane 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2.
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#2 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]
dcdc3_vol = 1250 dram_clk = 456 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 6 dram_zq = 0x7b (0x6b96900) dram_odt_en = 0 dram_tpr0 = 0x30926692 dram_tpr1 = 0x1090 dram_tpr2 = 0x1a0c8 dram_tpr3 = 0x0 dram_emr1 = 0x0 dram_emr2 = 0x0 dram_emr3 = 0x0 dqs_gating_delay = 0x06060506 active_windowing = 0 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=47, solidbits=7]
Total number of successful memtester runs: 282
Best luminance at the height 0.5 is above 0x041111, score = 0.786 Best luminance at the height 1.0 is above 0x041111, score = 0.693 Best luminance at the height 2.0 is above 0x041111, score = 0.582 Best luminance at the height 4.0 is above 0x041111, score = 0.461
Read errors per lane: [2, 3, 4, 4]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 25.0% eclipsed by the worst lane 1. Errors from the lane 2 are not intersecting with the errors from the worst lane 1. Errors from the lane 3 are not intersecting with the errors from the worst lane 1.
Write errors per lane: [2, 13, 21, 26]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 57.1% eclipsed by the worst lane 0. Errors from the lane 2 are 46.2% eclipsed by the worst lane 0. Errors from the lane 3 are 50.0% eclipsed by the worst lane 0.
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#3 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]
dcdc3_vol = 1250 dram_clk = 456 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 6 dram_zq = 0x7b (0x73d1800) dram_odt_en = 0 dram_tpr0 = 0x30926692 dram_tpr1 = 0x1090 dram_tpr2 = 0x1a0c8 dram_tpr3 = 0x0 dram_emr1 = 0x0 dram_emr2 = 0x0 dram_emr3 = 0x0 dqs_gating_delay = 0x06050506 active_windowing = 0 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=44, solidbits=5]
Total number of successful memtester runs: 345
Best luminance at the height 0.5 is above 0x031111, score = 0.814 Best luminance at the height 1.0 is above 0x031111, score = 0.734 Best luminance at the height 2.0 is above 0x031111, score = 0.638 Best luminance at the height 4.0 is above 0x031111, score = 0.530
Read errors per lane: [0, 4, 6, 8]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are not intersecting with the errors from the worst lane 0. Errors from the lane 2 are not intersecting with the errors from the worst lane 0.
Write errors per lane: [3, 3, 31, 6]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.
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#4 pcDuino2, NANYA DDR3 432MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]
dcdc3_vol = 1250 dram_clk = 432 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 6 dram_zq = 0x7b (0x6b91800) dram_odt_en = 0 dram_tpr0 = 0x30926692 dram_tpr1 = 0x1090 dram_tpr2 = 0x1a0c8 dram_tpr3 = 0x0 dram_emr1 = 0x0 dram_emr2 = 0x0 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 0 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=36, solidbits=9]
Total number of successful memtester runs: 456
Best luminance at the height 0.5 is above 0x041111, score = 0.894 Best luminance at the height 1.0 is above 0x041111, score = 0.844 Best luminance at the height 2.0 is above 0x041111, score = 0.770 Best luminance at the height 4.0 is above 0x031111, score = 0.668
Read errors per lane: [0, 6, 0, 0]. Lane 2 is the most noisy/problematic.
Write errors per lane: [1, 32, 6, 16]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 56.2% eclipsed by the worst lane 2. Errors from the lane 1 are 66.7% eclipsed by the worst lane 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2.
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DRAM clock speed limit with tuned settings
Tests with 480MHz DRAM clock speed
#1 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 480 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x32b27790 dram_tpr1 = 0xa0c0 dram_tpr2 = 0x23200 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
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0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=19, solidbits=6]
Total number of successful memtester runs: 579
Best luminance at the height 0.5 is above 0x001111, score = 0.914 Best luminance at the height 1.0 is above 0x001111, score = 0.874 Best luminance at the height 2.0 is above 0x001111, score = 0.820 Best luminance at the height 4.0 is above 0x011111, score = 0.749
Read errors per lane: [0, 7, 2, 2]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2.
Write errors per lane: [0, 3, 13, 10]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 90.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
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#2 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 480 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x32b27790 dram_tpr1 = 0xa0c0 dram_tpr2 = 0x23200 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=25, solidbits=9]
Total number of successful memtester runs: 446
Best luminance at the height 0.5 is above 0x021111, score = 0.879 Best luminance at the height 1.0 is above 0x021111, score = 0.823 Best luminance at the height 2.0 is above 0x021111, score = 0.746 Best luminance at the height 4.0 is above 0x021111, score = 0.646
Read errors per lane: [4, 2, 1, 1]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 3. Errors from the lane 1 are not intersecting with the errors from the worst lane 3. Errors from the lane 2 are not intersecting with the errors from the worst lane 3.
Write errors per lane: [0, 0, 8, 25]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 87.5% eclipsed by the worst lane 0.
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#3 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 480 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x32b27790 dram_tpr1 = 0xa0c0 dram_tpr2 = 0x23200 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=14, solidbits=3, bitspread=2]
Total number of successful memtester runs: 651
Best luminance at the height 0.5 is above 0x081111, score = 0.938 Best luminance at the height 1.0 is above 0x081111, score = 0.909 Best luminance at the height 2.0 is above 0x001111, score = 0.867 Best luminance at the height 4.0 is above 0x001111, score = 0.812
Read errors per lane: [0, 6, 0, 5]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2.
Write errors per lane: [0, 0, 8, 0]. Lane 1 is the most noisy/problematic.
|
#4 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 480 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x32b27790 dram_tpr1 = 0xa0c0 dram_tpr2 = 0x23200 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=36, solidbits=10]
Total number of successful memtester runs: 350
Best luminance at the height 0.5 is above 0x051111, score = 0.836 Best luminance at the height 1.0 is above 0x051111, score = 0.763 Best luminance at the height 2.0 is above 0x041111, score = 0.670 Best luminance at the height 4.0 is above 0x041111, score = 0.557
Read errors per lane: [0, 4, 0, 0]. Lane 2 is the most noisy/problematic.
Write errors per lane: [0, 0, 42, 13]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
|
Tests with 504MHz DRAM clock speed
#1 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 504 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x34d37790 dram_tpr1 = 0xa0d0 dram_tpr2 = 0x23600 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=17, solidbits=16]
Total number of successful memtester runs: 428
Best luminance at the height 0.5 is above 0x021111, score = 0.860 Best luminance at the height 1.0 is above 0x021111, score = 0.798 Best luminance at the height 2.0 is above 0x021111, score = 0.718 Best luminance at the height 4.0 is above 0x021111, score = 0.621
Read errors per lane: [0, 7, 4, 6]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 16.7% eclipsed by the worst lane 2. Errors from the lane 1 are 25.0% eclipsed by the worst lane 2.
Write errors per lane: [0, 3, 20, 15]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
|
#2 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 504 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x34d37790 dram_tpr1 = 0xa0d0 dram_tpr2 = 0x23600 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=36, bitflip=8, xor=1]
Total number of successful memtester runs: 283
Best luminance at the height 0.5 is above 0x041111, score = 0.786 Best luminance at the height 1.0 is above 0x041111, score = 0.694 Best luminance at the height 2.0 is above 0x041111, score = 0.583 Best luminance at the height 4.0 is above 0x041111, score = 0.463
Read errors per lane: [3, 0, 0, 3]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 3.
Write errors per lane: [0, 2, 15, 39]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 100.0% eclipsed by the worst lane 0. Errors from the lane 2 are 100.0% eclipsed by the worst lane 0.
|
#3 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 504 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x34d37790 dram_tpr1 = 0xa0d0 dram_tpr2 = 0x23600 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=19, solidbits=10, bitspread=1]
Total number of successful memtester runs: 472
Best luminance at the height 0.5 is above 0x001111, score = 0.875 Best luminance at the height 1.0 is above 0x011111, score = 0.818 Best luminance at the height 2.0 is above 0x011111, score = 0.745 Best luminance at the height 4.0 is above 0x011111, score = 0.656
Read errors per lane: [0, 9, 1, 4]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2.
Write errors per lane: [0, 0, 17, 2]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
|
#4 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]
dcdc3_vol = 1250 dram_clk = 504 mbus_clk = 0 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 7 dram_zq = 0x2135e00 dram_odt_en = 3 dram_tpr0 = 0x34d37790 dram_tpr1 = 0xa0d0 dram_tpr2 = 0x23600 dram_tpr3 = 0x61111 dram_emr1 = 0x42 dram_emr2 = 0x8 dram_emr3 = 0x0 dqs_gating_delay = 0x05050505 active_windowing = 1 | |
mfxdly | phase=36 | phase=54 | phase=72 | phase=90 | phase=108 | phase=126 |
---|
0x07 | 0x073333 | 0x072222 | 0x071111 | 0x070000 | 0x07EEEE | 0x07DDDD |
---|
0x06 | 0x063333 | 0x062222 | 0x061111 | 0x060000 | 0x06EEEE | 0x06DDDD |
---|
0x05 | 0x053333 | 0x052222 | 0x051111 | 0x050000 | 0x05EEEE | 0x05DDDD |
---|
0x04 | 0x043333 | 0x042222 | 0x041111 | 0x040000 | 0x04EEEE | 0x04DDDD |
---|
0x03 | 0x033333 | 0x032222 | 0x031111 | 0x030000 | 0x03EEEE | 0x03DDDD |
---|
0x02 | 0x023333 | 0x022222 | 0x021111 | 0x020000 | 0x02EEEE | 0x02DDDD |
---|
0x01 | 0x013333 | 0x012222 | 0x011111 | 0x010000 | 0x01EEEE | 0x01DDDD |
---|
0x00 | 0x003333 | 0x002222 | 0x001111 | 0x000000 | 0x00EEEE | 0x00DDDD |
---|
0x08 | 0x083333 | 0x082222 | 0x081111 | 0x080000 | 0x08EEEE | 0x08DDDD |
---|
0x10 | 0x103333 | 0x102222 | 0x101111 | 0x100000 | 0x10EEEE | 0x10DDDD |
---|
0x18 | 0x183333 | 0x182222 | 0x181111 | 0x180000 | 0x18EEEE | 0x18DDDD |
---|
0x20 | 0x203333 | 0x202222 | 0x201111 | 0x200000 | 0x20EEEE | 0x20DDDD |
---|
0x28 | 0x283333 | 0x282222 | 0x281111 | 0x280000 | 0x28EEEE | 0x28DDDD |
---|
0x30 | 0x303333 | 0x302222 | 0x301111 | 0x300000 | 0x30EEEE | 0x30DDDD |
---|
0x38 | 0x383333 | 0x382222 | 0x381111 | 0x380000 | 0x38EEEE | 0x38DDDD |
---|
| Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=37, bitflip=14]
Total number of successful memtester runs: 211
Best luminance at the height 0.5 is above 0x051111, score = 0.747 Best luminance at the height 1.0 is above 0x051111, score = 0.638 Best luminance at the height 2.0 is above 0x051111, score = 0.508 Best luminance at the height 4.0 is above 0x051111, score = 0.375
Read errors per lane: [0, 3, 1, 1]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2.
Write errors per lane: [2, 6, 43, 14]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 50.0% eclipsed by the worst lane 1. Errors from the lane 3 are 50.0% eclipsed by the worst lane 1.
|