User:Jernej/PLL Pattern Control Register

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(NOTE: This description is copied with permission from private e-mail exchange)

PLL Patern Control Register

It has two functions:

  • Spread Spectrum,
  • Fractional Frequency Dividing.

Actually, Fractional Frequency Dividing mode is just a special mode of Spread Spectrum, where amplitude is set to 0.

Spread Spectrum Frequency

The main effect of Spread Spectrum is to increase the bandwidth of the transmitted signal and reduce the occurrence of EMI. It is usually used in some EMI tests.

Take the example of the PLL_DDR0 of A64. The frequency output equation is:

PLL_DDR0=(24MHz*N*K)/M (1)


Spread Spectrum takes effects on the factor N, so we mark the new factor as:

N' = N + f(x) (2)


There are three configurable parameters which determine the f(x) waveform in equation (2):

  • PLL Central Value,
  • PLL Amplitude,
  • Spread Spectrum frequency.


For example, if N = 34, PLL Central Value = 0.5 PLL Amplitude = 0.4 and Spread Spectrum frequency = 31.5Khz and we got a waveform of equation (2). Once we determined the three parameters, we can setup “Pattern control register” to generate such a waveform by below equations:

Spread Spectrum Central Value = PLL Central Value * 2 - 1 (3)

Spread Spectrum Amplitude = PLL Amplitude * 2 (4)

Wave Bottom = (1 + ('Spread Spectrum Central Value' - 'Spread Spectrum Amplitude')) * 2^16 (5)

Wave Step = ('Spread Spectrum frequency' * 2 * 2 * 'Spread Spectrum Amplitude' / 24000) * 2^16 (6)

If Wave Bottom and Wave Step are not integers, cut of fractional part. These are final values which should be put in [16:0]WAVE_BOT and [28:20]WAV_STEP of “Pattern Control Register”.

In “Pattern Control Register”, you can choose the Spread Spectrum frequency with bits [18:17]FREQ. You can choose from four frequencies:

  • 31.5KHz,
  • 32kHz,
  • 32.5KHz,
  • 33KHz.


For the the aforementioned parameters register values are as follows:

Spread Spectrum Central Value = 0.5 * 2 - 1 = 0

Spread Spectrum Amplitude = 0.4 * 2 = 0.8

Wave Bottom = (1 + (0 - 0.8)) * 2 ^ 16 = 13107 = 0x3333

Wave Step = (31.5 * 2 * 2 * 0.8 / 24000) = 275 = 0x113

Fractional Frequency-Dividing

If you want to generate some special clock rates, fractional frequency-dividing is what you need. The effect of Fractional frequency dividings to make the frequency of the configuration more precise.

Fractional Frequency Dividing is a special case of Spread Spectrum, where PLL Amplitude equals 0:

N' = N + f(x) = N + 'PLL Central Value’

If we set PLL Central Value to a decimal, we would get a special clock rate (with fractional part).

For example, PLL_AUDIO = (24Mhz * N) / (M * P) and we want PLL_AUDIO to be 22.5792MHz.

Then N is 7, fractional part is 0.5264, M = 1, P = 8 (Note: Fractional part should be close to 0.5)


Spread Spectrum Central Value = 0.5264 * 2 - 1 = 0.0528

Spread Spectrum Amplitude = 0

Wave Bottom = (1 + (0.0528 - 0)) * 2 ^ 16 = 68996 = 0x10D84

Wave Step = (31.5kHz * 2 * 2 * 0 / 24000kHz) = 0


Short version:

Take fractional part and multiply it with 2^17 -> 0.5264 * 2^17 = 68996,3008 => Wave Bottom = 68996

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