PWM Controller Register Guide

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Contents

PWM

There are two 16-bit up counters in the A10 SoC. Counters will reset when PWM_CH0_PERIOD/PWM_CH1_PERIOD has been reached. On initialization PWM_OUT is active high and starts counting from 0x0000.

The PWM divisor devides the 24MHz clock by 1-4096 depending on the PWM_CTRL register.

There are two output modes, cycle mode and pulse mode which are either, a square waveform or a postive/negative pulse, based on the frequency in the PWM_CH0_PERIOD/PWM_CH1_PERIOD register.

Info

PWM Base address: 0x01c20e00

PWM Registers

Register Name Offset Size Description Note
PWM_CTRL 0x0000 4B PWM Control register
PWM_CH0_PERIOD 0x0004 4B PWM Channel 0 period register
PWM_CH1_PERIOD 0x0008 4B PWM Channel 1 period register Not available on sun5i
PWM_CTRL

Default value: 0x00000000
Offset: 0x00

Name Bit Read/Write Default Values Description
PWM_CH0_PRESCALAR 0:3 Read/Write 0x00
    0x00 = div(120)
    0x01 = div(180)
    0x02 = div(240)
    0x03 = div(360)
    0x04 = div(480)
    0x05 = no operation
    ...
    0x08 = div(12000)
    0x09 = div(24000)
    0x0a = div(36000)
    0x0b = div(48000)
    0x0c = div(72000)
    0x0d = no operation
    ...
  
Setup the Channel 0 PWM prescalar

Set these bits before enabling the clock-gate to this channel!

PWM_CH0_EN 4 Read/Write 0b0
    0 = disable
    1 = enable
  
Enable or disable the Channel 0 PWM
PWM_CH0_CLK_GATE 5 Read/Write 0b0
    0 = low level
    1 = high level
  
Setup Channel 0 PWM Active State
PWM_CH0_PULSE_START 6 Read/Write 0b0
    0 = mask
    1 = pass
  
Special clock gating for Channel 0 PWM
PWM_CH0_MODE 7 Read/Write 0b0
    0 = cycle mode
    1 = pulse mode
  
Setup Channel 0 PWM Active State
PWM_CH0_PUL_START 8 Read/Write 0b0
    0 = no operation
    1 = output 1 pulse
  
Output one pulse according to PWM_CH0_PERIOD and PWM_CH0_ACT_STATE.

The bit is cleared after the pulse.

no operation 9:14
PWM_CH1_PRESCALAR 15:18 Read/Write 0x00
    0x00 = div(120)
    0x01 = div(180)
    0x02 = div(240)
    0x03 = div(360)
    0x04 = div(480)
    0x05 = no operation
    ...
    0x08 = div(12000)
    0x09 = div(24000)
    0x0a = div(36000)
    0x0b = div(48000)
    0x0c = div(72000)
    0x0d = no operation
    ...
  
Setup the PWM Channel 1 prescalar

Set these bits before enabling the clock-gate to this channel!

PWM_CH1_EN 19 Read/Write 0b0
    0 = disable
    1 = enable
  
Enable or disable the Channel 1 PWM
PWM_CH1_ACT_STATE 20 Read/Write 0b0
    0 = low level
    1 = high level
  
Setup Channel 1 PWM Active State
PWM_CH1_CLK_GATING 21 Read/Write 0b0
    0 = mask
    1 = pass
  
Special clock gating for Channel 1 PWM
PWM_CH1_MODE 22 Read/Write 0b0
    0 = cycle mode
    1 = pulse mode
  
Setup Channel 1 PWM Active State
PWM_CH1_PUL_START 23 Read/Write 0b0
    0 = no operation
    1 = output 1 pulse
  
Output one pulse according to PWM_CH1_PERIOD and PWM_CH1_ACT_STATE.

The bit is cleared after the pulse.

no operation 24:31
PWM_CH0_PERIOD

Default value: 0x00000000
Offset: 0x04

Name Bit Read/Write Default Values Description
PWM_CH0_ACT_CYC 0:15 Read/Write 0x00
    0 = 0 cycles
    1 = 1 cycle
    ...
    n = n cycles
  
Number of active cycles in the channel 0 PWM clock
PWM_CH0_ENTIRE_CYC 16:31 Read/Write 0x00
    0 = 1 cycle
    1 = 2 cycles
    ...
    n = n + 1 cycles
  
Numer of entire cycles in the channel 0 PWM clock

If dynamic updates are required, the PCLK needs to be faster then the PWM_CLK (PWM_CLK = 24MHz/PWM_CH0_PRESCALAR)

PWM_CH1_PERIOD

Default value: 0x00000000
Offset: 0x08

Name Bit Read/Write Default Values Description
PWM_CH1_ACT_CYC 0:15 Read/Write 0x00
    0 = 0 cycles
    1 = 1 cycle
    ...
    n = n cycles
  
Number of active cycles in the channel 1 PWM clock
PWM_CH1_ENTIRE_CYC 16:31 Read/Write 0x00
    0 = 1 cycle
    1 = 2 cycles
    ...
    n = n + 1 cycles
  
Numer of entire cycles in the channel 1 PWM clock

If dynamic updates are required, the PCLK needs to be faster then the PWM_CLK (PWM_CLK = 24MHz/PWM_CH1_PRESCALAR)

Initial values

default map

md 0x01c20e00 3

01c20e00: 00000000 00000000 00000000    ...........

all to 1

mw 0x01c20e00 0xffffffff 3
md 0x01c20e00 3

01c20e00: 007f80ff 00ff00ff 00ff00ff    ............

all to 0

mw 0x01c20e00 0x00 3
md 0x01c20c00 3

01c20c00: 00000000 00000000 00000000    ............
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