Clock Control Module

Clock Control Module

Overview

Allwinner's A10 has 10 timing or clock sources. 7 Phase Locking Loop's (PLL's), a 24MHz main crystal oscillator, an RC based internal on chip based oscillator and a low-power 32kHz crystal oscillator.

The 24MHz crystal oscillator is mandatory and is responsible for supplying a clock source for the PLL. The 32kHz crystal oscillator is connected only to the RTC to ensure proper time is kept.

Many devices being driving by any of these clocks have often 2 clocks connected to them. One of the clocks drives the chip itself, the other clock matches the bus to whatever it is connected (usually the CPU).

Clock domain

Clock domain	Used module	Speed range	Description
24MHZ_CLK	Main clock	24.000 MHz	Core clock source, feeds the PLL and some timers.
RC_CLK	Timers, key	32 kHz	Internal 32 kHz source for timers and the RTC. As it is RC based, it is not highly accurate.
32KHZ_CLK	Timers, key	32.768 kHz	External 32 kHz source for timers and the RTC. If an accurate 32.768 kHz crystal oscillator is used, this should provide the most accurate timing reference.
CPU_CLK	CPU	2 kHz - 1200 MHz	The clock for the CPU clock domain is divided from either the CPU_CLK or the 24MHZ_CLK.
AHB_CLK	Advanced High-performance Bus clock domain	8 kHz - 276 MHz	The clock for the AHB clock domain is divided from the CPU_CLK.
APB_CLK	Advanced Peripherals Bus clock domain	0.5 kHz - 138 MHz	The clock for the peripherals clock domain is divided from the AHB_CLK.
SDRAM_CLK	SDRAM clock domain	0 - 400 MHz	The clock for the SDRAM clock domain is provided by the PLL.
USB_CLK	USB	480 MHz	The clock for the USB clock domain is provided by the PLL.
AUDIO_CLK	A/D and D/A devices	24.576 MHz or 22.5792 MHz	The clock for the Audio clock domain is provided by the PLL.

Clock generation

All PLL's are fed from the 24 MHz reference clock.

PLL

Name	Input	Speed range	Output	Defines
PLL1	24 MHz	240 MHz - 2 GHz	${\frac {24\,\mathrm {MHz} \times N\times K}{M\times P}}$	N = {0, 1 ... 31} K = {1, 2, 3, 4} M = {1, 2, 3, 4} P = {1, 2, 4, 8}
PLL2	24 MHz	22.5792 MHz or 24.576 MHz	22.5792 MHz or 24.576 MHz
PLL3	24 MHz	27 MHz - 381 MHz	Integer mode: $3\,\mathrm {MHz} \times M$ Fractional mode: $270\,\mathrm {MHz} \lor 297\,\mathrm {MHz}$	M = {9, 10 ... 127}
PLL4	24 MHz	240 MHz - 2 GHz	${\frac {24\,\mathrm {MHz} \times N\times K}{M\times P}}$	N = {0, 1 ... 31} K = {1, 2, 3, 4} M = {1, 2, 3, 4} P = {1, 2, 4, 8}
PLL5	24 MHz	240 MHz - 2 GHz	${\frac {24\,\mathrm {MHz} \times N\times K}{M}}$ ${\frac {24\,\mathrm {MHz} \times N\times K}{P}}$	N = {0, 1 ... 31} K = {1, 2, 3, 4} M = {1, 2, 3, 4} P = {1, 2, 4, 8}
PLL6	24 MHz	SATA mode: 100 MHz PLL6 mode: 240 MHz - 2 GHz	SATA mode: ${\frac {24\,\mathrm {MHz} \times N\times K}{M\times 6}}$ PLL6 mode: ${\frac {24\,\mathrm {MHz} \times N\times K}{2}}$ PLL6 * 2 mode: $24\,\mathrm {MHz} \times N\times K$	N = {0, 1 ... 31} K = {1, 2, 3, 4} M = {1, 2, 3, 4} P = {1, 2, 4, 8}
PLL7	24 MHz	27 MHz - 381 MHz	Integer mode: $3\,\mathrm {MHz} \times M$ Fractional mode: $270\,\mathrm {MHz} \lor 297\,\mathrm {MHz}$	M = {9, 10 ... 127}

Bus clock generation

Name	Input	Output	Defines
CPU_CLK	{32KHZ_CLK, 24MHZ_CLK, PLL1, ${\frac {\mathrm {PLL6} }{6}}$}
AXI_CLK	CPU_CLK	${\frac {\mathrm {Input} }{N}}$	N = {1, 2, 3, 4}
AHB_CLK	AXI_CLK	${\frac {\mathrm {Input} }{N}}$	N = {1, 2, 4, 8}
APB0_CLK	AHB_CLK	${\frac {\mathrm {Input} }{N}}$	N = {2, 4, 8}
APB1_CLK	{32KHZ_CLK, 24MHZ_CLK, PLL6}	${\frac {\mathrm {Input} }{M\times N}}$	M = {1, 2 ... 32} N = {1, 2, 4, 8}
{TWI_CLK, UART_CLK, PS2_CLK, CAN_CLK, SCR_CLK}	APB1_CLK
{NAND_CLK, <unknown>_CLK, SD[0123]_CLK, TS_CLK, SS_CLK, SPI[0123]_CLK, IR[01]_CLK}	{24MHZ_CLK, PLL5, PLL6}	${\frac {\mathrm {Input} }{M\times N}}$	M = {1, 2 ... 16} N = {1, 2, 4, 8}
PATA_CLK	{PLL5, PLL6}	${\frac {\mathrm {Input} }{M\times N}}$	M = {1, 2 ... 32} N = {1, 2, 4, 8}
{IIS_CLK, <unknown>}	8 * PLL2	${\frac {\mathrm {Input} }{N}}$	N = {1, 2, 4, 8}
KEYPAD_CLK	{32KHZ_CLK, 24MHZ_CLK}	${\frac {\mathrm {Input} }{M\times N}}$	M = {1, 2 ... 32} N = {1, 2, 4, 8}
USB_CLK	USB_CLK
<unknown>	AHB_CLK	${\frac {\mathrm {Input} }{M\times N}}$	M = {1, 2 ... 32} N = {1, 2, 4, 8}
{DE-BE[01]_CLK, FE[01]_CLK, MP_CLK}	{PLL3, PLL5, PLL7}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}
IEP_CLK	BE_CLK
VE_CLK	PLL4	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 8}
LCD_CH0_CLK	{1 * PLL3, 2 * PLL3, 1 * PLL7, 2 * PLL7}
LCD[01]_CH1_CLK2	{1 * PLL3, 2 * PLL3, 1 * PLL7, 2 * PLL7}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}
LCD[01]_CH1_CLK1	LCD[01]_CH1_CLK2	${\frac {\mathrm {Input} }{M}}$	M = {1, 2}
CSI_ISP_CLK	{PLL3, PLL4, PLL5, PLL6}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}
AUDIO_CODEC_CLK	PLL2	${\frac {\mathrm {Input} }{M}}$
SATA_CLK	PLL6
AVS_CLK	24MHZ_CLK
HDMI_CLK	{1 * PLL3, 2 * PLL3, 1 * PLL7, 2 * PLL7}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}
ACE_CLK	{PLL4, PLL5, 24MHZ_CLK}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}
CSI[01]_CLK	{1 * PLL3, 2 * PLL3, 1 * PLL7, 2 * PLL7}	${\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 32}
MALI400_CLK	{PLL3, PLL4, PLL5, PLL7}	$381\,\mathrm {MHz} \geq {\frac {\mathrm {Input} }{M}}$	M = {1, 2 ... 16}

Timer Registers

Timer Base address: 0x01c20000

Register Name	Offset	Size	Description
CCM_PLL1_CFG	0x0000	4B	PLL1 Control (Core)
CCM_PLL1_TUN	0x0004	4B	PLL1 Tuning
CCM_PLL2_CFG	0x0008	4B	PLL2 Control (Audio))
CCM_PLL2_TUN	0x000c	4B	PLL1 Tuning
CCM_PLL3_CFG	0x0010	4B	PLL3 Control (Video0)
CCM_PLL3_TUN (No Tuning 3 seems to exist)	0x0014 (Should be here if it exists)	4B	PLL3 Tuning (Unconfirmed)
CCM_PLL4_CFG	0x0018	4B	PLL4 Control (VE)
CCM_PLL4_TUN (No Tuning 4 seems to exist)	0x001c (Should be here if it exists)	4B	PLL4 Tuning (Unconfirmed)
CCM_PLL5_CFG	0x0020	4B	PLL5 Control (DDR)
CCM_PLL5_TUN	0x0024	4B	PLL5 Tuning
CCM_PLL6_CFG	0x0028	4B	PLL6 Control (SATA)
CCM_PLL6_TUN	0x002c	4B	PLL6 Tuning
CCM_PLL7_CFG	0x0030	4B	PLL7 Control (Video1)
CCM_PLL7_TUN (No Tuning 7 seems to exist)	0x0034 (Should be here if it exists)	4B	PLL7 Tuning (Unconfirmed)
CCM_PLL1_TUN2	0x0038	4B	PLL1 Secondary Tuning
CCM_PLL5_TUN2	0x003c	4B	PLL5 Secondary Tuning
Reserved	0x0040	12B
CCM_PLL_LOCK_DBG	0x004c	4B	PLL Lock Debug
CCM_OSC24M_CFG	0x0050	4B	OSC24M control
CCM_CPU_AHB_APB0_CFG	0x0054	4B	CPU, AHB and APB0 division ratio
CCM_APB1_CLK_DIV	0x0058	4B	APB1 clock division ratio
CCM_AXI_GATING	0x005c	4B	AXI module clock gating
CCM_AHB_GATING0	0x0060	4B	AHB module clock gating 0
CCM_AHB_GATING1	0x0064	4B	AHB module clock gating 1
CCM_APB0_GATING	0x0068	4B	APB0 module clock gating
CCM_APB1_GATING	0x006c	4B	APB1 module clock gating
Reserved	0x0070	16B
CCM_NAND_SCLK_CFG	0x0080	4B	Module clock type 0
CCM_MS_SCLK_CFG	0x0084	4B	Module clock type 0
CCM_MMC0_SCLK_CFG	0x0088	4B	Module clock type 0
CCM_MMC1_SCLK_CFG	0x008c	4B	Module clock type 0
CCM_MMC2_SCLK_CFG	0x0090	4B	Module clock type 0
CCM_MMC3_SCLK_CFG	0x0094	4B	Module clock type 0
CCM_TS_CLK	0x0098	4B	Module clock type 0
CCM_SS_CLK	0x009c	4B	Module clock type 0
CCM_SPI0_CLK	0x00a0	4B	Module clock type 0
CCM_SPI1_CLK	0x00a4	4B	Module clock type 0
CCM_SPI2_CLK	0x00a8	4B	Module clock type 0
CCM_PATA_CLK	0x00ac	4B	Module clock type 0
CCM_IR0_CLK	0x00b0	4B	Module clock type 0
CCM_IR1_CLK	0x00b4	4B	Module clock type 0
CCM_IIS_CLK	0x00b8	4B	Module clock type 1
CCM_AC97_CLK	0x00bc	4B	Module clock type 1
CCM_SPDIF_CLK	0x00c0	4B	Module clock type 1
CCM_KEYPAD_CLK	0x00c4	4B
CCM_SATA_CLK	0x00c8	4B
CCM_USB_CLK	0x00cc	4B
CCM_GPS_CLK	0x00d0	4B
CCM_SPI3_CLK	0x00d4	4B
Reserved	0x00d8	40B
CCM_DRAM_CLK	0x0100	4B
CCM_BE0_SCLK	0x0104	4B
CCM_BE1_SCLK	0x0108	4B
CCM_FE0_CLK	0x010c	4B
CCM_FE1_CLK	0x0110	4B
CCM_MP_CLK	0x0114	4B
CCM_LCD0_CH0_CLK	0x0118	4B
CCM_LCD1_CH0_CLK	0x011c	4B
CCM_CSI_ISP_CLK	0x0120	4B
Reserved	0x0124	4B
CCM_TVD_CLK	0x0128	4B
CCM_LCD0_CH1_CLK	0x012c	4B
CCM_LCD1_CH1_CLK	0x0130	4B
CCM_CS0_CLK	0x0134	4B
CCM_CS1_CLK	0x0138	4B
CCM_VE_CLK	0x013c	4B
CCM_AUDIO_CODEC_CLK	0x0140	4B
CCM_AVS_CLK	0x0144	4B
CCM_ACE_CLK	0x0148	4B
CCM_LVDS_CLK	0x014c	4B
CCM_HDMI_CLK	0x0150	4B
CCM_MALI400_CLK	0x0154	4B
CCM_MBUS_CLK	0x015c	4B
CCM_GMAC_CLK	0x0164	4B
CCM_HDMI1_RST_CLK	0x0170	4B
CCM_HDMI1_CTRL_CLK	0x0174	4B
CCM_HDMI1_SLOW_CLK	0x0178	4B
CCM_HDMI1_REPEAT_CLK	0x017c	4B
CCM_OUTA_CLK	0x01F0	4B
CCM_OUTB_CLK	0x01F4	4B

CCM_PLL1_CFG

Default value: 0x21005000
Offset: 0x0000

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL1_M	0:1	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL1 factor M
CCM_PLL1_SD	2	Read/Write	0x00	0 = disable 1 = enable	Sigma-delta pattern enable
CCM_PLL1_SD_IN	3	Read/Write	0x00		Sigma-delta pattern input
CCM_PLL1_K	4:5	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL1 factor K
no operation	6:7
CCM_PLL1_N	8:12	Read/Write	0x10	0x00 = 0 0x01 = 1 ... 0x1f = 31	PLL1 factor N
CCM_PLL1_LCK_CTRL	13:15	Read/Write	<unknown>		PLL1 lock timer control
CCM_PLL1_P	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	External factor P
no operation	18:19
CCM_PLL1_BIAS	20:24	Read/Write	<unknown>		PLL1 bias current
CCM_PLL1_PLL4_EX	25	Read/Write	0x00	0 = disable 1 = enable {unverified}	Exchange with PLL4 enable
CCM_PLL1_VCO_BIAS	26:29			<unknown>	PLL1 VCO bias control (e.g. pre-div)
CCM_PLL1_VCO_RESET	30	Read/Write	0x00	0 = no operation 1 = reset {unverified}	PLL1 VCO reset in
CCM_PLL1	31	Read/Write	0x00	0 = disable 1 = enable	${\frac {24\,\mathrm {MHz} \times N\times K}{M\times P}}$ The default value for the output is 384 MHz. If bypass is disabled, the result must be 240 MHz - 2 GHz

CCM_PLL1_TUN

Default value: unknown
Offset: 0x0004

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:15				Reserved for verification
CCM_FREQ_INIT	16:25	Read/Write			PLL1 initial frequency control
CCM_PLL1_VCO_GAIN	26	Read/Write		0 = no operation 1 = enable {unverified}	PLL5 VCO gain control
CCM_PLL1_BW	27	Read/Write		0 = narrow 1 = wide {unverified}	PLL1 bandwith control
CCM_PLL1_DAMP	28:31	Read/Write			PLL1 dampening factor

CCM_PLL1_TUN2

Default value: unknown
Offset: 0x0038

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL1_WAV_BOT	0:16
CCM_PLL1_FREQ	17:18	Read/Write	0x00	0x00 = 31.5 kHz 0x01 = 32.0 kHz 0x02 = 32.5 kHz 0x03 = 33.0 kHz	PLL1 frequency
reserved	19
CCM_PLL1_WAV_STP	20:28	Read/Write	0x00		PLL1 Wave step
CCM_PLL1_FREQ_MOD	29:30	Read/Write	0x00	0x00 = DC=0 0x01 = DC=1 0x02 = triangular 0x03 = awmode	PLL1 Spread spectrum frequency mode
CCM_PLL1_SD_PAT	31	Read/Write	0x00	0 = disable 1 = enable	PLL1 Sigma delta pattern enable

CCM_PLL2_CFG

Default value: 0x81000010
Offset: 0x0008

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL2_VCO_BIAS	0:4	Read/Write	0x10	0x00 = 1 0x01 = 2 ... 0x1f = 32	PLL2 VCO bias control (e.g. pre-div)
reserved	5:7
CCM_PLL2_N	8:14	Read/Write	0x00	0x00 = 1 0x01 = 1 0x02 = 2 ... 0x7f = 127	PLL2 factor N
reserved	15
CCM_PLL2_BIAS	16:20	Read/Write	0x02	0x00 = 0 0x01 = 1 ... 0x0f = 15 {unverified}	PLL2 bias current control (e.g. post-div)
reserved	21:27
CCM_PLL2_SD_OUT	28	Read/Write			PLL2 sigma delta output
no operation	29:31
CCM_PLL2	31	Read/Write	0x00	0 = disable 1 = enable	PLL2 is used for Audio. Output formula: ${\frac {24\,\mathrm {MHz} \times N}{\mathrm {CCM\_PLL\_VCO\_BIAS} \times \mathrm {CCM\_PLL\_BIAS} }}$ 1x ${\frac {(2\times 24\,\mathrm {MHz} )\times N}{\mathrm {CCM\_PLL\_VCO\_BIAS} \times \mathrm {CCM\_PLL\_BIAS} \times 2}}$(Not 50% duty cycle) 2x ${\frac {(2\times 24\,\mathrm {MHz} )\times N}{\mathrm {CCM\_PLL\_VCO\_BIAS} \times \mathrm {CCM\_PLL\_BIAS} \times 4}}$(8 x /4 50% duty cycle) 4x ${\frac {(2\times 24\,\mathrm {MHz} )\times N}{\mathrm {CCM\_PLL\_VCO\_BIAS} \times \mathrm {CCM\_PLL\_BIAS} \times 2}}$(8 x /2 50% duty cycle) 8x ${\frac {(2\times 24\,\mathrm {MHz} )\times N}{\mathrm {CCM\_PLL\_VCO\_BIAS} \times \mathrm {CCM\_PLL\_BIAS} }}$(Not 50% duty cycle)

CCM_PLL2_TUN

Default value: 0x00000000
Offset: 0x000c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL2_WAV_BOTTOM	0:16	Read/Write	0x00		Wave bottom
CCM_PLL2_FREQ	17:18	Read/Write	0x00	0x00 = 31.5 kHz 0x01 = 32.0 kHz 0x02 = 32.5 kHz 0x03 = 33.0 kHz	PLL2 Frequency
reserved	19
CCM_PLL2_WAV_STEP	20:28	Read/Write	0x00		PLL2 Wave step
CCM_PLL2_SPRD_FREQ	29:30	Read/Write	0x00	0x00 = DC=0 0x01 = DC=1 0x02 = Triangle 0x03 = awmode	PLL2 Spread spectrum frequency mode
CCM_PLL2_SD_PAT	31	Read/Write	0x00	0 = disable 1 = enable	PLL2 Sigma delta pattern enable

CCM_PLL3_CFG

Default value: 0x0010d063
Offset: 0x0010

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL3_M	0:6	Read/Write	0x63	0x00 = no operation ... 0x09 = 9 ... 0x7f = 127	PLL3 factor M
reserved	7
CCM_PLL3_BIAS	8:12	Read/Write	<unknown>	0x00 = 0 0x01 = 1 ... 0x0f = 15 {unverified}	PLL3 bias current control (e.g. post-div)
reserved	13
CCM_PLL3_FRAC	14	Read/Write	0x01	0 = 270 MHz 1 = 297 MHz {unverified}	PLL3 fractional frequency setting
CCM_PLL3_MODE	15	Read/Write	0x01	0 = fractional 1 = integer	PLL3 mode
CCM_PLL3_VCO_BIAS	16:20	Read/Write	<unknown>	0x00 = 1 0x01 = 2 ... 0x1f = 32 {unverified}	PLL3 bias current control (e.g. pre-div)
CCM_PLL3_DAMP	21:23	<unknown>		PLL3 dampening factor
reserved	24:26
CCM_PLL3		Read/Write	0x00	0 = disable 1 = enable	PLL3 output range: 27 MHz - 381 MHz Integer mode: $3\,\mathrm {MHz} \times M$ Fractional mode: $270\,\mathrm {MHz} \lor 297\,\mathrm {MHz}$ (see bit 14)

CCM_PLL4_CFG

Default value: 0x21081000
Offset: 0x0018

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL4_M	0:1	Read/Write	0x00	0x01 = 1 0x02 = 2 0x03 = 3 0x04 = 4	PLL4 factor M
reserved	2:3
CCM_PLL4_K	4:5	Read/Write	0x00	0x01 = 1 0x02 = 2 0x03 = 3 0x04 = 4	PLL4 factor K
reserved	6:7
CCM_PLL4_N	8:12	Read/Write	0x10	0x00 = 0 0x01 = 1 ... 0x1f = 31	PLL4 factor N
reserved	13:14
CCM_PLL4_SW	15	Read/Write	0x00	0 = disabled 1 = enabled	When enabled, PLL4 is sourced by PLL6
CCM_PLL4_P	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	PLL4 external factor P
reserved	18
CCM_PLL4_VCO_GAIN	19	Read/Write	<unknown>	0 = disabled 1 = enabled {unverified}	PLL4 VCO bias control
CCM_PLL4_BIAS	20:24	Read/Write	<unknown>	0x00 = 1 0x01 = 2 ... 0x1f = 32 {unverified}	PLL4 bias control
CCM_PLL4_VCO_GAIN	25:29	Read/Write	<unknown>	0x00 = 1 0x01 = 2 ... 0x1f = 32 {unverified}	PLL4 VCO gain control
CCM_PLL4_BYPASS	30	Read/Write	0x00	0 = disable 1 = enable	PLL4 bypass, when enabled 24 MHz is being output
CCM_PLL4	31	Read/Write	0x00	0 = disable 1 = enable	PLL4 output range: 24 MHz or 240 MHz - 2 GHz ${\frac {24\,\mathrm {MHz} \times N\times K}{M\times P}}$ Output when CCM_PLL4_BYPASS is disabled must be in the 240 MHz - 2 GHz range

CCM_PLL5_CFG

Default value: 0x11049280
Offset: 0x0020

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL5_M	0:1	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL5 factor M
CCM_PLL5_M1	2:3	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4 {unconfirmed}	PLL5 factor M1
CCM_PLL5_K	4:5	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL5 factor K
reserved	6
CCM_PLL5_LDO	7	Read/Write	0x01	0 = no operation 1 = enable	PLL5 LDO enable
CCM_PLL5_N	8:12	Read/Write	0x12	0x00 = 0 0x01 = 1 ... 0x1f = 31	PLL5 factor N
CCM_PLL5_P	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL5 external factor P
CCM_PLL5_BW	18	Read/Write	<unknown>	0 = narrow 1 = wide	PLL5 bandwith control
CCM_PLL5_VCO_GAIN	19	Read/Write		0 = no operation 1 = enable {unverified}	PLL5 VCO gain control
CCM_PLL5_BIAS	20:24	Read/Write	<unknown>	0x00 = 1 0x01 = 2 ... 0x1f = 32 {unverified}	PLL5 bias current control
CCM_PLL5_VCO_BIAS	25:28	Read/Write	<unknown>	0x00 = 1 0x01 = 2 ... 0x1f = 32 {unverified}	PLL5 VCO bias control (e.g. pre-div)
CCM_PLL5_DDR_CLK	29	Read/Write	0x00	0 = no operation 1 = enable {unverified}	PLL5 DDR clock output enable
CCM_PLL5_BYPASS	30	Read/Write	0x00	0 = disable 1 = enable	PLL5 bypass, when enabled 24 MHz is being output
CCM_PLL5		Read/Write	0x00	0 = disable 1 = enable	PLL5 output range: 24 MHz or 240 MHz - 2 GHz DDR: ${\frac {24\,\mathrm {MHz} \times N\times K}{M}}$ Others: ${\frac {24\,\mathrm {MHz} \times N\times K}{P}}$ Output when CCM_PLL5_BYPASS is disabled must be in the 240 MHz - 2 GHz range

CCM_PLL5_TUN

Default value: unknown
Offset: 0x0024

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:15
CCM_PLL5_FREQ_INIT	16:22	Read/Write			PLL5 initial frequency control
CCM_PLL5_VCO_RST	23	Read/Write		0 = no operation 1 = reset {unverified}	PLL5 VCO reset in
CCM_PLL5_LCK_CTRL	24:26	Read/Write	<unknown>		PLL5 lock timer control
reserved	27
CCM_PLL5_VREG1	28	Read/Write	<unknown>		VReg1 output enable
CCM_PLL5_DAMP	29:31	Read/Write	<unknown>		PLL5 dampening factor

CCM_PLL5_TUN2

Default value: 0x00000000
Offset: 0x003c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL5_WAV_BOT	0:16
CCM_PLL5_FREQ	17:18	Read/Write	0x00	0x00 = 31.5 kHz 0x01 = 32.0 kHz 0x02 = 32.5 kHz 0x03 = 33.0 kHz	PLL5 frequency
reserved	19
CCM_PLL5_WAV_STP	20:28	Read/Write	0x00		PLL5 Wave step
CCM_PLL5_FREQ_MOD	29:30	Read/Write	0x00	0x00 = DC=0 0x01 = DC=1 0x02 = triangular 0x03 = awmode	PLL5 Spread spectrum frequency mode
CCM_PLL5_SD_PAT	31	Read/Write	0x00	0 = disable 1 = enable	PLL5 Sigma delta pattern enable

CCM_PLL6_CFG

Default value: 0x21009911
Offset: 0x0028

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL6_M	0:1	Read/Write	0x01	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL6 factor M
reserved	2:3
CCM_PLL6_K	4:5	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	PLL6 factor K
CCM_PLL6_DAMP	6:7	Read/Write		PLL6 dampening factor
CCM_PLL6_N	8:12	Read/Write	0x19	0x00 = 0 0x01 = 1 ... 0x1f = 31	PLL6 factor N
reserved	13
CCM_PLL6_SATA_CLK	14	Read/Write	<unknown>	0 = no operation 1 = enabled {unconfirmed}	PLL6 SATA clock output enable
CCM_PLL6_BW	15	Read/Write	<unknown>	0 = narrow 1 = wide {unconfirmed}	PLL6 bandwidth control
reserved	16:19
CCM_PLL6_BIAS	20:24	Read/Write	<unknown>		PLL6 bias current
CCM_PLL6_VCO_BIAS	25:29			<unknown>	PLL6 VCO bias control (e.g. pre-div)
CCM_PLL6_BYPASS	30	Read/Write	0x00	0 = disabled 1 = enabled	PLL6 bypass, when enabled 24 MHz is being output
CCM_PLL6	31	Read/Write	0x00	0 = disable 1 = enable	PLL6 output range: 24 MHz or 240 MHz - 2 GHz DDR: ${\frac {24\,\mathrm {MHz} \times N\times K}{M\times 6}}$ Others: ${\frac {24\,\mathrm {MHz} \times N\times K}{2}}$ Output when CCM_PLL6_BYPASS is disabled must be in the 240 MHz - 2 GHz range

CCM_PLL6_TUN

Default value: unknown
Offset: 0x002c

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:31

CCM_PLL7_CFG

Default value: 0x0010d063
Offset: 0x0030

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_PLL7_M	0:6	Read/Write	0x63	0x00 = no operation ... 0x09 = 9 ... 0x7f = 127	PLL7 factor M
reserved	7
CCM_PLL7_BIAS	8:12	Read/Write	<unknown>		PLL6 bias current
reserved	13
CCM_PLL7_FRAC	14	Read/Write	0x01	0 = 270 MHz 1 = 297 MHz	PLL7 fractional frequency setting
CCM_PLL7_MODE	15	Read/Write	0x01	0 = fractional 1 = integer	PLL7 mode
CCM_PLL7_VCO_BIAS	16:20			<unknown>	PLL7 VCO bias control (e.g. pre-div)
reserved	21:23
CCM_PLL7_DAMP	24:26	<unknown>		PLL7 dampening factor
reserved	27:30
CCM_PLL7	31	Read/Write	0x00	0 = disable 1 = enable	PLL7 output range: 27 MHz - 381 MHz Integer mode: $3\,\mathrm {MHz} \times M$ Fractional mode: $270\,\mathrm {MHz} \lor 297\,\mathrm {MHz}$ (see bit 14)

CCM_OSC24M_CFG

Default value: 0x001380133
Offset: 0x0050

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_OSC24M	0	Read/Write	0x01	0 = disable 1 = enable	Enable or disable the external 24 MHz Oscillator
CCM_OSC24M_GSM	1	Read/Write	0x01	0 = disable 1 = enable {Unconfirmed}
reserved	2:14
CCM_OSC24M_PLL_BIAS	15	Read/Write	0x01	0 = disable 1 = enable	OSC24M PLL bias current
CCM_OSC24M_LDO	16	Read/Write	0x01	0 = disable 1 = enable	OSCM24M LDO
CCM_OSC24M_PWR	17	Read/Write	0x01	0 = 2.5 V 1 = 3.3 V	OSC24M input power select
CCM_OSC24M_LDO_OUT	18:20	Read/Write	unknown	0x00 = ??? ... 0x04 = 1.25 V ...	OSC24M LDO output
CCM_OSC24M_KEYFIELD	21:31	Read/Write	0x538		OSC24M keyfield for LDO. Bits 24 - 31 are valid. Writing "strb" will do nothing.

CCM_CPU_AXI_AHB_APB0_CFG

Default value: 0x00010010
Offset: 0x0054

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_AXI_CLK_DIV	0:1	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 3 0x03 = 4	Choose the clock divider for the AXI-bus when the AXI clock source is the CPU clock.
reserved	2:3
CCM_AHB_CLK_DIV	4:5	Read/Write	0x01	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	Choose the clock divider for the AHB when the AHB clock source is the AXI clock.
reserved	5:7
CCM_APB0_CLK_DIV	8:9	Read/Write	0x00	0x00 = 2 0x01 = 2 0x02 = 4 0x03 = 8	Choose the clock divider for the APB0 when the APB0 clock source is the AHB2 clock.
reserved	10:15
CCM_CPU_CLK_SRC	16:17	Read/Write	0x01	0x00 = 32 KHz internal RC clock 0x01 = 24 MHz external Oscillator 0x02 = PLL1 0x03 = 200 MHz sourced from PPL6	Change the CPU Clock source. After changing the clock source, at least 8 clock cycles need to pass before changes are active.
reserved	18:31

CCM_APB1_CLK_DIV_CFG

Default value: 0x00000000
Offset: 0x0058

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_APB1_M	0:4	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x1f = 32	APB1 factor M
reserved	5:15
CCM_APB1_N	16:17	Read/Write	0x01	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	APB1 factor N
reserved	18:23
CCM_APB1_CLK_SRC	24:25	Read/Write	0x00	0x00 = 24 MHz 0x01 = 1.2 GHz (from PLL6) 0x02 = 32 kHz 0x03 = no operation	APB1 clock source
reserved	26:30
reserved	31				Could possibly be APBI Enable/disable? Some special modules (twi, uart, ps2, can, scr) using the APB_CLK use this clock as they need a special clock rate, even if APB_CLK is changed. ${\frac {\mathrm {CCM\_APB1\_CLK\_SRC} }{M\times N}}$

CCM_AXI_CLK_GATE

Default value: 0x00000000
Offset: 0x005c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_AXI_GATE_MASK	0	Read/Write	0x00	0 = mask 1 = pass	AXI dram clock gate pass- or masking
reserved	1:31

CCM_AHB_GATING0

Default value: 0x00000000
Offset: 0x0060

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_AHB_GATE_USB0	0	Read/Write	0x00	0 = mask 1 = pass	AHB USB 0 clock gate pass- or masking
CCM_AHB_GATE_EHCI0	1	Read/Write	0x00	0 = mask 1 = pass	AHB USB EHCI 0 clock gate pass- or masking
CCM_AHB_GATE_OHCI0	2	Read/Write	0x00	0 = mask 1 = pass	AHB USB OHCI 0 clock gate pass- or masking
CCM_AHB_GATE_EHCI1	3	Read/Write	0x00	0 = mask 1 = pass	AHB USB EHCI 1 clock gate pass- or masking
CCM_AHB_GATE_OHCI1	4	Read/Write	0x00	0 = mask 1 = pass	AHB USB OHCI 1 clock gate pass- or masking
CCM_AHB_GATE_SS	5	Read/Write	0x00	0 = mask 1 = pass	AHB SS clock gate pass- or masking
CCM_AHB_GATE_DMA	6	Read/Write	0x00	0 = mask 1 = pass	AHB DMA clock gate pass- or masking
CCM_AHB_GATE_BIST	7	Read/Write	0x00	0 = mask 1 = pass	AHB BIST clock gate pass- or masking
CCM_AHB_GATE_SDMMC0	8	Read/Write	0x00	0 = mask 1 = pass	AHB SD/MMC 0 clock gate pass- or masking
CCM_AHB_GATE_SDMMC1	9	Read/Write	0x00	0 = mask 1 = pass	AHB SD/MMC 1 clock gate pass- or masking
CCM_AHB_GATE_SDMMC2	10	Read/Write	0x00	0 = mask 1 = pass	AHB SD/MMC 2 clock gate pass- or masking
CCM_AHB_GATE_SDMMC3	11	Read/Write	0x00	0 = mask 1 = pass	AHB SD/MMC 3 clock gate pass- or masking
CCM_AHB_GATE_MS	12	Read/Write	0x00	0 = mask 1 = pass	AHB MS clock gate pass- or masking
CCM_AHB_GATE_NAND	13	Read/Write	0x00	0 = mask 1 = pass	AHB NAND clock gate pass- or masking
CCM_AHB_GATE_SDRAM	14	Read/Write	0x00	0 = mask 1 = pass	AHB SDRAM clock gate pass- or masking
CCM_AHB_GATE_DLL	15	Read/Write	0x00	0 = mask 1 = pass	AHB DLL clock gate pass- or masking
CCM_AHB_GATE_ACE	16	Read/Write	0x00	0 = mask 1 = pass	AHB ACE clock gate pass- or masking
CCM_AHB_GATE_EMAC	17	Read/Write	0x00	0 = mask 1 = pass	AHB EMAC clock gate pass- or masking
CCM_AHB_GATE_TS	18	Read/Write	0x00	0 = mask 1 = pass	AHB TS clock gate pass- or masking
reserved	19
CCM_AHB_GATE_SPI0	20	Read/Write	0x00	0 = mask 1 = pass	AHB SPI 0 clock gate pass- or masking
CCM_AHB_GATE_SPI1	21	Read/Write	0x00	0 = mask 1 = pass	AHB SPI 1 clock gate pass- or masking
CCM_AHB_GATE_SPI2	22	Read/Write	0x00	0 = mask 1 = pass	AHB SPI 2 clock gate pass- or masking
CCM_AHB_GATE_SPI3	23	Read/Write	0x00	0 = mask 1 = pass	AHB SPI 3 clock gate pass- or masking
CCM_AHB_GATE_PATA	24	Read/Write	0x00	0 = mask 1 = pass	AHB PATA clock gate pass- or masking
CCM_AHB_GATE_SATA	25	Read/Write	0x00	0 = mask 1 = pass	AHB SATA clock gate pass- or masking
CCM_AHB_GATE_GPS	26	Read/Write	0x00	0 = mask 1 = pass	AHB GPS clock gate pass- or masking
reserved	27
reserved	28
reserved	29
reserved	30
reserved	31

CCM_AHB_GATING1

Default value: 0x00000000
Offset: 0x0064

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_AHB_GATE_VE	0	Read/Write	0x00	0 = mask 1 = pass	AHB VE clock gate pass- or masking
CCM_AHB_GATE_TVD	1	Read/Write	0x00	0 = mask 1 = pass	AHB TVD clock gate pass- or masking
CCM_AHB_GATE_TVE0	2	Read/Write	0x00	0 = mask 1 = pass	AHB TVE 0 clock gate pass- or masking
CCM_AHB_GATE_TVE1	3	Read/Write	0x00	0 = mask 1 = pass	AHB TVE 1 clock gate pass- or masking
CCM_AHB_GATE_LCD0	4	Read/Write	0x00	0 = mask 1 = pass	AHB LCD 0 clock gate pass- or masking
CCM_AHB_GATE_LCD1	5	Read/Write	0x00	0 = mask 1 = pass	AHB LCD 1 clock gate pass- or masking
reserved	6			Possibly for AVS? (LVDS)?
reserved	7				Possibly for AVS? (LVDS)?
CCM_AHB_GATE_CS0	8	Read/Write	0x00	0 = mask 1 = pass	AHB CS 0 clock gate pass- or masking
CCM_AHB_GATE_CS1	9	Read/Write	0x00	0 = mask 1 = pass	AHB CS 1 clock gate pass- or masking
reserved	10				Possibly LVDS? AVS?
CCM_AHB_GATE_HDMI	11	Read/Write	0x00	0 = mask 1 = pass	AHB HDMI clock gate pass- or masking
CCM_AHB_GATE_DE-BE0	12	Read/Write	0x00	0 = mask 1 = pass	AHB DE-BE 0 clock gate pass- or masking
CCM_AHB_GATE_DE-BE1	13	Read/Write	0x00	0 = mask 1 = pass	AHB DE-BE 1 clock gate pass- or masking
CCM_AHB_GATE_DE-FE0	14	Read/Write	0x00	0 = mask 1 = pass	AHB DE-FE 0 clock gate pass- or masking
CCM_AHB_GATE_DE-FE1	15	Read/Write	0x00	0 = mask 1 = pass	AHB DE-FE 1 clock gate pass- or masking
reserved	16				Possibly LVDS? AVS?
reserved	17				Possibly LVDS? AVS?
CCM_AHB_GATE_MP	18	Read/Write	0x00	0 = mask 1 = pass	AHB MP clock gate pass- or masking
reserved	19				Possibly LVDS? AVS?
CCM_AHB_GATE_MALI400	20	Read/Write	0x00	0 = mask 1 = pass	AHB Mali-400 clock gate pass- or masking
reserved	21:31

CCM_APB0_GATING

Default value: 0x00000000
Offset: 0x0068

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_APB_AUDIOCODEC	0	Read/Write	0x00	0 = mask 1 = pass	APB 0 audiocodec clock gate pass- or masking
CCM_APB_SPDIF	1	Read/Write	0x00	0 = mask 1 = pass	APB 0 SPDIF clock gate pass- or masking
CCM_APB_GATE_AC97	2	Read/Write	0x00	0 = mask 1 = pass	APB 0 AC97 clock gate pass- or masking
CCM_APB_GATE_IIS	3	Read/Write	0x00	0 = mask 1 = pass	APB 0 IIS clock gate pass- or masking
reserved	4
CCM_APB_GATE_PIO	5	Read/Write	0x00	0 = mask 1 = pass	APB 0 PIO clock gate pass- or masking
CCM_APB_GATE_IR0	6	Read/Write	0x00	0 = mask 1 = pass	APB 0 IR 0 clock gate pass- or masking
CCM_APB_GATE_IR1	7	Read/Write	0x00	0 = mask 1 = pass	APB 0 IR 1 clock gate pass- or masking
reserved	8				Possibly LVDS? AVS?
reserved	9				Possibly LVDS? AVS?
CCM_APB_GATE_KEYPAD	10	Read/Write	0x00	0 = mask 1 = pass	APB 0 Keypad clock gate pass- or masking
reserved	11:31

CCM_APB1_GATING

Default value: 0x00000000
Offset: 0x006c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_APB_GATE_TWI0	0	Read/Write	0x00	0 = mask 1 = pass	APB 1 TWI 0 clock gate pass- or masking
CCM_APB_GATE_TWI1	1	Read/Write	0x00	0 = mask 1 = pass	APB 1 TWI 1 clock gate pass- or masking
CCM_APB_GATE_TWI2	2	Read/Write	0x00	0 = mask 1 = pass	APB 1 TWI 2 clock gate pass- or masking
CCM_APB_GATE_TWI3	3	Read/Write	0x00	0 = mask 1 = pass	APB 1 TWI 3 clock gate pass- or masking
CCM_APB_GATE_CAN	4	Read/Write	0x00	0 = mask 1 = pass	APB 1 CAN clock gate pass- or masking
CCM_APB_GATE_SCR	5	Read/Write	0x00	0 = mask 1 = pass	APB 1 SCR clock gate pass- or masking
CCM_APB_GATE_PS20	6	Read/Write	0x00	0 = mask 1 = pass	APB 1 PS/2 0 clock gate pass- or masking
CCM_APB_GATE_PS21	7	Read/Write	0x00	0 = mask 1 = pass	APB 1 PS/2 1 clock gate pass- or masking
reserved	8:14
CCM_APB_GATE_TWI4	15	Read/Write	0x00	0 = mask 1 = pass	APB 1 TWI 4 clock gate pass- or masking
CCM_APB_GATE_UART0	16	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 0 clock gate pass- or masking
CCM_APB_GATE_UART1	17	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 1 clock gate pass- or masking
CCM_APB_GATE_UART2	18	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 2 clock gate pass- or masking
CCM_APB_GATE_UART3	19	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 3 clock gate pass- or masking
CCM_APB_GATE_UART4	20	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 4 clock gate pass- or masking
CCM_APB_GATE_UART5	21	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 5 clock gate pass- or masking
CCM_APB_GATE_UART6	22	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 6 clock gate pass- or masking
CCM_APB_GATE_UART70	23	Read/Write	0x00	0 = mask 1 = pass	APB 1 UART 7 clock gate pass- or masking
reserved	24:31

CCM_NAND_CLK

Default value: 0x00000000
Offset: 0x0080

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_NAND_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	NAND factor M
reserved	4:15
CCM_NAND_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	NAND factor N
reserved	18:23
CCM_NAND_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for NAND controller
reserved	26:30
CCM_NAND_GATE	31	Read/Write	0x00	0 = mask 1 = pass	NAND special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_NAND\_CLK\_SRC} }{M\times N}}$

CCM_MMC0_CLK

Default value: 0x00000000
Offset: 0x0088

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MMC0_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SD/MMC 0 factor M
reserved	4:7
CCM_MMC_CTRL_OCLK_DLY	8:10	Read/Write	0x00		Output clock phase control; The output clock phase delay is based on the number of source clock that is from 0 to 7.
reserved	11:15
CCM_MMC0_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SD/MMC 0 factor N
reserved	18:19
CCM_MMC_CTRL_SCLK_DLY	20:22	Read/Write	0x00		Sample clock phase control; The sample clock phase delay is based on the number of source clock that is from 0 to 7.
reserved	23
CCM_MMC0_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SD/MMC 0 controller
reserved	26:30
CCM_MMC0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SD/MMC 0 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_MMC0\_CLK\_SRC} }{M\times N}}$

CCM_MMC1_CLK

Default value: 0x00000000
Offset: 0x008c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MMC1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SD/MMC 1 factor M
reserved	4:15
CCM_MMC1_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SD/MMC 1 factor N
reserved	18:23
CCM_MMC1_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SD/MMC 1 controller
reserved	26:30
CCM_MMC1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SD/MMC 1 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_MMC1\_CLK\_SRC} }{M\times N}}$

CCM_MMC2_CLK

Default value: 0x00000000
Offset: 0x0090

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MMC2_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SD/MMC 2 factor M
reserved	4:15
CCM_MMC2_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SD/MMC 2 factor N
reserved	18:23
CCM_MMC2_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SD/MMC 2 controller
reserved	26:30
CCM_MMC2_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SD/MMC 2 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_MMC2\_CLK\_SRC} }{M\times N}}$

CCM_MMC3_CLK

Default value: 0x00000000
Offset: 0x0094

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MMC3_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SD/MMC 3 factor M
reserved	4:15
CCM_MMC3_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SD/MMC 3 factor N
reserved	18:23
CCM_MMC3_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SD/MMC 3 controller
reserved	26:30
CCM_MMC3_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SD/MMC 3 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_MMC3\_CLK\_SRC} }{M\times N}}$

CCM_SS_CLK

Default value: 0x00000000
Offset: 0x009c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_SS_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SS factor M
reserved	4:15
CCM_SS_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SS factor N
reserved	18:23
CCM_SS_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SS controller
reserved	26:30
CCM_SS_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SS special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_SS\_CLK\_SRC} }{M\times N}}$

CCM_SPI0_CLK

Default value: 0x00000000
Offset: 0x00a0

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_SPI0_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SPI 0 factor M
reserved	4:15
CCM_SPI0_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SPI 0 factor N
reserved	18:23
CCM_SPI0_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SPI 0 controller
reserved	26:30
CCM_SPI0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SPI 0 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_SPI0\_CLK\_SRC} }{M\times N}}$

CCM_SPI1_CLK

Default value: 0x00000000
Offset: 0x00a4

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_SPI1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SPI 1 factor M
reserved	4:15
CCM_SPI1_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SPI 1 factor N
reserved	18:23
CCM_SPI1_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SPI 1 controller
reserved	26:30
CCM_SPI1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SPI 1 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_SPI1\_CLK\_SRC} }{M\times N}}$

CCM_SPI2_CLK

Default value: 0x00000000
Offset: 0x00a8

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_SPI2_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SPI 2 factor M
reserved	4:15
CCM_SPI2_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SPI 2 factor N
reserved	18:23
CCM_SPI2_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SPI 2 controller
reserved	26:30
CCM_SPI2_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SPI 2 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_SPI2\_CLK\_SRC} }{M\times N}}$

CCM_SPI3_CLK

Default value: 0x00000000
Offset: 0x00d4

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_SPI3_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	SPI 3 factor M
reserved	4:15
CCM_SPI3_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	SPI 3 factor N
reserved	18:23
CCM_SPI3_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for SPI 3 controller
reserved	26:30
CCM_SPI3_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SPI 3 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_SPI3\_CLK\_SRC} }{M\times N}}$

CCM_IR0_CLK

Default value: 0x00000000
Offset: 0x00b0

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_IR0_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	IR 0 factor M
reserved	4:15
CCM_IR0_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	IR 0 factor N
reserved	18:23
CCM_IR0_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for IR 0 controller
reserved	26:30
CCM_IRI0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	IR 0 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_IR0\_CLK\_SRC} }{M\times N}}$

CCM_IR1_CLK

Default value: 0x00000000
Offset: 0x00b4

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_IR1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	IR 1 factor M
reserved	4:15
CCM_IR1_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	IR 1 factor N
reserved	18:23
CCM_IR1_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for IR 1 controller
reserved	26:30
CCM_IR1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	IR 1 special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_IR1\_CLK\_SRC} }{M\times N}}$

CCM_IIS_CLK

Default value: 0x00000000
Offset: 0x00b8

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:15
CCM_IIS_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x08 = 8	IIS factor N
reserved	18:30
CCM_IIS_GATE	31	Read/Write	0x00	0 = mask 1 = pass	IIS special clock gating (Max clock = 100 MHz): ${\frac {8\times \mathrm {PLL2} }{M\times N}}$

CCM_A97_CLK

Default value: 0x00030000
Offset: 0x00bc

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:15
CCM_AC97_N	16:17	Read/Write	0x03	0x00 = 1 0x01 = 2 ... 0x08 = 8	AC97 factor N
reserved	18:30
CCM_AC97_GATE	31	Read/Write	0x00	0 = mask 1 = pass	AC97 special clock gating (Max clock = 200 MHz): ${\frac {8\times \mathrm {PLL2} }{N}}$

CCM_SPDIF_CLK

Default value: 0x00030000
Offset: 0x00c0

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:15
CCM_SPDIF_N	16:17	Read/Write	0x03	0x00 = 1 0x01 = 2 ... 0x08 = 8	SPDIF factor N
reserved	18:30
CCM_SPDIF_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SPDIF special clock gating (Max clock = 200 MHz): ${\frac {8\times \mathrm {PLL2} }{N}}$

CCM_KPAD_CLK

Default value: 0x0000001f
Offset: 0x00c4

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_KPAD_M	0:4	Read/Write	0x1f	0x00 = 1 0x01 = 2 ... 0x1f = 32	Keypad factor M
reserved	5:15
CCM_KPAD_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 0x02 = 4 0x03 = 8	Keypad factor N
reserved	18:23
CCM_KPAD_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = no operation 0x02 = RC_CLK 0x03 = no operation	Clock source for keypad controller
reserved	26:30
CCM_KPAD_GATE	31	Read/Write	0x00	0 = mask 1 = pass	Keypad special clock gating (Max clock = 100 MHz): ${\frac {\mathrm {CCM\_KPAD\_CLK\_SRC} }{M\times N}}$

CCM_SATA_CLK

Default value: 0x00000000
Offset: 0x00c8

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:23
CCM_SATA_CLK_SRC	24	Read/Write	0x00	0 = PLL6 (100 MHz) 1 = External Clock	Clock source for SATA controller
reserved	25:30
CCM_SATA_GATE	31	Read/Write	0x00	0 = mask 1 = pass	SATA clock gate pass- or masking

CCM_USB_CLK

Default value: 0x00000000
Offset: 0x00cc

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_USB0_RESET	0	Read/Write	0x00	0 = reset 1 = no reset	USB PHY0 reset control
CCM_USB1_RESET	1	Read/Write	0x00	0 = reset 1 = no reset	USB PHY1 reset control
CCM_USB2_RESET	2	Read/Write	0x00	0 = reset 1 = no reset	USB PHY2 reset control
reserved	3
CCM_USB_CLK_SRC	4	Read/Write	0x00	0 = PLL6 / 25 1 = 48 MHz	Clock source for USB controller: 48 MHz is generated from a 24 MHz sample taken from PLL6
CCM_USB_CLK_SW	5	Read/Write	0x00	0 = ? 1 = ?	USB Clock switch
CCM_USB_OHCI0_GATE	6	Read/Write	0x00	0 = mask 1 = pass	Special USB clock gating for USB OHCI 0
CCM_USB_OHCI1_GATE	7	Read/Write	0x00	0 = mask 1 = pass	Special USB clock gating for USB OHCI 1
CCM_USB_GATE	8	Read/Write	0x00	0 = mask 1 = pass	Special USB clock gating for USB PHY[012]
reserved	9:31

CCM_GPS_CLK

Default value: 0x00000000
Offset: 0x00d0

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_GPS_RESET	0	Read/Write	unknown	0 = disable 1 = enable {unconfirmed}	Enable reset for the GPS module
CCM_GPS_GATE	1	Read/Write	0x00	0 = mask 1 = pass	GPS clock gate pass- or masking
reserved	2:31

CCM_DRAM_CLK

Default value: 0x00000000
Offset: 0x0100

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_DRAM_VE_GATE	0	Read/Write	0x00	0 = mask 1 = pass	DRAM VE clock gate pass- or masking
CCM_DRAM_CSI0_GATE	1	Read/Write	0x00	0 = mask 1 = pass	DRAM CSI 0 clock gate pass- or masking
CCM_DRAM_CSI1_GATE	2	Read/Write	0x00	0 = mask 1 = pass	DRAM CSI 1 clock gate pass- or masking
CCM_DRAM_TS_GATE	3	Read/Write	0x00	0 = mask 1 = pass	DRAM TS clock gate pass- or masking
CCM_DRAM_TVD_GATE	4	Read/Write	0x00	0 = mask 1 = pass	DRAM TVD clock gate pass- or masking
CCM_DRAM_TVE0_GATE	5	Read/Write	0x00	0 = mask 1 = pass	DRAM TVE 0 clock gate pass- or masking
CCM_DRAM_TVE1_GATE	6	Read/Write	0x00	0 = mask 1 = pass	DRAM TVE 1 clock gate pass- or masking
reserved	7:14
CCM_DRAM_CLK_OUT	15	Read/Write	0x00	0 = disable 1 = enable	Enable or disable DRAM clock output
reserved	16:23
CCM_DRAM_FE1_GATE	24	Read/Write	0x00	0 = mask 1 = pass	DRAM FE 1 clock gate pass- or masking
CCM_DRAM_FE0_GATE	25	Read/Write	0x00	0 = mask 1 = pass	DRAM FE 0 clock gate pass- or masking
CCM_DRAM_BE0_GATE	26	Read/Write	0x00	0 = mask 1 = pass	DRAM BE 0 clock gate pass- or masking
CCM_DRAM_BE1_GATE	27	Read/Write	0x00	0 = mask 1 = pass	DRAM BE 1 clock gate pass- or masking
CCM_DRAM_MP_GATE	28	Read/Write	0x00	0 = mask 1 = pass	DRAM MP clock gate pass- or masking
CCM_DRAM_ACE_GATE	29	Read/Write	0x00	0 = mask 1 = pass	DRAM ACE clock gate pass- or masking
reserved	30:31

CCM_DE-BE0_CLK

Default value: 0x00000000
Offset: 0x0104

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_DE-BE0_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	DE-BE 0 factor M
reserved	4:23
CCM_DE-BE0_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL7 0x02 = PLL5 0x03 = no operation	Clock source for DE-BE 0
reserved	26:29
CCM_DE-BE0_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	DE-BE0 reset
CCM_DE-BE0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	DE-BE 0 special clock gating: ${\frac {\mathrm {CCM\_DE-BE0\_CLK\_SRC} }{M}}$

CCM_DE-BE1_CLK

Default value: 0x00000000
Offset: 0x0108

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_DE-BE1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	DE-BE 1 factor M
reserved	4:23
CCM_DE-BE1_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL7 0x02 = PLL5 0x03 = no operation	Clock source for DE-BE1
reserved	26:29
CCM_DE-BE1_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	DE-BE1 reset
CCM_DE-BE1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	DE-BE 1 special clock gating: ${\frac {\mathrm {CCM\_DE-BE1\_CLK\_SRC} }{M}}$

CCM_DE-FE0_CLK

Default value: 0x00000000
Offset: 0x010c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_DE-FE0_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	DE-FE 0 factor M
reserved	4:23
CCM_DE-FE0_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL7 0x02 = PLL5 0x03 = no operation	Clock source for DE-FE 0
reserved	26:29
CCM_DE-FE0_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	DE-FE0 reset
CCM_DE-FE0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	DE-FE 0 special clock gating: ${\frac {\mathrm {CCM\_DE-FE0\_CLK\_SRC} }{M}}$

CCM_DE-FE1_CLK

Default value: 0x00000000
Offset: 0x0110

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_DE-FE1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	DE-FE 1 factor M
reserved	4:23
CCM_DE-FE1_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL7 0x02 = PLL5 0x03 = no operation	Clock source for DE-FE 1
reserved	26:29
CCM_DE-FE1_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	DE-FE1 reset
CCM_DE-FE1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	DE-FE 1 special clock gating: ${\frac {\mathrm {CCM\_DE-FE1\_CLK\_SRC} }{M}}$

CCM_MP_CLK

Default value: 0x00000000
Offset: 0x0114

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MP_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MP factor M
reserved	4:23
CCM_MP_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL7 0x02 = PLL5 0x03 = no operation	Clock source for MP
reserved	26:29
CCM_MP_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	MP reset
CCM_MP_GATE	31	Read/Write	0x00	0 = mask 1 = pass	MP special clock gating: ${\frac {\mathrm {CCM\_MP\_CLK\_SRC} }{M}}$

CCM_LCD0_CH0_CLK

Default value: 0x00000000
Offset: 0x0118

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:23
CCM_LCD0_CH0_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 (x1) 0x01 = PLL7 (x1) 0x02 = PLL3 (x2) 0x03 = PLL7 (x2)	Clock source for LCD 0 CH 0
reserved	26:29
CCM_LCD0_CH0_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	LCD 0 CH 0 reset
CCM_LCD0_CH0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	LCD 0 channel 0 special clock gating: $\mathrm {CCM\_LCD0\_CH0\_CLK\_SRC}$

CCM_LCD0_CH1_CLK

Default value: 0x00000000
Offset: 0x012c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_LCD0_CH1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	LCD 0 CH 1 factor M
reserved	4:10
CCM_LCD0_CH1_CLK_SRC0	11	Read/Write	0x00	0 = CCM_LCD0_CH1_CLK_SRC1 1 = CCM_LCD0_CH1_CLK_SRC1 / 2	Clock source 0 for LCD 0 CH 1
reserved	12:14
CCM_LCD0_CH1_GATE0	15	Read/Write	0x00	0 = mask 1 = pass	LCD 0 channel 1 special clock 0 gating
reserved	16:23
CCM_LCD0_CH1_CLK_SRC1	24:25	Read/Write	0x00	0x00 = PLL3 (x1) 0x01 = PLL7 (x1) 0x02 = PLL3 (x2) 0x03 = PLL7 (x2)	Clock source 1 for LCD 0 CH 1
reserved	26:30
CCM_LCD0_CH1_GATE1	31	Read/Write	0x00	0 = mask 1 = pass	LCD 0 channel 1 special clock 1 gating: ${\frac {\mathrm {CCM\_LCD0\_CH1\_CLK\_SRC1} }{M}}$

CCM_LCD1_CH0_CLK

Default value: 0x00000000
Offset: 0x011c

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:23
CCM_LCD1_CH0_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 (x1) 0x01 = PLL7 (x1) 0x02 = PLL3 (x2) 0x03 = PLL7 (x2)	Clock source for LCD 1 CH 0
reserved	26:29
CCM_LCD1_CH0_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	LCD 1 CH 0 reset
CCM_LCD1_CH0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	LCD 1 channel 0 special clock gating: $\mathrm {CCM\_LCD1\_CH0\_CLK\_SRC}$

CCM_LCD1_CH1_CLK

Default value: 0x00000000
Offset: 0x0130

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_LCD1_CH1_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	LCD 1 CH 1 factor M
reserved	4:10
CCM_LCD1_CH1_CLK_SRC0	11	Read/Write	0x00	0 = CCM_LCD1_CH1_CLK_SRC1 1 = CCM_LCD1_CH1_CLK_SRC1 / 2	Clock source 0 for LCD 1 CH 1
reserved	12:14
CCM_LCD1_CH1_GATE0	15	Read/Write	0x00	0 = mask 1 = pass	LCD 1 channel 1 special clock 0 gating
reserved	16:23
CCM_LCD1_CH1_CLK_SRC1	24:25	Read/Write	0x00	0x00 = PLL3 (x1) 0x01 = PLL7 (x1) 0x02 = PLL3 (x2) 0x03 = PLL7 (x2)	Clock source 1 for LCD1 CH 1
reserved	26:30
CCM_LCD1_CH1_GATE1	31	Read/Write	0x00	0 = mask 1 = pass	LCD 1 channel 1 special clock 1 gating: ${\frac {\mathrm {CCM\_LCD1\_CH1\_CLK\_SRC1} }{M}}$

CCM_CSI-ISP_CLK

Default value: 0x00000000
Offset: 0x0120

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_CSI-ISP_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	CSI-ISP factor M
reserved	4:23
CCM_CSI-ISP_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL4 0x02 = PLL5 0x03 = PLL6	Clock source for CSI-ISP
reserved	26:30
CCM_CSI-ISP_GATE	31	Read/Write	0x00	0 = mask 1 = pass	CSI-ISP clock gate pass- or masking: ${\frac {\mathrm {CCM\_CSI-ISP\_CLK\_SRC} }{M}}$

CCM_TVD_CLK

Default value: 0x00000000
Offset: 0x0128

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:23
CCM_TVD_CLK_SRC	24	Read/Write	0x00	0 = PLL3 1 = PLL7	Clock source for TVD
reserved	25:30
CCM_TVD_GATE	31	Read/Write	0x00	0 = mask 1 = pass	TVD clock gate pass- or masking: ${\frac {\mathrm {CCM\_TVD\_CLK\_SRC} }{M}}$

CCM_CSI0_CLK

Default value: 0x00000000
Offset: 0x0134

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_CSI0_M	0:4	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x1f = 32	CSI 0 factor M
reserved	5:23
CCM_CSI0_CLK_SRC	24:26	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL3 (x1) 0x02 = PLL7 (x1) 0x03 = no operation 0x04 = no operation 0x05 = PLL3 (x2) 0x06 = PLL7 (x2) 0x07 = no operation	Clock source for CSI 0
reserved	27:29
CCM_CSI0_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	CSI 0 reset
CCM_CSI0_GATE	31	Read/Write	0x00	0 = mask 1 = pass	CSI special clock gating: ${\frac {\mathrm {CCM\_CSI0\_CLK\_SRC} }{M}}$

CCM_CSI1_CLK

Default value: 0x00000000
Offset: 0x0138

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_CSI1_M	0:4	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x1f = 32	CSI 1 factor M
reserved	5:23
CCM_CSI1_CLK_SRC	24:26	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL3 (x1) 0x02 = PLL7 (x1) 0x03 = no operation 0x04 = no operation 0x05 = PLL3 (x2) 0x06 = PLL7 (x2) 0x07 = no operation	Clock source for CSI 1
reserved	27:29
CCM_CSI1_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	CSI 1 reset
CCM_CSI1_GATE	31	Read/Write	0x00	0 = mask 1 = pass	CSI special clock gating: ${\frac {\mathrm {CCM\_CSI1\_CLK\_SRC1} }{M}}$

CCM_VE_CLK

Default value: 0x00000000
Offset: 0x013c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_VE_RESET	0	Read/Write	0x00	0 = reset 1 = no reset	VE reset
reserved	1:15
CCM_VE_N	16:18	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x7 = 8	CSI 0 factor M
reserved	19:30
CCM_VE_GATE	31	Read/Write	0x00	0 = mask 1 = pass	CSI special clock gating: ${\frac {\mathrm {PLL4} }{M}}$

CCM_ADDA_CLK

Default value: 0x00000000
Offset: 0x0140

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:30
CCM_ADDA_GATE	31	Read/Write	0x00	0 = mask 1 = pass	AD/DA (audiocodec) special clock gating: $\mathrm {PLL2}$

CCM_AVS_CLK

Default value: 0x00000000
Offset: 0x0144

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:30
CCM_AVS_GATE	31	Read/Write	0x00	0 = mask 1 = pass	AVS special clock gating: $\mathrm {OSC24M}$

CCM_ACE_CLK

Default value: 0x00000000
Offset: 0x0148

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_ACE_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	ACE factor M
reserved	4:15
CCM_ACE_RESET	16	Read/Write	0x00	0 = reset 1 = no reset	ACE 1 reset
reserved	17:23
CCM_ACE_CLK_SRC	24	Read/Write	0x00	0 = PLL4 1 = PLL5	Clock source for CSI 1
reserved	25:30
CCM_ACE_GATE	31	Read/Write	0x00	0 = mask 1 = pass	CSI special clock gating (Max clock = 200 MHz): ${\frac {\mathrm {CCM\_ACE\_CLK\_SRC} }{M}}$

CCM_LVDS_CLK

Default value: 0x00000000
Offset: 0x014c

Name	Bit	Read/Write	Default (Hex)	Values	Description
reserved	0:30
CCM_LVDS_RESET	31	Read/Write	0x00	0 = reset 1 = no reset	LVDS reset

CCM_HDMI_CLK

Default value: 0x00000000
Offset: 0x0150

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_HDMI_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	HDMI factor M
reserved	4:23
CCM_HDMI_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 (x1) 0x01 = PLL7 (x1) 0x02 = PLL3 (x2) 0x03 = PLL7 (x2)	Clock source for HDMI
reserved	26:30
CCM_HDMI_GATE	31	Read/Write	0x00	0 = mask 1 = pass	HDMI special clock gating: ${\frac {\mathrm {CCM\_HDMI\_CLK\_SRC1} }{M}}$

CCM_MALI400_CLK

Default value: 0x00000000
Offset: 0x0154

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MALI400_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MALI 400 factor M
reserved	4:23
CCM_MALI400_CLK_SRC	24:25	Read/Write	0x00	0x00 = PLL3 0x01 = PLL4 0x02 = PLL5 0x03 = PLL7	Clock source for MALI400
reserved	26:29
CCM_MALI400_RESET	30	Read/Write	0x00	0 = reset 1 = no reset	MALI 400 reset
CCM_MALI400_GATE	31	Read/Write	0x00	0 = mask 1 = pass	MALI 400 special clock gating (Max clock = 381 MHz): ${\frac {\mathrm {CCM\_MALI400\_CLK\_SRC} }{M}}$

CCM_MBUS_CTRL

Default value: 0x00000000
Offset: 0x015c

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MBUS_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MBUS factor M
reserved	4:15
CCM_MBUS_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MBUS factor N
reserved	18:23
CCM_MBUS_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 (*2 for A20) 0x02 = PLL5 0x03 = no operation	Clock source for MBUS controller
reserved	26:30
CCM_MBUS_GATE	31	Read/Write	0x00	0 = mask 1 = pass	MBUS special clock gating (Max clock = 300 MHz): ${\frac {\mathrm {CCM\_MBUS\_CLK\_SRC} }{M\times N}}$

CCM_MBUS_CH2_CTRL

Default value: 0x00000000
Offset: 0x0160

Name	Bit	Read/Write	Default (Hex)	Values	Description
CCM_MBUS_M	0:3	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MBUS Channel 2 factor M
reserved	4:15
CCM_MBUS_N	16:17	Read/Write	0x00	0x00 = 1 0x01 = 2 ... 0x0f = 16	MBUS Channel 2 factor N
reserved	18:23
CCM_MBUS_CLK_SRC	24:25	Read/Write	0x00	0x00 = OSC24M 0x01 = PLL6 0x02 = PLL5 0x03 = no operation	Clock source for MBUS Channel 2 controller
reserved	26:30
CCM_MBUS_GATE	31	Read/Write	0x00	0 = mask 1 = pass	MBUS Channel 2 special clock gating (Max clock = 300 MHz): ${\frac {\mathrm {CCM\_MBUS\_CLK\_SRC} }{M\times N}}$

Initial values

default map

md 0x01c20000 0x56

01c20000: a1005000 0a101010 08100010 00000000    .P..............
01c20010: 0010d063 00000000 21081000 00000000    c..........!....
01c20020: b1059491 14888020 21009911 00000000    .... ......!....
01c20030: 0010d063 00000000 00000000 00000000    c...............
01c20040: 00000000 00000000 00000000 00000000    ................
01c20050: 00138013 00020010 00000000 00000000    ................
01c20060: 00004140 00000000 00000020 00010001    @A...... .......
01c20070: 00000000 00000000 00000000 00000000    ................
01c20080: 00000000 00000000 82000004 00000000    ................
01c20090: 00000000 00000000 00000000 00000000    ................
01c200a0: 00000000 00000000 00000000 00000000    ................
01c200b0: 00000000 00000000 00000000 00030000    ................
01c200c0: 00010000 0000001f 00000000 00000000    ................
01c200d0: 00000000 00000000 00000000 00000000    ................
01c200e0: 00000000 00000000 00000000 00000000    ................
01c200f0: 00000000 00000000 00000000 00000000    ................
01c20100: 00008000 00000000 00000000 00000000    ................
01c20110: 00000000 00000000 00000000 00000000    ................
01c20120: 00000000 00000000 00000000 00000000    ................
01c20130: 00000000 00000000 00000000 00000000    ................
01c20140: 00000000 00000000 00000000 00000000    ................
01c20150: 00000000 00000000    ........

Code References

https://github.com/hno/uboot-allwinner/blob/lichee/lichee-dev-mmc/arch/arm/include/asm/arch-sunxi/clock.h https://github.com/amery/linux-allwinner/blob/allwinner-v3.0-android-v2/arch/arm/mach-sun4i/include/mach/ccmu_regs.h