|CPU||Quad-Core ARM Cortex-A53|
|Memory||up to 3 GB LPDDR2/ LPDDR3/ DDR3 / DDR3L|
|Video||MIPI DSI [email protected], LVDS [email protected], RGB [email protected], HDMI v1.4 [email protected]|
|Network||GBit MAC, no PHY|
|Storage||NAND, NOR, MMC|
|USB||OTG, 1x Host|
|Other||BGA396, 0.65mm pitch, 15x15mm|
Allwinner A64 (sun50i) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali400 MP2 GPU from ARM.
The A64 is basically an Allwinner H3 with the Cortex-A7 cores replaced with Cortex-A53 cores (ARM64 architecture). They share most of the memory map, clocks, interrupts and also uses the same IP blocks. Differences between the H3 and the A64 seem to be:
- The H3 has three USB host controllers, whereas the A64 has only one. Both SoCs have an additional USB-OTG controller, which is assumed to be used as normal host controller as well.
- The H3 DRAM controller supports up to 2GB of RAM, the A64 supports up to 3 GB. Despite being a 64-bit chip, this makes the SoC entirely 32-bit on the physical side.
- The H3 supports 5 UARTs, the A64 has 6 of them.
- The MMC controller has been updated to support faster transfer modes. The MMC clocks have changed on the way, now the MMC controller itself provides support for the output and sample phase.
- The H3 has SRAM A1 mapped at address 0, the BROM is at 0xffff0000. The A64 has its BROM mapped at address 0, SRAM A1 is mapped right behind it at 0x10000 (64KB).
- The pinmux configuration is still somewhat similar, but differs to an extent which makes them incompatible. A prominent example is (the debug) UART0, which is on PortA on the H3, but on PortB on the A64. H3 lacks PortB entirely.
A64 SoC Features
- ARM Cortex-A53 Quad-Core (r0p4, revidr=0x80) (scroll down for the PDF link)
- 512KiB L2-Cache
- 32KiB (Instruction) / 32KiB (Data) L1-Cache per core
- SIMD NEON (including double-precision floating point), VFP4
- Cryptography Extension (SHA and AES instructions)
- Affected by one critical erratum (only in AArch64 state): 843419
- ARM Mali400 MP2
- Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).
- Complies with OpenGL ES 2.0
- DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 controller (up to 3GB of 667MHz(DDR-1333))
- NAND Flash controller and 64-bit ECC
- Supports parallel 8-bit YUV422 sensor
- Support CCIR656 protocol for NTSC and PAL
- Maximum still capture resolution 5M
- Maximum video capture resolution up to [email protected]
- X-Powers AXP803, as seen used with A64 in Olimex Olinuxino A64 design
Allwinner H64 is targetted for OTT boxes and A64 for the tablets. Both are quad core Cortex A53 processors with a Mali-400MP2 GPU, H.265 4K video playback with basically the same interfaces and peripherals, but H64 also supports H.264 at 4K resolutions, while A64 is limited to H.264 @ 1080p, and H64 adds a TS interface.
Some devices in the SoC are not described in the manual, but have descriptions in other SoC's manuals:
- RSB: MMIO address and IRQ mentioned in the A64 manual, IP description in the A83T manual.
- PRCM: MMIO address mentioned in the A64 manual, IP description in the A83T manual.
Some remarks about the memory map.
Basic support for the A64 SoC has been been merged into 2016.05-rc1. This covers UART, MMC and required GPIOs and clocks. Ethernet support has been added in 2016.09-rc1, USB with 2016.11-rc3.
U-Boot 2017.03-rc1 saw the addition of the required DRAM init code, so SPL support is now enabled. However this version lacks support for loading the ATF, which limits the usability. Patches to overcome this are on the list already.
The U-Boot implementation is 64-bit (armv8), so an aarch64 cross compiler is needed to compile U-Boot.
Devices in development:
The publically available SDKs contain kernel and u-boot trees which include and depend on several binaries. Allwinner is always violating the GPL in this way since A31. In the current A64 SDK, lots of blobs are included in kernel and U-Boot, including the critical DRAM code and the important HDMI code.
(The list below may be not finished, and do not list files related to non-A64 SoC)
(Only u-boot-2014.07 is checked here)