User:Ssvb/Cubietruck DRAM Calibration

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Cubietruck 600MHz (cold start zq settings)

dcdc3_vol = 1275
dram_clk = 600
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 8
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x10d1800
dram_odt_en = 3
dram_tpr0 = 0x3c9688b4
dram_tpr1 = 0xa090
dram_tpr2 = 0x2be00
dram_tpr3 = 0x11111
dram_emr1 = 0x42
dram_emr2 = 0x10
dram_emr3 = 0x0
dqs_gating_delay = 0x07070707
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=22, solidbits=2, checkerboard=1]

Total number of successful memtester runs: 320

Best luminance at the height 0.5 is above 0x101111, score = 0.804
Best luminance at the height 1.0 is above 0x101111, score = 0.719
Best luminance at the height 2.0 is above 0x101111, score = 0.615
Best luminance at the height 3.0 is above 0x101111, score = 0.547

Read errors per lane: [5, 0, 6, 2]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst line 1.
Errors from the lane 3 are not intersecting with the errors from the worst line 1.

Write errors per lane: [6, 0, 0, 6]. Lane 3 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst line 3.

Cubietruck 600MHz (normal zq settings)

dcdc3_vol = 1275
dram_clk = 600
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 8
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x2c (0x10d3900)
dram_odt_en = 3
dram_tpr0 = 0x3c9688b4
dram_tpr1 = 0xa090
dram_tpr2 = 0x2be00
dram_tpr3 = 0x11111
dram_emr1 = 0x42
dram_emr2 = 0x10
dram_emr3 = 0x0
dqs_gating_delay = 0x07070707
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=12, solidbits=2]

Total number of successful memtester runs: 357

Best luminance at the height 0.5 is above 0x101111, score = 0.816
Best luminance at the height 1.0 is above 0x101111, score = 0.736
Best luminance at the height 2.0 is above 0x101111, score = 0.640
Best luminance at the height 3.0 is above 0x101111, score = 0.577

Read errors per lane: [3, 0, 6, 3]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst line 1.
Errors from the lane 3 are not intersecting with the errors from the worst line 1.

Write errors per lane: [0, 0, 0, 2]. Lane 0 is the most noisy/problematic.

Cubietruck 648MHz (cold start zq settings)

dcdc3_vol = 1250
dram_clk = 648
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 8192
dram_io_width = 16
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x10d1800
dram_odt_en = 3
dram_tpr0 = 0x429899b4
dram_tpr1 = 0xa0a0
dram_tpr2 = 0x2c200
dram_tpr3 = 0x81111
dram_emr1 = 0x42
dram_emr2 = 0x10
dram_emr3 = 0x0
dqs_gating_delay = 0x07070707
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=28, solidbits=11]

Total number of successful memtester runs: 121

Best luminance at the height 0.5 is above 0x012222, score = 0.614
Best luminance at the height 1.0 is above 0x012222, score = 0.473
Best luminance at the height 2.0 is above 0x012222, score = 0.338
Best luminance at the height 3.0 is above 0x012222, score = 0.268

Read errors per lane: [1, 0, 6, 5]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst line 1.
Errors from the lane 3 are not intersecting with the errors from the worst line 1.

Write errors per lane: [21, 1, 1, 7]. Lane 3 is the most noisy/problematic.
Errors from the lane 0 are 14.3% eclipsed by the worst lane 3.
Errors from the lane 1 are 100.0% eclipsed by the worst lane 3.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 3.

Cubietruck 648MHz (normal zq settings)

dcdc3_vol = 1250
dram_clk = 648
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 8192
dram_io_width = 16
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x10d3900
dram_odt_en = 3
dram_tpr0 = 0x429899b4
dram_tpr1 = 0xa0a0
dram_tpr2 = 0x2c200
dram_tpr3 = 0x81111
dram_emr1 = 0x42
dram_emr2 = 0x10
dram_emr3 = 0x0
dqs_gating_delay = 0x07070707
active_windowing = 1
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=19, solidbits=10]

Total number of successful memtester runs: 242

Best luminance at the height 0.5 is above 0x082222, score = 0.764
Best luminance at the height 1.0 is above 0x082222, score = 0.662
Best luminance at the height 2.0 is above 0x082222, score = 0.541
Best luminance at the height 3.0 is above 0x082222, score = 0.464

Read errors per lane: [4, 0, 7, 5]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst line 1.
Errors from the lane 3 are not intersecting with the errors from the worst line 1.

Write errors per lane: [2, 0, 0, 11]. Lane 0 is the most noisy/problematic.
Errors from the lane 3 are not intersecting with the errors from the worst line 0.

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