Talk:PWM Controller Register Guide

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Two things need to be noted here.

PWM_CH0_PERIOD (and CH1) is defined to setup and read a 16-bit counter. PWM_CH0_PUL_START mentions that the pulse width is set in register [0:15]. But PWM_CH0_PERIOD defines it as an 8-bit value, with the other 8-bits being undefined/unused. This seems like an obvious mistake in the datasheet. "Luckly" the code uses hardcoded registers so searching for 0x204 gave some results stating this to be true, as the write mask is specifically set to 0xffff0000. https://github.com/amery/linux-allwinner/blob/wip/lichee3-sunxi/import-sun5i/drivers/video/sun4i/disp/de_bsp/de/disp_lcd.c#L939

Dwilkins (talk) 16:25, 8 May 2013 (UTC)

I have written a pwm driver for this chip, and empirically tested your hypothesis and I can say:

PWM_CH0_PERIOD and PWM_CH1_PERIOD are certainly 8bit only

If you set the extra bits, bad things won't immediately happen, but random chip features will stop working (I'm looking directly at active_cycles here...)

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