Icenowy/DE2 Register Guide

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Contents

DE2 register guide

Overview

Although DE2 is listed as a single block in the datasheet, it in fact contains several sub-blocks.

Sections

Section Subsection Address Size Description
CCU CCU 0x01000000 - 0x01000014  ?kiB DE2 Clock Controller
Mixer Mixer0 0x01100000 - 0x011fffff  ?kiB Display Mixer 0
Mixer1 0x01200000 - 0x012fffff  ?kiB Display Mixer 1
WB WB  ?  ?kiB Write Back Controller

CCU

Register Name Offset Size Description
DE2_CCU_GATE 0x00 4 B Module clock gate register
DE2_CCU_BUS_GATE 0x04 4 B Bus clock gate register
DE2_CCU_RST 0x08 4 B Bus reset register
DE2_CCU_DIV 0x0c 4 B Module clock division register
DE2_CCU_SEL 0x10 4 B Unknown

DE2_CCU_GATE

Bit Read/Write Default description
31:3 / / Reserved
2 Read/Write 0 Module clock gate for WB
1 Read/Write 0 Module clock gate for Mixer 1
0 Read/Write 0 Module clock gate for Mixer 0

DE2_CCU_BUS_GATE

Bit Read/Write Default description
31:3 / / Reserved
2 Read/Write 0 Bus gate for WB
1 Read/Write 0 Bus gate for Mixer 1
0 Read/Write 0 Bus gate for Mixer 0

DE2_CCU_RST

Bit Read/Write Default description
31:3 / / Reserved
2 Read/Write 0 Bus reset for WB (and on A83T, H3, R40 and unknown sun8iw{9,10} SoCs, it's also the bus reset for Mixer 1)
1 Read/Write 0 Bus reset for Mixer 1 (on SoCs not mentioned above)
0 Read/Write 0 Bus reset for Mixer 0

DE2_CCU_DIV

The real division value is the value in the register part + 1.

Bit Read/Write Default description
31:12 / / Reserved
8:11 Read/Write 0 Module clock division for WB
4:7 Read/Write 0 Module clock division for Mixer 1
0:3 Read/Write 0 Module clock division for Mixer 0

Mixer sub-functions

Section Starting Address to Mixer Base Address Description
Mixer Global Configuration 0x00000 Some Configuration among different sub-functions
Blend Configuration 0x01000 Configuration about display channels and layers
Other Configurations 0x20000 Something that not so known now
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