DRAM Calibration Results/Olimex A20-OLinuXino-Micro Rev.E

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DRAM calibration results for Olimex A20-OLinuXino-Micro rev. E board.

Contents

dram_emr1

432MHz, emr1=0x4

dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 300
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7f (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x05060505
active_windowing = 0
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=20, bitflip=18]

Total number of successful memtester runs: 309

Best luminance at the height 0.5 is above 0x021111, score = 0.760
Best luminance at the height 1.0 is above 0x021111, score = 0.662
Best luminance at the height 2.0 is above 0x021111, score = 0.559
Best luminance at the height 4.0 is above 0x021111, score = 0.462

Read errors per lane: [0, 0, 15, 9]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 1.

Write errors per lane: [0, 0, 14, 14]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.


432MHz, emr1=0x44

dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 300
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7f (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x21111
dram_emr1 = 0x44
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x05060605
active_windowing = 0
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=20, bitflip=12]

Total number of successful memtester runs: 267

Best luminance at the height 0.5 is above 0x031111, score = 0.745
Best luminance at the height 1.0 is above 0x031111, score = 0.640
Best luminance at the height 2.0 is above 0x031111, score = 0.528
Best luminance at the height 4.0 is above 0x031111, score = 0.421

Read errors per lane: [0, 0, 13, 6]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 16.7% eclipsed by the worst lane 1.

Write errors per lane: [1, 1, 14, 13]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.

432MHz, emr1=0x40

dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 300
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7f (0x5294a00)
dram_odt_en = 0
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x21111
dram_emr1 = 0x40
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x05060606
active_windowing = 0
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x181111
0x20
0x28
0x30
0x38
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=17, bitflip=11]

Total number of successful memtester runs: 264

Best luminance at the height 0.5 is above 0x031111, score = 0.746
Best luminance at the height 1.0 is above 0x031111, score = 0.642
Best luminance at the height 2.0 is above 0x031111, score = 0.529
Best luminance at the height 4.0 is above 0x031111, score = 0.421

Read errors per lane: [0, 0, 12, 8]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 1.

Write errors per lane: [1, 1, 8, 7]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.

zq

<tbody></tbody>
dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 300
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x4e (0x199cb00)
dram_odt_en = 3
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x41111
dram_emr1 = 0x4
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
<tbody></tbody>
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=18, bitflip=4]

Total number of successful memtester runs: 180

Best luminance at the height 0.5 is above 0x061111, score = 0.709
Best luminance at the height 1.0 is above 0x061111, score = 0.587
Best luminance at the height 2.0 is above 0x061111, score = 0.451
Best luminance at the height 4.0 is above 0x061111, score = 0.324

Read errors per lane: [1, 1, 0, 2]. Lane 0 is the most noisy/problematic.
Errors from the lane 2 are not intersecting with the errors from the worst lane 0.
Errors from the lane 3 are not intersecting with the errors from the worst lane 0.

Write errors per lane: [5, 5, 16, 16]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 40.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 40.0% eclipsed by the worst lane 1.
</tbody>

A20-new-u-boot

<tbody></tbody>
<tbody></tbody>
dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 400
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x5e (0x31deb00)
dram_odt_en = 3
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x41111
dram_emr1 = 0x4
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
<tbody></tbody>
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x28
0x30
0x38
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=15, bitflip=11]

Total number of successful memtester runs: 436

Best luminance at the height 0.5 is above 0x031111, score = 0.890
Best luminance at the height 1.0 is above 0x031111, score = 0.838
Best luminance at the height 2.0 is above 0x031111, score = 0.763
Best luminance at the height 4.0 is above 0x031111, score = 0.656

Read errors per lane: [0, 0, 0, 4]. Lane 0 is the most noisy/problematic.

Write errors per lane: [6, 6, 19, 19]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 50.0% eclipsed by the worst lane 1.
Errors from the lane 3 are 50.0% eclipsed by the worst lane 1.

A20-new-u-boot <tbody></tbody>
<tbody></tbody>
dcdc3_vol = 1300
dram_clk = 432
mbus_clk = 300
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x6e (0x31deb00)
dram_odt_en = 3
dram_tpr0 = 0x2a906690
dram_tpr1 = 0xa068
dram_tpr2 = 0x22e00
dram_tpr3 = 0x41111
dram_emr1 = 0x4
dram_emr2 = 0x8
dram_emr3 = 0x0
dqs_gating_delay = 0x06060606
active_windowing = 1
<tbody></tbody>
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=22, bitflip=6, bitspread=1]

Total number of successful memtester runs: 470

Best luminance at the height 0.5 is above 0x031111, score = 0.905
Best luminance at the height 1.0 is above 0x031111, score = 0.859
Best luminance at the height 2.0 is above 0x031111, score = 0.791
Best luminance at the height 4.0 is above 0x031111, score = 0.692

Read errors per lane: [0, 0, 0, 2]. Lane 0 is the most noisy/problematic.

Write errors per lane: [17, 16, 19, 19]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.
Errors from the lane 2 are 56.2% eclipsed by the worst lane 1.
Errors from the lane 3 are 52.9% eclipsed by the worst lane 1.

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