LinkSprite pcDuino2

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LinkSprite pcDuino2
Pcd v2 front.jpg
Manufacturer Linksprite
Dimensions 125mm x 52mm x heightmm
Release Date September 2013
Website Product Page
Specifications
SoC A10 @ 1GHz
DRAM 1GiB DDR3 @ 360MHz (H5TQ2G83CFR-H9C, NT5CB256M8BN-CG)
NAND 2/4GB
Power DC 5V @ 2A
Features
Video HDMI (Type A - full)
Audio HDMI
Network WiFi 802.11bgn (Realtek RTL8188CUS), 10/100Mbps Ethernet (IC+ IP101A)
Storage µSD
USB 1 USB2.0 Host, 1 USB2.0 OTG

The pcDuino2 is an A10 based development board with Arduino compatible headers. Unlike many other A10 based boards, this one does not have a SATA connector.

Contents

Identification

On the back of the board, it helpfully says "pcDuino V2".

Sunxi support

Current status

Fully supported.

Images

HW-Pack

BSP

Manual build

  • For building u-boot, use the pcDuino target.
  • The .fex file can be found in sunxi-boards as linksprite_pcduino2.fex

Everything else is the same as the manual build howto.

Mainline U-Boot

For building mainline u-boot, use the Linksprite_pcDuino board name.

Mainline kernel

Use the sun4i-a10-pcduino.dts device-tree file for the mainline kernel.

Tips, Tricks, Caveats

FEL mode

The UPGRADE (SW2, near the HDMI connector) button triggers FEL mode.

LEDs

The board has 5 green LEDs. One of them is an always-on power indicator. Two LEDs labelled TX and RX are accessible via GPIO (using the PH15 and PH16 pins). One LED labelled CLK is connected to the PI11 pin, which can also have a dedicated use as SPI0_CLK. So this CLK LED serves either as an SPI activity indicator or just as an ordinary LED if no SPI hardware is connected. And there is also one more WIFI LED on the board, which is connected to the WIFI chip.

DRAM

This board uses four x8 DDR3 chips (two on the front side of the PCB and two on the back side). So far SKhynix and NANYA chips have been encountered. SKhynix has reliability problems at clock speeds higher than 360MHz. Preliminary tests show that NANYA appears to be reasonably good and at least works without problems at the default 408MHz settings from the vendor.

Below are the a10-tpr3-scan results with the default U-Boot settings, just after setting the DRAM clock frequency a little bit too high. The a10-tpr3-scan tool suggests to change the tpr3 value to 0x181111 for HYNIX and to 0x041111 for NANYA. Basically, the delay settings need to be changed in different directions for improving reliability. The HYNIX settings are bad for NANYA and the other way around. The default tpr3 value 0x000000 happens to be on the edge of the reliable/unreliable boundary in both cases.

a10-tpr3-scan results from pcDuino2 with HYNIX DDR3 @408MHz

dcdc3_vol = 1250
dram_clk = 408
mbus_clk = 0
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 6
dram_zq = 0x7b (0x6b96900)
dram_odt_en = 0
dram_tpr0 = 0x30926692
dram_tpr1 = 0x1090
dram_tpr2 = 0x1a0c8
dram_tpr3 = 0x0
dram_emr1 = 0x0
dram_emr2 = 0x0
dram_emr3 = 0x0
dqs_gating_delay = 0x06050505
active_windowing = 0
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [solidbits=35, bitflip=20]

Total number of successful memtester runs: 383

Best luminance at the height 0.5 is above 0x181111, score = 0.857
Best luminance at the height 1.0 is above 0x181111, score = 0.792
Best luminance at the height 2.0 is above 0x181111, score = 0.703
Best luminance at the height 4.0 is above 0x181111, score = 0.589

Read errors per lane: [0, 0, 11, 0]. Lane 1 is the most noisy/problematic.

Write errors per lane: [0, 11, 33, 1]. Lane 1 is the most noisy/problematic.
Errors from the lane 0 are not intersecting with the errors from the worst lane 1.
Errors from the lane 2 are not intersecting with the errors from the worst lane 1.

a10-tpr3-scan results from pcDuino2 with NANYA DDR3 @432MHz

dcdc3_vol = 1250
dram_clk = 432
mbus_clk = 0
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 6
dram_zq = 0x7b (0x6b91800)
dram_odt_en = 0
dram_tpr0 = 0x30926692
dram_tpr1 = 0x1090
dram_tpr2 = 0x1a0c8
dram_tpr3 = 0x0
dram_emr1 = 0x0
dram_emr2 = 0x0
dram_emr3 = 0x0
dqs_gating_delay = 0x05050505
active_windowing = 0
mfxdlyphase=36phase=54phase=72phase=90phase=108phase=126
0x070x0733330x0722220x0711110x0700000x07EEEE0x07DDDD
0x060x0633330x0622220x0611110x0600000x06EEEE0x06DDDD
0x050x0533330x0522220x0511110x0500000x05EEEE0x05DDDD
0x040x0433330x0422220x0411110x0400000x04EEEE0x04DDDD
0x030x0333330x0322220x0311110x0300000x03EEEE0x03DDDD
0x020x0233330x0222220x0211110x0200000x02EEEE0x02DDDD
0x010x0133330x0122220x0111110x0100000x01EEEE0x01DDDD
0x000x0033330x0022220x0011110x0000000x00EEEE0x00DDDD
0x080x0833330x0822220x0811110x0800000x08EEEE0x08DDDD
0x100x1033330x1022220x1011110x1000000x10EEEE0x10DDDD
0x180x1833330x1822220x1811110x1800000x18EEEE0x18DDDD
0x200x2033330x2022220x2011110x2000000x20EEEE0x20DDDD
0x280x2833330x2822220x2811110x2800000x28EEEE0x28DDDD
0x300x3033330x3022220x3011110x3000000x30EEEE0x30DDDD
0x380x3833330x3822220x3811110x3800000x38EEEE0x38DDDD
Lane phase adjustments: [0, 0, 0, 0]
Error statistics from memtester: [bitflip=36, solidbits=9]

Total number of successful memtester runs: 456

Best luminance at the height 0.5 is above 0x041111, score = 0.894
Best luminance at the height 1.0 is above 0x041111, score = 0.844
Best luminance at the height 2.0 is above 0x041111, score = 0.770
Best luminance at the height 4.0 is above 0x031111, score = 0.668

Read errors per lane: [0, 6, 0, 0]. Lane 2 is the most noisy/problematic.

Write errors per lane: [1, 32, 6, 16]. Lane 2 is the most noisy/problematic.
Errors from the lane 0 are 56.2% eclipsed by the worst lane 2.
Errors from the lane 1 are 66.7% eclipsed by the worst lane 2.
Errors from the lane 3 are 100.0% eclipsed by the worst lane 2.

Expansion headers

J11 (Closer to the corner with the ethernet connector) J12 (Closer to the corner with the HDMI connector)
Pin number pcDuino name Sunxi name Pin number pcDuino name Sunxi name
1 UART2_RX PI19 6 ADC_5
2 UART2_TX PI18 5 ADC_4
3 GPIO2 PH7 4 ADC_3
4 PWM0 PH6 3 ADC_2
5 GPIO3 PH8 2 ADC_1
6 PWM1 PB2 1 ADC_0
7 PWM2 PI3
8 GPIO4 PH9
J8 (Closer to the corner with the WIFI chip) J9 (Closer to the corner with the USB connector)
Pin number pcDuino name Sunxi name Pin number pcDuino name Sunxi name
1 GPIO5 8 DC_5V
2 PWM3 7 GND
3 SPI0_CS 6 GND
4 SPI0_MOSI 5 DC_5V
5 SPI0_MISO 4 3V3_SYS
6 SPI0_CLK 3 RESET
7 GND 2 3V3_SYS
8 1
9 TWI2-SDA
10 TWI2-SCK

Arduino shields compatibility

ITeadstudio 2.4 TFT LCD Touch shield can be only successfully used with jumper wires

The advertised compatibility with Arduino shields is not always perfect.

Adding a serial port

UART pads

There is 2.54mm pitch header next to the Wifi Module, labelled "UART". All you need to do is connect some jumper wires according to our UART howto.

Pictures

Also known as

This type of device has no rebadges.

See also

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