https://linux-sunxi.org/api.php?action=feedcontributions&user=Wink&feedformat=atomlinux-sunxi.org - User contributions [en]2024-03-29T07:29:44ZUser contributionsMediaWiki 1.35.8https://linux-sunxi.org/index.php?title=H6&diff=22294H62019-04-02T07:42:39Z<p>Wink: </p>
<hr />
<div>{{Infobox SoC<br />
| image = [[File:AllwinnerH6.jpg|250px]]<br />
| manufacturer = Allwinner<br />
| process = 28nm<br />
| cpu = Quad-Core ARM Cortex-A53 @ 1.8GHz<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR2/LPDDR3/DDR3/DDR4<br />
| gpu = Mali-T720 MP2 @ 600Mhz<br />
| vpu = <br />
| apu = <br />
| video = HDMI 2.0 with HDCP 2.2, TV CVBS, RGB LCD<br />
| audio = I2S, PCM, TDM<br />
| network = GBit MAC, integrated 10/100M PHY<br />
| storage = MMC, NAND<br />
| usb = 1x OTG, 1x Host 2.0, 1x Host 3.0<br />
| other = PCIE 2.0 1x<br />
| release_date = June 2017<br />
| website = [http://www.allwinnertech.com/index.php?c=product&a=index&id=66 Product Page]<br />
}}<br />
<br />
Allwinner [[H6]] (sun50iw6p1) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali-T720 MP2 GPU from ARM. The Allwinner H6 is an OTT SoC.<br />
<br />
=Overview=<br />
See [[Mainlining Effort]] and [[Mainline U-Boot]] for support status. The initial support for the SoC will be added in kernel 4.17<br />
<br />
== Differences / New features (compared to H5) ==<br />
<br />
=== High level differences ===<br />
* addition of PCIe support (broken, see below)<br />
** single lane PCIe 2.0<br />
** totally undocumented software interface<br />
* addition of USB 3.0 host<br />
* Mali T720 instead of Mali 450<br />
* DDR4 DRAM support<br />
* addition of IOMMU<br />
** though only connected to display controller and video codecs<br />
* (New?) Audio Hub component<br />
<br />
=== Programming model/driver level differences ===<br />
* heavily changed memory map (UART0 at 0x05000000, for instance)<br />
** SRAM locations moved around as well (SRAM A1 at 0x2000 now)<br />
* bus clock gates and device reset control now grouped by devices and merged into one register (high 16 bits reset, low 16 bits clock gates) <br />
* DMA controller changed (more than 32 ports, but still limited to 32 bit addresses)<br />
* no GPIO port A and B<br />
<br />
=== Errata ===<br />
* '''The PCIe implementation is broken.'''<br />
Allwinner H6 has a quirky PCIe controller that doesn't map the PCIe address space properly (only 64k accessible at one time) to CPU, and accessing the PCIe config space, I/O space or memory space will need to be wrapped. As Linux doesn't wrap PCIe memory space access, it's not possible to do a proper PCIe controller driver for H6. The BSP kernel modifies the driver to wrap the access, so it's also not generic, and only devices with modified driver will work.<br />
<br />
=H6 SoC Features=<br />
* CPU<br />
** ARM Cortex-A53 Quad-Core<br />
** 512KB L2-Cache (shared between four cores)<br />
** 32 KB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
* GPU<br />
** ARM Mali-T720 MP2<br />
** Featuring 2 unified shader cores<br />
** Complies with OpenGL ES 3.0, OpenCL 1.2<br />
* Memory<br />
** DDR3/DDR4/LPDDR2/LPDDR3 controller<br />
** NAND Flash controller and 64-bit ECC, supports full disk encryption<br />
** 3 MMC controllers, in which MMC2 (eMMC controller) supports full disk encryption<br />
* Video<br />
** Ultra HD 4k and Full HD 1080p video decoding of MPEG-2, MPEG-4 SP/ASP GMC, H.263, H.264, H.265, WMV9/VC-1, and VP8<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@60fps encoding<br />
** 3840×1080,1920x2160 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** Integrated HDMI V2.0 with HDCP2.2 4K@60fps<br />
** TV CVBS output<br />
** RGB LCD output<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV422 sensor<br />
** Support CCIR656 protocol fot NTSC and PAL<br />
** 5M CMOS sensor support<br />
** Support video capture resolution up to 1080p@30fps<br />
* Audio<br />
** Two audio digital-to-analog(DAC) channels 92dB SNR<br />
** Two differential microphone inputs (one low-noise)<br />
** Stereo Linein input<br />
** TDM Digital Microphone input<br />
* Embedded Controller:<br />
** [[AR100]] controller.<br />
* Thermal Sensor Controller (TSC) providing over-temperature protection interrupt and over-temperature alarm interrupt<br />
* AXP805 PMIC<br />
* package: FBGA451, 15 mm x 15 mm, 0.65 mm Pitch<br />
<br />
=Documentation=<br />
* [[File:Allwinner_H6_V200_Datasheet_V1.1.pdf]] <small>(PDF, 80 pages, 2017-11-14)</small><br />
* [[File:Allwinner_H6_V200_User_Manual_V1.1.pdf]] <small>(PDF, 965 pages, 2017-11-14)</small><br />
<br />
<br />
= Register guide =<br />
= Software =<br />
<br />
== Original SDK ==<br />
A beta version of the H6 BSP was released on 2018/01/30...<br />
<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-brandy<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-tools<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-linux<br />
<br />
SDK tarballs are also available from pine64, mirrored on our own dl server as well.<br />
* [http://files.pine64.org/os/sdk/H64-ver1.1/H6-lichee-v1.1.tar.gz H6 Lichee v1.1] [http://dl.linux-sunxi.org/H6/H6-lichee-v1.1.tar.gz (mirror)]<br />
* [http://files.pine64.org/os/sdk/H64-ver1.0/H6-BSP-1.0.tgz H6 BSP 1.0] [http://dl.linux-sunxi.org/H6/H6-BSP-1.0.tgz (mirror)]<br />
* [http://files.pine64.org/os/sdk/H64-ver1.0/H6-Android-7.1-SDK.tgz H6 Android 7.1 SDK] [http://dl.linux-sunxi.org/H6/H6-Android-7.1-SDK.tgz (mirror)]<br />
<br />
== Boot0 ==<br />
== U-boot ==<br />
<br />
=== Allwinner ===<br />
<br />
=== Sunxi Community ===<br />
=== Mainline U-Boot ===<br />
<br />
<br />
== Kernel code ==<br />
=== Allwinner ===<br />
=== Sunxi Community ===<br />
=== Mainline ===<br />
<br />
== GPL Violations ==<br />
<br />
As is customary, even the H6 SDKs/BSPs come with a range of binaries included in GPL licensed code.<br />
<br />
=== H6-lichee-v1.1 ===<br />
<br />
The tarball for this can be found [http://files.pine64.org/os/sdk/H64-ver1.1/H6-lichee-v1.1.tar.gz on the pine64 website].<br />
<br />
==== kernel ====<br />
<br />
In the subdirectory linux-3.10, a patched linux-3.10.65, the following binaries can be found:<br />
<pre><br />
<br />
# --------------------------- Nand Drivers ---------------------------<br />
libnand-xxx are Legacy Codes and will be removed in next release SDK. <br />
For source codes of these blobs, please visit : https://github.com/allwinner-zh/linux-3.4-sunxi/tree/master/modules/nand<br />
<br />
./modules/nand/sun50iw2p1/libnand_sun50iw2p1<br />
./modules/nand/common0/libnand<br />
./modules/nand/sun50iw1p1/libnand_sun50iw1p1<br />
./modules/nand/sun8iw10p1/libnand_sun8iw10p1<br />
./modules/nand/sun8iw5p1/libnand<br />
./modules/nand/sun8iw11p1/libnand_sun8iw11p1<br />
# --------------------------------------------------------------------<br />
# ------------------------- HDMI 1.0 Drivers -------------------------<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun8iw11 # This blob is no longer used and its source code is included in the Hdmi 2.0 code<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun50iw1 # Same as libhdmi_sun50iw1.<br />
# --------------------------------------------------------------------<br />
<br />
# -------------------------- ARISC Drivers --------------------------<br />
Legacy Codes for old platform, not for H6, should be removed in next release SDK. <br />
<br />
./drivers/arisc/binary/arisc_sun8iw5p1.bin <br />
./drivers/arisc/binary/arisc_sun50iw1p1.code<br />
# --------------------------------------------------------------------<br />
<br />
# --------------------------- Power Manager Subsystem ---------------------------<br />
<br />
./drivers/soc/allwinner/pm/standby/standby.xn # It's a linker script, not a blob.<br />
<br />
Legacy Codes for old platform, not for H6, should be removed in next release SDK. <br />
<br />
./drivers/soc/allwinner/pm/resume1/sun8i_resume1_scatter.scat # It's a linker script, not a blob.<br />
./drivers/soc/allwinner/pm/resume1/gen_check_code # It's a host tool, it l is used to shape the binary file which build from the pm project. It's deprecated.<br />
./drivers/soc/allwinner/pm_legacy/standby/sun9i_resume1_scatter.scat # It's a linker script, not a blob.<br />
./drivers/soc/allwinner/pm_legacy/standby/sun8i_resume1_scatter.scat # It's a linker script, not a blob.<br />
./drivers/soc/allwinner/pm_legacy/standby/standby.xn # It's a linker script, not a blob.<br />
./drivers/soc/allwinner/pm_legacy/standby/gen_check_code # Same as pm/resume1/gen_check_code<br />
# ----------------------------------------------------------------------------------<br />
<br />
# ------------------------- Camera Relative -------------------------<br />
Legacy Codes for old platform, not for H6, should be removed in next release SDK. <br />
./drivers/media/platform/sunxi-vfe/lib/libisp_32<br />
./drivers/media/platform/sunxi-vfe/lib/lib_mipicsi2_v1<br />
./drivers/media/platform/sunxi-vfe/lib/lib_mipicsi2_v2<br />
./drivers/media/platform/sunxi-vfe/lib/libisp_64<br />
# -------------------------------------------------------------------<br />
</pre><br />
<br />
==== U-Boot ====<br />
<br />
<big>'''u-boot-2011.09 are legacy source codes, H6 didn’t use it. It should be removed in next release SDK. '''</big><br />
<br />
In the subdirectories bootloader/uboot_2011_sunxi_spl, and uboot_2014_sunxi_spl a bunch of dram binaries can be seen which likely must be included in the u-boot builds listed in under lichee/brandy/.<br />
<br />
In the subdirectory lichee/brandy/u-boot-2011.09/, a patched u-boot 2011-09-rc1, the following binaries can be found:<pre><br />
<br />
./nand_sunxi/sun8iw3/libnand-sun8iw3<br />
./nand_sunxi/sun8iw1/libnand-sun8iw1<br />
./nand_sunxi/sun8iw5/libnand-sun8iw5<br />
./nand_sunxi/sun8iw8/libnand-sun8iw8<br />
./nand_sunxi/sun9iw1/libnand-sun9iw1<br />
./nand_sunxi/sun7i/libnand-sun7i<br />
./nand_sunxi/sun8iw9/libnand-sun8iw9<br />
./nand_sunxi/sun8iw7/libnand-sun8iw7<br />
./nand_sunxi/sun5i/libnand-sun5i<br />
./nand_sunxi/sun8iw6/libnand-sun8iw6<br />
./board/sunxi/sun9iw1/box_standby/cpus_pm/cpus_pm_binary.code<br />
./board/sunxi/sun8iw7/box_standby/cpus_pm/cpus_pm_binary.code<br />
./board/sunxi/sun8iw6/box_standby/cpus_pm/cpus_pm_binary.code<br />
./arch/arm/cpu/armv7/sun8iw5/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw8/dram/libdram<br />
./arch/arm/cpu/armv7/sun9iw1/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw7/dram/libchipid<br />
./arch/arm/cpu/armv7/sun8iw7/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw6/dram/libdram-homlet<br />
./arch/arm/cpu/armv7/sun8iw6/dram/libdram-pad<br />
./drivers/video_sunxi/sunxi_v1/obj_video<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/hdmi/aw/libhdcp<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/de/lowlevel_sun9iw1/libdsi<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/de/lowlevel_sun9iw1/libedp<br />
./drivers/video_sunxi/sunxi_v2/obj_video<br />
./drivers/video_sunxi/sunxi_v3/obj_video</pre><br />
<br />
In the subdirectory lichee/brandy/u-boot-2014.07/, a patched u-boot 2014-07, the following binaries can be found:<br />
<pre><br />
libnand-xxx are Legacy Codes and will be removed in next release SDK. <br />
For source code of these blobs, please visit : https://github.com/allwinner-zh/bootloader/tree/master/u-boot-2011.09/nand_spl ,<br />
and https://github.com/allwinner-zh/bootloader/tree/master/u-boot-2011.09/nand_sunxi<br />
<br />
./nand_sunxi/sun50iw2p1/libnand-sun50iw2p1<br />
./nand_sunxi/sun50iw3p1/libnand-sun50iw3p1<br />
./nand_sunxi/sun50iw1p1/libnand-sun50iw1p1<br />
./nand_sunxi/sun8iw10p1/libnand-sun8iw10p1<br />
./nand_sunxi/sun8iw11p1/libnand-sun8iw11p1<br />
./nand_sunxi/sun8iw12p1/libnand-sun8iw12p1<br />
./nand_sunxi/sun50iw6p1/libnand-sun50iw6p1<br />
<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun8iw11 # This blob is no longer used and its source code is included in the Hdmi 2.0 code<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun50iw1 # Same as libhdmi_sun8iw11<br />
</pre><br />
<br />
= Devices =<br />
<br />
<categorytree mode=pages hideroot=on depth=1>H6 Devices</categorytree><br />
<br />
[[Category:System on Chip]]</div>Winkhttps://linux-sunxi.org/index.php?title=H6&diff=22293H62019-04-02T05:49:41Z<p>Wink: /* U-Boot */</p>
<hr />
<div>{{Infobox SoC<br />
| image = [[File:AllwinnerH6.jpg|250px]]<br />
| manufacturer = Allwinner<br />
| process = 28nm<br />
| cpu = Quad-Core ARM Cortex-A53 @ 1.8GHz<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR2/LPDDR3/DDR3/DDR4<br />
| gpu = Mali-T720 MP2 @ 600Mhz<br />
| vpu = <br />
| apu = <br />
| video = HDMI 2.0 with HDCP 2.2, TV CVBS, RGB LCD<br />
| audio = I2S, PCM, TDM<br />
| network = GBit MAC, integrated 10/100M PHY<br />
| storage = MMC, NAND<br />
| usb = 1x OTG, 1x Host 2.0, 1x Host 3.0<br />
| other = PCIE 2.0 1x<br />
| release_date = June 2017<br />
| website = [http://www.allwinnertech.com/index.php?c=product&a=index&id=66 Product Page]<br />
}}<br />
<br />
Allwinner [[H6]] (sun50iw6p1) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali-T720 MP2 GPU from ARM. The Allwinner H6 is an OTT SoC.<br />
<br />
=Overview=<br />
See [[Mainlining Effort]] and [[Mainline U-Boot]] for support status. The initial support for the SoC will be added in kernel 4.17<br />
<br />
== Differences / New features (compared to H5) ==<br />
<br />
=== High level differences ===<br />
* addition of PCIe support (broken, see below)<br />
** single lane PCIe 2.0<br />
** totally undocumented software interface<br />
* addition of USB 3.0 host<br />
* Mali T720 instead of Mali 450<br />
* DDR4 DRAM support<br />
* addition of IOMMU<br />
** though only connected to display controller and video codecs<br />
* (New?) Audio Hub component<br />
<br />
=== Programming model/driver level differences ===<br />
* heavily changed memory map (UART0 at 0x05000000, for instance)<br />
** SRAM locations moved around as well (SRAM A1 at 0x2000 now)<br />
* bus clock gates and device reset control now grouped by devices and merged into one register (high 16 bits reset, low 16 bits clock gates) <br />
* DMA controller changed (more than 32 ports, but still limited to 32 bit addresses)<br />
* no GPIO port A and B<br />
<br />
=== Errata ===<br />
* '''The PCIe implementation is broken.'''<br />
Allwinner H6 has a quirky PCIe controller that doesn't map the PCIe address space properly (only 64k accessible at one time) to CPU, and accessing the PCIe config space, I/O space or memory space will need to be wrapped. As Linux doesn't wrap PCIe memory space access, it's not possible to do a proper PCIe controller driver for H6. The BSP kernel modifies the driver to wrap the access, so it's also not generic, and only devices with modified driver will work.<br />
<br />
=H6 SoC Features=<br />
* CPU<br />
** ARM Cortex-A53 Quad-Core<br />
** 512KB L2-Cache (shared between four cores)<br />
** 32 KB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
* GPU<br />
** ARM Mali-T720 MP2<br />
** Featuring 2 unified shader cores<br />
** Complies with OpenGL ES 3.0, OpenCL 1.2<br />
* Memory<br />
** DDR3/DDR4/LPDDR2/LPDDR3 controller<br />
** NAND Flash controller and 64-bit ECC, supports full disk encryption<br />
** 3 MMC controllers, in which MMC2 (eMMC controller) supports full disk encryption<br />
* Video<br />
** Ultra HD 4k and Full HD 1080p video decoding of MPEG-2, MPEG-4 SP/ASP GMC, H.263, H.264, H.265, WMV9/VC-1, and VP8<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@60fps encoding<br />
** 3840×1080,1920x2160 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** Integrated HDMI V2.0 with HDCP2.2 4K@60fps<br />
** TV CVBS output<br />
** RGB LCD output<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV422 sensor<br />
** Support CCIR656 protocol fot NTSC and PAL<br />
** 5M CMOS sensor support<br />
** Support video capture resolution up to 1080p@30fps<br />
* Audio<br />
** Two audio digital-to-analog(DAC) channels 92dB SNR<br />
** Two differential microphone inputs (one low-noise)<br />
** Stereo Linein input<br />
** TDM Digital Microphone input<br />
* Embedded Controller:<br />
** [[AR100]] controller.<br />
* Thermal Sensor Controller (TSC) providing over-temperature protection interrupt and over-temperature alarm interrupt<br />
* AXP805 PMIC<br />
* package: FBGA451, 15 mm x 15 mm, 0.65 mm Pitch<br />
<br />
=Documentation=<br />
* [[File:Allwinner_H6_V200_Datasheet_V1.1.pdf]] <small>(PDF, 80 pages, 2017-11-14)</small><br />
* [[File:Allwinner_H6_V200_User_Manual_V1.1.pdf]] <small>(PDF, 965 pages, 2017-11-14)</small><br />
<br />
<br />
= Register guide =<br />
= Software =<br />
<br />
== Original SDK ==<br />
A beta version of the H6 BSP was released on 2018/01/30...<br />
<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-brandy<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-tools<br />
* https://github.com/Allwinner-Homlet/H6-BSP4.9-linux<br />
<br />
SDK tarballs are also available from pine64, mirrored on our own dl server as well.<br />
* [http://files.pine64.org/os/sdk/H64-ver1.1/H6-lichee-v1.1.tar.gz H6 Lichee v1.1] [http://dl.linux-sunxi.org/H6/H6-lichee-v1.1.tar.gz (mirror)]<br />
* [http://files.pine64.org/os/sdk/H64-ver1.0/H6-BSP-1.0.tgz H6 BSP 1.0] [http://dl.linux-sunxi.org/H6/H6-BSP-1.0.tgz (mirror)]<br />
* [http://files.pine64.org/os/sdk/H64-ver1.0/H6-Android-7.1-SDK.tgz H6 Android 7.1 SDK] [http://dl.linux-sunxi.org/H6/H6-Android-7.1-SDK.tgz (mirror)]<br />
<br />
== Boot0 ==<br />
== U-boot ==<br />
<br />
=== Allwinner ===<br />
<br />
=== Sunxi Community ===<br />
=== Mainline U-Boot ===<br />
<br />
<br />
== Kernel code ==<br />
=== Allwinner ===<br />
=== Sunxi Community ===<br />
=== Mainline ===<br />
<br />
== GPL Violations ==<br />
<br />
As is customary, even the H6 SDKs/BSPs come with a range of binaries included in GPL licensed code.<br />
<br />
=== H6-lichee-v1.1 ===<br />
<br />
The tarball for this can be found [http://files.pine64.org/os/sdk/H64-ver1.1/H6-lichee-v1.1.tar.gz on the pine64 website].<br />
<br />
==== kernel ====<br />
<br />
In the subdirectory linux-3.10, a patched linux-3.10.65, the following binaries can be found:<pre>./modules/nand/sun50iw2p1/libnand_sun50iw2p1<br />
./modules/nand/common0/libnand<br />
./modules/nand/sun50iw1p1/libnand_sun50iw1p1<br />
./modules/nand/sun8iw10p1/libnand_sun8iw10p1<br />
./modules/nand/sun8iw5p1/libnand<br />
./modules/nand/sun8iw11p1/libnand_sun8iw11p1<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun8iw11<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun50iw1<br />
./drivers/arisc/binary/arisc_sun8iw5p1.bin<br />
./drivers/arisc/binary/arisc_sun50iw1p1.code<br />
./drivers/soc/allwinner/pm/standby/standby.xn<br />
./drivers/soc/allwinner/pm/resume1/sun8i_resume1_scatter.scat<br />
./drivers/soc/allwinner/pm/resume1/gen_check_code<br />
./drivers/soc/allwinner/pm_legacy/standby/sun9i_resume1_scatter.scat<br />
./drivers/soc/allwinner/pm_legacy/standby/sun8i_resume1_scatter.scat<br />
./drivers/soc/allwinner/pm_legacy/standby/standby.xn<br />
./drivers/soc/allwinner/pm_legacy/standby/gen_check_code<br />
./drivers/media/platform/sunxi-vfe/lib/libisp_32<br />
./drivers/media/platform/sunxi-vfe/lib/lib_mipicsi2_v1<br />
./drivers/media/platform/sunxi-vfe/lib/lib_mipicsi2_v2<br />
./drivers/media/platform/sunxi-vfe/lib/libisp_64</pre><br />
<br />
==== U-Boot ====<br />
<br />
<big>'''u-boot-2011.09 are legacy source codes, H6 didn’t use it. It should be removed in next release SDK. '''</big><br />
<br />
In the subdirectories bootloader/uboot_2011_sunxi_spl, and uboot_2014_sunxi_spl a bunch of dram binaries can be seen which likely must be included in the u-boot builds listed in under lichee/brandy/.<br />
<br />
In the subdirectory lichee/brandy/u-boot-2011.09/, a patched u-boot 2011-09-rc1, the following binaries can be found:<pre><br />
<br />
./nand_sunxi/sun8iw3/libnand-sun8iw3<br />
./nand_sunxi/sun8iw1/libnand-sun8iw1<br />
./nand_sunxi/sun8iw5/libnand-sun8iw5<br />
./nand_sunxi/sun8iw8/libnand-sun8iw8<br />
./nand_sunxi/sun9iw1/libnand-sun9iw1<br />
./nand_sunxi/sun7i/libnand-sun7i<br />
./nand_sunxi/sun8iw9/libnand-sun8iw9<br />
./nand_sunxi/sun8iw7/libnand-sun8iw7<br />
./nand_sunxi/sun5i/libnand-sun5i<br />
./nand_sunxi/sun8iw6/libnand-sun8iw6<br />
./board/sunxi/sun9iw1/box_standby/cpus_pm/cpus_pm_binary.code<br />
./board/sunxi/sun8iw7/box_standby/cpus_pm/cpus_pm_binary.code<br />
./board/sunxi/sun8iw6/box_standby/cpus_pm/cpus_pm_binary.code<br />
./arch/arm/cpu/armv7/sun8iw5/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw8/dram/libdram<br />
./arch/arm/cpu/armv7/sun9iw1/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw7/dram/libchipid<br />
./arch/arm/cpu/armv7/sun8iw7/dram/libdram<br />
./arch/arm/cpu/armv7/sun8iw6/dram/libdram-homlet<br />
./arch/arm/cpu/armv7/sun8iw6/dram/libdram-pad<br />
./drivers/video_sunxi/sunxi_v1/obj_video<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/hdmi/aw/libhdcp<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/de/lowlevel_sun9iw1/libdsi<br />
./drivers/video_sunxi/sunxi_v2/de_bsp/de/lowlevel_sun9iw1/libedp<br />
./drivers/video_sunxi/sunxi_v2/obj_video<br />
./drivers/video_sunxi/sunxi_v3/obj_video</pre><br />
<br />
In the subdirectory lichee/brandy/u-boot-2014.07/, a patched u-boot 2014-07, the following binaries can be found:<br />
<pre><br />
libnand-xxx are Legacy Codes and will be removed in next release SDK. For source of blobs, please visit : https://github.com/allwinner-zh/linux-3.4-sunxi/tree/master/modules/nand<br />
./nand_sunxi/sun50iw2p1/libnand-sun50iw2p1<br />
./nand_sunxi/sun50iw3p1/libnand-sun50iw3p1<br />
./nand_sunxi/sun50iw1p1/libnand-sun50iw1p1<br />
./nand_sunxi/sun8iw10p1/libnand-sun8iw10p1<br />
./nand_sunxi/sun8iw11p1/libnand-sun8iw11p1<br />
./nand_sunxi/sun8iw12p1/libnand-sun8iw12p1<br />
./nand_sunxi/sun50iw6p1/libnand-sun50iw6p1<br />
<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun8iw11 # This blob is no longer used and its source code is included in the Hdmi 2.0 code<br />
./drivers/video/sunxi/disp2/hdmi/libhdmi_sun50iw1 # Same as libhdmi_sun8iw11<br />
</pre><br />
<br />
= Devices =<br />
<br />
<categorytree mode=pages hideroot=on depth=1>H6 Devices</categorytree><br />
<br />
[[Category:System on Chip]]</div>Winkhttps://linux-sunxi.org/index.php?title=NAND&diff=21140NAND2018-03-23T15:30:25Z<p>Wink: </p>
<hr />
<div>{{alert|This page provides installation instructions for the legacy unmaintained u-boot-sunxi and sunxi-3.4 kernel forks. Although it contains useful information how things work, driver for mainline kernel (3.14+) has [[MTD_Driver|its own page here]].}}<br />
<br />
In the sunxi world, NAND (a type of flash memory) signifies the on board flash memory of a sunxi device. Our main u-boot version currently does not support booting from NAND and an altered allwinner version or an experimental MTD u-boot version (with MTD kernel driver) needs to be used instead.<br />
<br />
= Background =<br />
<br />
Our SoCs have a very specific [[Boot_Process | boot process]]. First it executes [[BROM | a tiny on chip rom (BROM)]] which then checks the buttons for [[FEL]] mode and then starts checking the various storage options for a valid boot signature at the right location.<br />
<br />
There is no real difference between NAND and an SD-card apart from the fact that directly attached flash use the Sunxi NAND controller directly while SD-Cards come with a standard interface and an embedded controller usually based today on cortex-m0 core that runs proprietary firmware which implements flash translation layer that performs wear leveling. The sunxi nand controller is harder to implement than the sunxi sd-card controller, and the sample code provided by allwinner is rather large (and shared between U-boot and the kernel).<br />
<br />
Then there is the NAND hw randomizer that gets in the way. Allwinner uses one setting for the BROM and the second boot stage (boot0/SPL), and another setting for normal use. With this setup, it is currently not implemented to access both bits at the same time. This currently provides another barrier for implementation, as one first needs to be able to read/write this area. While this is not beyond fixing, these are quite a few hoops to jump through.<br />
<br />
As a result of the above, we have to use the existing second and third stages of the allwinner nand boot process, and we need to use nand-part for partitioning. If we had proper u-boot support, we would not need any of that.<br />
<br />
It is very likely that this usage of the NAND is going to disappear completely in future. The plans for mainline support currently involves a [[#MTD_driver|MTD device driver]], and no longer a block device driver. This would render a large part of the content of this wiki page outdated.<br />
<br />
= Installing to NAND =<br />
<br />
There is [[Installing_to_NAND|a nice, full howto]] available which explains how to install and boot from NAND.<br />
<br />
= nand-part =<br />
<br />
There is a utility which is part of [[Sunxi-tools|sunxi-tools]], called nand-part. It has many many issues:<br />
<br />
* The licensing is all muddled up. The author is not chinese, but the main file which only carries his copyright has chinese comments.<br />
* Barely passes as C-code. There are very few C style comments, and return values are 1 for success and 0 for failure.<br />
* Doesn't care about the size of the block device (how hard would it have been to check BLKGETSIZE64), and allows the creation of partition tables which are not contained within the bounds of the block device.<br />
* There are two known versions of allwinner nand partition tables. Instead of checking the magic and version fields, the code is fully duplicated but with different structs, and both versions of the code get run to see which one sticks. This needs to have the two versions of the structs living side by side (version the structure names!).<br />
<br />
It needs a day or so of work by a proper coder.<br />
<br />
As an extra, the format of the allwinner nand partitioning is really simple. It should be easy to write a simple interactive user interface like fdisk has, as the amount of options are really limited. '''m''', '''p''', '''n''', '''d''', '''v''', '''w''', '''q''' for the standard uses, and '''f''' for toggling a mode which gives the ability to alter the first partition and for changing the partitioning version.<br />
<br />
This utility can be redeveloped without hardware. A dump of the nand of a machines first MB, plus a dd from /dev/zero, can be presented as a loop device. For an example of this, check [[Installing_to_NAND#Accessing_the_full_backup | this]].<br />
<br />
== nand-part output ==<br />
<br />
Below is the typical output of the nand partitioning of a Mele A1000.<br />
<br />
<pre>check partition table copy 0: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 1: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 2: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 3: mbr: version 0x00000100, magic softw311<br />
OK<br />
mbr: version 0x00000100, magic softw311<br />
9 partitions<br />
partition 1: class = DISK, name = BOOTFS, partition start = 2048, partition size = 32768 user_type=0<br />
partition 2: class = DISK, name = LROOTFS, partition start = 34816, partition size = 65536 user_type=2<br />
partition 3: class = DISK, name = LSYSTEMFS, partition start = 100352, partition size = 524288 user_type=2<br />
partition 4: class = DISK, name = LDATAFS, partition start = 624640, partition size = 3145728 user_type=2<br />
partition 5: class = DISK, name = MISC, partition start = 3770368, partition size = 2048 user_type=2<br />
partition 6: class = DISK, name = LRECOVERYFS, partition start = 3772416, partition size = 65536 user_type=2<br />
partition 7: class = DISK, name = LCACHEFS, partition start = 3837952, partition size = 262144 user_type=2<br />
partition 8: class = DISK, name = env, partition start = 4100096, partition size = 4096 user_type=0<br />
partition 9: class = DISK, name = UDISK, partition start = 4104192, partition size = 0 user_type=0<br />
check partition table copy 0: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 1: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 2: mbr: version 0x00000100, magic softw311<br />
OK<br />
check partition table copy 3: mbr: version 0x00000100, magic softw311<br />
OK<br />
mbr: version 0x00000100, magic softw311<br />
9 partitions<br />
partition 1: class = DISK, name = BOOTFS, partition start = 2048, partition size = 32768 user_type=0<br />
partition 2: class = DISK, name = LROOTFS, partition start = 34816, partition size = 65536 user_type=2<br />
partition 3: class = DISK, name = LSYSTEMFS, partition start = 100352, partition size = 524288 user_type=2<br />
partition 4: class = DISK, name = LDATAFS, partition start = 624640, partition size = 3145728 user_type=2<br />
partition 5: class = DISK, name = MISC, partition start = 3770368, partition size = 2048 user_type=2<br />
partition 6: class = DISK, name = LRECOVERYFS, partition start = 3772416, partition size = 65536 user_type=2<br />
partition 7: class = DISK, name = LCACHEFS, partition start = 3837952, partition size = 262144 user_type=2<br />
partition 8: class = DISK, name = env, partition start = 4100096, partition size = 4096 user_type=0<br />
partition 9: class = DISK, name = UDISK, partition start = 4104192, partition size = 0 user_type=0<br />
</pre><br />
<br />
= MTD driver =<br />
<br />
MTD U-Boot default partition table:<br />
{| class="wikitable"<br />
|-<br />
! Partition Size !! Uses<br />
|-<br />
| 1M || U-Boot SPL<br />
|-<br />
| 4M || U-Boot<br />
|-<br />
| 3M || U-Boot Enviroment<br />
|-<br />
| 9M || Packimg(combine kernel & script.bin)<br />
|-<br />
| 8M || Linux Kernel<br />
|-<br />
| 64M || Initramfs/Small rootfs<br />
|-<br />
| - || Uses for custom<br />
|}<br />
<br />
== MTD driver for sunxi-3.4 kernel ==<br />
[https://github.com/rgwan/linux-sunxi MTD driver for sunxi-3.4 kernel] requires [https://github.com/rgwan/u-boot-sunxi/tree/sunxi-current modified u-boot]. It is not stable and therefore not suitable for production environment.<br />
<br />
== MTD driver for mainline Linux kernel (3.14+) ==<br />
[https://github.com/bbrezillon/linux-sunxi MTD driver for Linux 3.14+] is currently in progress of [[Mainlining_Effort#Major_drivers|being reviewed]] and has [[MTD_Driver|its own page here]].<br />
<br />
= More information on BROM NAND =<br />
<br />
The BROM contains a very basic NAND driver that does not support bad blocks. This driver also does '''not''' use Chip ID to identify the part, like the Linux NAND driver does, and so it blindly attempts to read Boot0 out of Flash using a sequence of predefined configurations. For A10/A20, the configurations, in order, are as follows:<br />
<br />
{| class="wikitable"<br />
|-<br />
! Interface !! Hardware page !! Address cycles !! ECC capacity !! ECC page !! CPU<br />
|-<br />
| asynchronous || 1024 B || 5 || 64 b || 1024 B || A10/A20<br />
|-<br />
| asynchronous || 1024 B || 5 || 64 b || 512 B || A10/A20<br />
|-<br />
| asynchronous || 1024 B || 4 || 64 b || 1024 B || A10/A20<br />
|-<br />
| asynchronous || 1024 B || 4 || 64 b || 512 B || A10/A20<br />
|-<br />
| asynchronous || 8192 B || 5 || 24 b || 1024 B || A20<br />
|-<br />
| asynchronous || 8192 B || 5 || 40 b || 1024 B || A20<br />
|-<br />
| asynchronous || 4096 B || 5 || 64 b || 1024 B || A20<br />
|-<br />
| asynchronous || 4096 B || 5 || 64 b || 512 B || A20<br />
|-<br />
| DDR timing 1 || 1024 B || 5 || 64 b || 1024 B || A10/A20<br />
|-<br />
| DDR timing 2 || 1024 B || 5 || 64 b || 1024 B || A10/A20<br />
|-<br />
| DDR timing 3 || 1024 B || 5 || 64 b || 1024 B || A10/A20<br />
|-<br />
| DDR timing 1 || 1024 B || 5 || 64 b || 512 B || A10/A20<br />
|-<br />
| DDR timing 2 || 1024 B || 5 || 64 b || 512 B || A10/A20<br />
|-<br />
| DDR timing 3 || 1024 B || 5 || 64 b || 512 B || A10/A20<br />
|-<br />
| DDR timing 1 || 4096 B || 5 || 64 b || 512 B || A20<br />
|-<br />
| DDR timing 2 || 4096 B || 5 || 64 b || 512 B || A20<br />
|-<br />
| DDR timing 3 || 4096 B || 5 || 64 b || 512 B || A20<br />
|}<br />
<br />
Note that a lot of modern Flash (large page NAND) would not be supported well by the configurations available on A10, so A20 adds a whole bunch.<br />
<br />
At first, the BROM tries to use all of those configurations to read a Boot0 image starting at page 0 of Flash. However, because of bad blocks (or other considerations like partition table location), all of those options may fail. BROM will then attempt reading a Boot0 image starting at pages 0x40, 0x80, 0xC0, ..., 0x1C0. Only then will it give up and proceed with other boot options (or FEL).<br />
<br />
= Manufacturers = <br />
<br />
== SK Hynix ==<br />
<br />
==== H27UCG8T2ATR-BC ====<br />
NAND 64Gb(8192M x 8bit) Legacy MLC NAND Flash, page: 8,192 + 640 bytes, block: 256 pages = 2M + 160K bytes, device: 4180 blocks = 73,835,520 Kbits<br />
<br />
Datasheet: http://www.szyuda88.com/uploadfile/cfile/2013419135343223.pdf<br />
<br />
= See also =<br />
* [http://www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf Open NAND Flash Interface Specification].<br />
<br />
= Documents =<br />
* [[File:A33_Nand_Flash_Controller_Specification.pdf |thumbnail|A33_Nand_Flash_Controller_Specification.pdf ]]<small>(PDF, 29 pages, 2014-02-28)</small><br />
<br />
<br />
[[Category:Hardware]]</div>Winkhttps://linux-sunxi.org/index.php?title=File:A33_Nand_Flash_Controller_Specification.pdf&diff=21139File:A33 Nand Flash Controller Specification.pdf2018-03-23T15:26:21Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=File:AW_HDMI_TX_PHY_S40_Spec_V0.1.pdf&diff=20937File:AW HDMI TX PHY S40 Spec V0.1.pdf2018-01-30T06:26:23Z<p>Wink: Wink uploaded a new version of &quot;File:AW HDMI TX PHY S40 Spec V0.1.pdf&quot;</p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=File:Allwinner_DE2.0_Spec_V1.0.pdf&diff=20909File:Allwinner DE2.0 Spec V1.0.pdf2018-01-23T08:26:23Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=File:Allwinner_DE3.0_Spec_V1.0.pdf&diff=20908File:Allwinner DE3.0 Spec V1.0.pdf2018-01-23T08:23:43Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=DWC_HDMI_Controller&diff=20846DWC HDMI Controller2018-01-03T07:07:08Z<p>Wink: </p>
<hr />
<div>The [[A83T]]/[[H3]]/[[A64]]/[[A80]] SoCs use a Synopsys DesignWare HDMI controller. A80 and A83T use a PHY from Synopsys too, but H3 and A64 PHY is unknown.<br />
<br />
There is no sunxi specific documentation about this controller, so everything on this page is only guessed based on observations, trial and error and third party documentation of similar systems. Don't rely on it being 100% correct and feel free to discuss ambiguous parts.<br />
<br />
= Overview =<br />
<br />
The HDMI controller consists of two blocks, the inner real HDMI controller from Synopsys, and some outer wrapper (above address 0x10000) scrambling the addresses and locking read access of the inner controller. On H3/A64 the outer block also provides configuration registers for the PHY. A80 might not have the outer part, this has to be checked.<br />
<br />
== Clocks ==<br />
<br />
(A80/A83T/A64 not checked yet, might be different there)<br />
<br />
=== H3 ===<br />
<br />
There are three clocks: BUS_CLK_HDMI_GATE, HDMI_SLOW_CLK, PLL3_CLK. HDMI_CLK seems to be unused, leaving it disabled or changing dividers has no effect.<br />
<br />
HDMI_SLOW_CLK is the actual module clock, used by the inner controller for configuration and low-speed interfaces. Everything except the high-speed data is clocked from this.<br />
<br />
PLL3_CLK is input to the PHY PLL, which provides a 1-16 pre-divider to match the pixel clock from TCON. This PLL generates the pixel/TMDS clocks and feeds them back to the inner controller as required.<br />
<br />
== Resets ==<br />
<br />
There are two resets (A80 not checked yet), HDMI0_RST and HDMI1_RST.<br />
<br />
HDMI0_RST resets the inner controller.<br />
<br />
HDMI1_RST resets the outer wrapper (and at least on H3/A64 the PHY too).<br />
<br />
= Register Guide =<br />
<br />
Base address: 0x01ee0000 (sun8i/sun50i), 0x03d00000 (sun9i)<br />
<br />
=== HDMI_READ_EN ===<br />
{{REG|HDMI_READ_EN|offset=0x10010|<br />
{{REG/FIELD| 31:0 | HDMI_READ_EN<br />
|mode=W<br />
|values=<pre><br />
0x54524545 = enable read access<br />
0x57415452 = disable read access<br />
</pre>}}<br />
}}<br />
<br />
=== HDMI_UNSCRAMBLE_ADDR ===<br />
{{REG|HDMI_UNSCRAMBLE_ADDR|offset=0x10014|<br />
{{REG/FIELD| 31:0 | HDMI_UNSCRAMBLE_ADDR<br />
|mode=W<br />
|values=<pre><br />
0x42494E47 = unscramble addresses<br />
0 = scramble addresses<br />
</pre><br />
|description=Unsrambling restores same addresses as they are described in i.MX6 manual.</br><br />
NOTE: Be sure to make dummy read before scrambling addresses, otherwise, if the last operation is write to HDMI register, value will be lost.}}<br />
}}<br />
<br />
== DWC HDMI Controller ==<br />
<br />
0x01ee0000 - 0x01eeffff (only byte-accessible)<br />
<br />
(A similar version of) the controller is publicly documented in the i.MX6 Reference Manual, chapter 33. <br />
There also is a mainline Linux driver for the controller in [https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/bridge/dw-hdmi.c drivers/gpu/drm/bridge/dw_hdmi.c].<br />
<br />
The design, revision, product and config IDs are 13 2a a0 c1 bf 02 fe 00 on H3/A64/A80/A83T.<br />
<br />
Now the hard part, the register addresses are obfuscated in sunxi SoCs (except A80). To use existing drivers/documentation the address bits have to be rearranged in the following way:<br />
<br />
<pre>real <-> obfuscated address bits<br />
A1 <-> A15<br />
A3 <-> A14<br />
A5 <-> A13<br />
A7 <-> A12<br />
A9 <-> A11<br />
A11 <-> A10<br />
A13 <-> A9<br />
A15 <-> A8<br />
A14 <-> A7<br />
A12 <-> A6<br />
A10 <-> A5<br />
A8 <-> A4<br />
A6 <-> A3<br />
A4 <-> A2<br />
A2 <-> A1<br />
A0 <-> A0</pre><br />
<br />
For example, to access register 0x100D (vsync width) one has to access 0x4043 on sunxi.<br />
<br />
<pre><br />
# Python functions to translate DWC registers to sunxi register value:<br />
def bitrev32(x):<br />
x = ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1)<br />
x = ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2)<br />
x = ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4)<br />
x = ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8)<br />
x = ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16)<br />
return x<br />
<br />
def dwc2sunxi(x):<br />
x = bitrev32(x) | x # put bit-reversed version in upper 16bit<br />
x = x & 0x55555555 # extract all even bits<br />
x = (x | (x >> 1)) & 0x33333333 # move all of them to lower 16 bits<br />
x = (x | (x >> 2)) & 0x0f0f0f0f # in multiple steps<br />
x = (x | (x >> 4)) & 0x00ff00ff<br />
x = (x | (x >> 8)) & 0x0000ffff<br />
return x<br />
</pre><br />
<br />
<pre><br />
def sunxi2dwc(x):<br />
x = ((x & 0xff00) << 8) | (x & 0x00ff)<br />
x = ((x << 4) | x) & 0x0f0f0f0f<br />
x = ((x << 2) | x) & 0x33333333<br />
x = ((x << 1) | x) & 0x55555555<br />
x = (bitrev32(x) | x) & 0xffff<br />
return x<br />
</pre><br />
<br />
Optimized version (bitrev32() as defined in linux bitrev.h):<br />
<br />
<pre><br />
uint16_t dwc2sunxi(uint16_t addr)<br />
{<br />
uint32_t x = bitrev32((uint32_t)addr) | (uint32_t)addr; // put bit-reversed version in upper 16bit<br />
x = x & 0x55555555; // then extract all even bits<br />
x = (x | (x >> 1)) & 0x33333333; // and move them all to the lower 16bit<br />
x = (x | (x >> 2)) & 0x0f0f0f0f; // in multiple steps<br />
x = (x | (x >> 4)) & 0x00ff00ff; // ...<br />
x = (x | (x >> 8)) & 0x0000ffff;<br />
return (uint16_t)x;<br />
}<br />
</pre><br />
<br />
== DWC HDMI PHY ==<br />
<br />
A80 and A83T use a Synopsys PHY, connected to controllers internal I2C bus. This PHY is documented in the i.MX6 Reference Manual, chapter 34, too. The existing Linux driver has support for this PHY, but SoC specific parameters are needed for configuration.<br />
<br />
== H3/A64 HDMI PHY ==<br />
<br />
The H3/A64 PHY is unknown and undocumented.<br />
<br />
The HDMI block uses PLL3 as input clock, not HDMI_CLK. It looks like the input clock has to be higher than ~165MHz to get a stable HDMI signal.<br />
<br />
Some register guessing, only notes from experiments, no facts yet:<br />
<br />
=== HDMI_H3_PHY_CTRL ===<br />
{{REG|HDMI_H3_PHY_CTRL|offset=0x10020|<br />
{{REG/FIELD| 15 | HDMI_TMDS_CLK_OUTPUT_EN | description=enable TMDS clock output }}<br />
{{REG/FIELD| 14 | HDMI_TMDS_2_OUTPUT_EN | description=enable TMDS data2 output }}<br />
{{REG/FIELD| 13 | HDMI_TMDS_1_OUTPUT_EN | description=enable TMDS data1 output }}<br />
{{REG/FIELD| 12 | HDMI_TMDS_0_OUTPUT_EN | description=enable TMDS data0 output }}<br />
}}<br />
<br />
=== HDMI_H3_PHY_PLL ===<br />
{{REG|HDMI_H3_PHY_PLL|offset=0x1002c|<br />
{{REG/FIELD| 25 | | description=enable pll? }}<br />
{{REG/FIELD| 5:0 | | description=some pll parameter }}<br />
}}<br />
<br />
=== HDMI_H3_PHY_CLK ===<br />
{{REG|HDMI_H3_PHY_CLK|offset=0x10030|<br />
{{REG/FIELD| 19 | | description= ?enable 18:16? }}<br />
{{REG/FIELD| 18:16 | | description=some pll parameter (bandwidth?) }}<br />
{{REG/FIELD| 15:12 | | description=some pll parameter }}<br />
{{REG/FIELD| 3:0 | HDMI_CLK_DIV | description=clock divider }}<br />
}}<br />
<br />
=== HDMI_H3_PHY_STATUS ===<br />
{{REG|HDMI_H3_PHY_STATUS|offset=0x10038|<br />
{{REG/FIELD| 19 | HPD | description=HPD status }}<br />
{{REG/FIELD| 16:11 | | description=some pll calibration? result }}<br />
}}<br />
<br />
=== HDMI_H3_PHY_CEC ===<br />
Note: Description field has notes found by trial and error.<br />
{{REG|HDMI_H3_PHY_CEC|offset=0x1003c|<br />
{{REG/FIELD| 7 | CTRL_SEL | default=0 | values=<pre><br />
0 - cec controller<br />
1 - reg control<br />
</pre> | description=if bit 2=0 send bit 0 on cec line }}<br />
{{REG/FIELD| 6 | / | default=0 }}<br />
{{REG/FIELD| 5 | PAD_SELO2 | default=0 | description=?}}<br />
{{REG/FIELD| 4 | PAD_SELO1 | default=0 | description=?}}<br />
{{REG/FIELD| 3 | INPUT_EN | default=0 | description=1 = disable input cec line(bit 1) If set to 1 hw tx will send but don't get ACKs}}<br />
{{REG/FIELD| 2 | OUTPUT_EN | default=0 | description=1 = pass cec line to hardware cec receiver<br /><br />
0 = pass cec line to hardware cec transmitter. Transmitting works only when bits 2:7 = 0}}<br />
{{REG/FIELD| 1 | INPUT_DATA | default=0 | description=status cec line when bit 3=0}}<br />
{{REG/FIELD| 0 | OUPUT_DATA | default=0 | description=output on cec line when bit 2=0 and 7=1 }}<br />
}}<br />
<br />
= Documents =<br />
* [[File:AW_HDMI_TX_PHY_S40_Spec_V0.1.pdf|thumbnail|AW_HDMI_TX_PHY_S40_Spec_V0.1.pdf]]<small>(PDF, 11 pages, 2018-01-03)</small><br />
<br />
[[Category:Hardware]]</div>Winkhttps://linux-sunxi.org/index.php?title=File:AW_HDMI_TX_PHY_S40_Spec_V0.1.pdf&diff=20845File:AW HDMI TX PHY S40 Spec V0.1.pdf2018-01-03T07:04:47Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=AC200&diff=20681AC2002017-12-04T09:33:10Z<p>Wink: Created page with "= Overview = The AC200 is a digital analog mix IC, which use in TV-BOX(H Series) , it is composed of '''Audio''', '''Video''' and '''EPHY''' modules. '''Audio''', communicat..."</p>
<hr />
<div>= Overview =<br />
The AC200 is a digital analog mix IC, which use in TV-BOX(H Series) , it is composed of '''Audio''', '''Video''' and '''EPHY''' modules.<br />
<br />
'''Audio''', communicate with SoC through I2s Interface, transform I2S to 2MIC and 1 lineout.<br />
<br />
'''Video''', communicate with SoC through CCIR656 Interface, transform CCIR656 to CVBS(Composite Video Broadcast Signal).<br />
<br />
'''EPHY''', communicate with SoC through MII/RMII Interface, transform to 100M ethernet.<br />
<br />
= Feature =<br />
<br />
== Audio ==<br />
*Support One I2S/PCM interface <br />
*Two audio digital-to-analog(DAC) channels <br />
**— 100dB SNR@A-weight <br />
**— Supports DAC Sample Rates from 8KHz to 192KHz <br />
*Support analog/ digital volume control<br />
*Two differential microphone inputs <br />
*One lineout output with voltage ramp <br />
*Two audio analog-to-digital(ADC) channels <br />
*— 92dB SNR@A-weight <br />
*— Supports ADC Sample Rates from 8KHz to 48KHz <br />
*Support Automatic Gain Control(AGC) adjusting the ADC recording output <br />
<br />
== Video ==<br />
*Support CCIR656 and Serial YUV interface <br />
*1 CVBS out, Support NTSC and PAL<br />
*Plug status auto detecting <br />
<br />
== EPHY ==<br />
*Support MII and RMII interface <br />
*Fully IEEE 802.3 10/100 Base-TX compliant and supports EEE <br />
*Auto negotiation and parallel detection capability for automatic speed and duplex selection <br />
*Programmable loopback mode for diagnostic <br />
*Supports WOL (Wake-On-Lan) functionality <br />
*Design for Testability with extensive testability feature and 95% fault coverage <br />
*Power consumption (100Base-TX) less than 140mW<br />
<br />
== OTHERS ==<br />
*TWI/RSB control interface, TWI up to 400Kbps, RSB up to10Mbps <br />
*Integrate Codec LDO, Core LDO, single 3.3V supply for chip <br />
*Internal OSC, 32K clock output <br />
*Internal RTC function <br />
*QFN 68-pin package, 8mm x 8mm <br />
<br />
= Block Diagram =<br />
[[File:Ac200.png|thumbnail|center]]<br />
<br />
= Relate to H6 =<br />
[[H6]] has embedded AC200, it was called ATE(Audio, TVE, EPHY) Controller. For more details, check chapter 3.20 of [[H6]] UserManual.<br />
<br />
= Documents =<br />
* [[File:AC200 Datasheet V1.1.pdf|thumbnail|AC200_Datasheet_V1.1.pdf]]<small>(PDF, 96 pages, 2017-12-04)</small></div>Winkhttps://linux-sunxi.org/index.php?title=File:AC200_Datasheet_V1.1.pdf&diff=20680File:AC200 Datasheet V1.1.pdf2017-12-04T09:27:21Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=File:Ac200.png&diff=20679File:Ac200.png2017-12-04T08:40:26Z<p>Wink: </p>
<hr />
<div></div>Winkhttps://linux-sunxi.org/index.php?title=H6&diff=20653H62017-11-16T02:42:02Z<p>Wink: </p>
<hr />
<div>{{Infobox SoC<br />
| manufacturer = Allwinner<br />
| process = 28nm<br />
| cpu = Quad-Core ARM Cortex-A53 @ ? (BSP uses 1.8GHz)<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR2/LPDDR3/DDR3/DDR4<br />
| gpu = Mali-T720 MP2 @ 600Mhz<br />
| vpu = <br />
| apu = <br />
| video = HDMI 2.0 with HDCP 2.2, TV CVBS, RGB LCD<br />
| audio = I2S, PCM, TDM<br />
| network = GBit MAC, integrated 10/100M PHY<br />
| storage = MMC, NAND<br />
| usb = 1x OTG, 1x Host 2.0, 1x Host 3.0<br />
| other = PCIE 2.0 1x<br />
| release_date = June 2017<br />
| website = [http://www.allwinnertech.com/index.php?c=product&a=index&id=66 Product Page]<br />
}}<br />
<br />
Allwinner [[H6]] (sun50iw6p1) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali-T720 MP2 GPU from ARM. The Allwinner H6 is an OTT SoC.<br />
<br />
=Overview=<br />
Mainline support not started yet due to lack of boards. Xunlong and Pine64 are working on H6 SBCs.<br />
<br />
== Differences / New features (compared to H5) ==<br />
<br />
=== High level differences ===<br />
* addition of PCIe support<br />
** single lane PCIe 2.0<br />
** totally undocumented software interface<br />
* addition of USB 3.0 host<br />
* Mali T720 instead of Mali 450<br />
* DDR4 DRAM support<br />
* addition of IOMMU<br />
** though only connected to display controller and video codecs<br />
* (New?) Audio Hub component<br />
<br />
=== programming model/driver level differences ===<br />
* heavily changed memory map (UART0 at 0x05000000, for instance)<br />
** SRAM locations moved around as well (SRAM A1 at 0x2000 now)<br />
* bus clock gates and device reset control now grouped by devices and merged into one register (high 16 bits reset, low 16 bits clock gates) <br />
* DMA controller changed (more than 32 ports, but still limited to 32 bit addresses)<br />
* no GPIO port A and B<br />
<br />
=H6 SoC Features=<br />
* CPU<br />
** ARM Cortex-A53 Quad-Core<br />
** 512KB L2-Cache (shared between four cores)<br />
** 32 KB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
* GPU<br />
** ARM Mali-T720 MP2<br />
** Featuring 2 unified shader cores<br />
** Complies with OpenGL ES 3.0, OpenCL 1.2<br />
* Memory<br />
** DDR3/DDR4/LPDDR2/LPDDR3 controller<br />
** NAND Flash controller and 64-bit ECC, supports full disk encryption<br />
** 3 MMC controllers, in which MMC2 (eMMC controller) supports full disk encryption<br />
* Video<br />
** Ultra HD 4k and Full HD 1080p video decoding of MPEG-2, MPEG-4 SP/ASP GMC, H.263, H.264, H.265, WMV9/VC-1, and VP8<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@60fps encoding<br />
** 3840×1080,1920x2160 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** Integrated HDMI V2.0 with HDCP2.2 4K@60fps<br />
** TV CVBS output<br />
** RGB LCD output<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV422 sensor<br />
** Support CCIR656 protocol fot NTSC and PAL<br />
** 5M CMOS sensor support<br />
** Support video capture resolution up to 1080p@30fps<br />
* Audio<br />
** Two audio digital-to-analog(DAC) channels 92dB SNR<br />
** Two differential microphone inputs (one low-noise)<br />
** Stereo Linein input<br />
** TDM Digital Microphone input<br />
* Embedded Controller:<br />
** There might be an [[AR100]] controller.<br />
* Thermal Sensor Controller (TSC) providing over-temperature protection interrupt and over-temperature alarm interrupt<br />
* AXP805 PMIC<br />
* package: FBGA451, 15 mm x 15 mm, 0.65 mm Pitch<br />
<br />
=Documents=<br />
* [[File:Allwinner_H6_V200_Datasheet_V1.1.pdf]] <small>(PDF, 80 pages, 2017-11-14)</small><br />
* [[File:Allwinner_H6_V200_User_Manual_V1.1.pdf]] <small>(PDF, 965 pages, 2017-11-14)</small><br />
<br />
[[Category:System on Chip]]</div>Wink