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2024-03-29T12:53:56Z
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https://linux-sunxi.org/index.php?title=USB_OTG_Controller_Register_Guide&diff=24915
USB OTG Controller Register Guide
2022-06-23T20:10:08Z
<p>Increscent: Added link to Mentor Graphics Documentation</p>
<hr />
<div>= USB Vocabulary =<br />
'''HCD''' - Host Controller Driver<br />
<br />
'''UDC''' - USB Device Controller<br />
<br />
= USB OTG =<br />
All Allwinner A-series SoCs come with one USB OTG controller.<br />
The controller has been identified as a Mentor Graphics Inventra HDRC<br />
(High-speed Dual Role Controller), which is supported by the "musb" driver.<br />
However, the register addresses are scrambled.<br />
<br />
The A20 manual lists the following features<br />
* Complies with USB 2.0 specification<br />
* Supports high-speed, full-speed, and low-speed in host mode<br />
* Supports high-speed and full-speed in device mode<br />
* 64 byte endpoint 0 for control transfer<br />
* Supports up to 5 user configurable endpoints for bulk, isochronous, control, and interrupt bi-directional transfers<br />
<br />
The USB OTG controller is connected to a port controller.<br />
Only the data pins are exported from the SoC.<br />
The port controller is also used to control or tune the USB PHYs<br />
for the other USB host controllers.<br />
<br />
== Info ==<br />
* USB OTG Controller base address: 0x01c13000<br />
* USB Port Controller base address: 0x01c13400<br />
<br />
== USB OTG Controller Registers ==<br />
=== Default Map ===<br />
<pre><br />
sun7i# md 0x01c13000 0x100<br />
01c13000: 6f427dee 6f427dee 6f427dee 6f427dee .}Bo.}Bo.}Bo.}Bo<br />
01c13010: 6f427dee 6f427dee 00000000 00000000 .}Bo.}Bo........<br />
01c13020: 00000000 00000000 00000000 00000000 ................<br />
01c13030: 00000000 00000000 00000000 00000000 ................<br />
01c13040: 00008020 00000000 00000000 00000000 ...............<br />
01c13050: 00000000 00000000 00000000 00000000 ................<br />
01c13060: 00000000 00000000 00000000 00000000 ................<br />
01c13070: 00000000 00000000 00000000 00000000 ................<br />
01c13080: 00000000 00000000 00000000 00000000 ................<br />
01c13090: 00000000 00000000 00000000 00000000 ................<br />
01c130a0: 00000000 00000000 00000000 00000000 ................<br />
01c130b0: 00000000 00000000 00000000 00000000 ................<br />
01c130c0: 000b55de 5c727780 0000003c 00000000 .U...wr\<.......<br />
01c130d0: 00000000 05e64074 00000000 00000000 ....t@..........<br />
01c130e0: 00000000 00000000 00000000 00000000 ................<br />
01c130f0: 00000000 00000000 00000000 00000000 ................<br />
01c13100: 00000000 00000000 00000000 00000000 ................<br />
01c13110: 00000000 00000000 00000000 00000000 ................<br />
01c13120: 00000000 00000000 00000000 00000000 ................<br />
01c13130: 00000000 00000000 00000000 00000000 ................<br />
01c13140: 00000000 00000000 00000000 00000000 ................<br />
01c13150: 00000000 00000000 00000000 00000000 ................<br />
01c13160: 00000000 00000000 00000000 00000000 ................<br />
01c13170: 00000000 00000000 00000000 00000000 ................<br />
01c13180: 00000000 00000000 00000000 00000000 ................<br />
01c13190: 00000000 00000000 00000000 00000000 ................<br />
01c131a0: 00000000 00000000 00000000 00000000 ................<br />
01c131b0: 00000000 00000000 00000000 00000000 ................<br />
01c131c0: 00000000 00000000 00000000 00000000 ................<br />
01c131d0: 00000000 00000000 00000000 00000000 ................<br />
01c131e0: 00000000 00000000 00000000 00000000 ................<br />
01c131f0: 00000000 00000000 00000000 00000000 ................<br />
01c13200: 00000000 00000000 00000000 00000000 ................<br />
01c13210: 00000000 00000000 00000000 00000000 ................<br />
01c13220: 00000000 00000000 00000000 00000000 ................<br />
01c13230: 00000000 00000000 00000000 00000000 ................<br />
01c13240: 00000000 00000000 00000000 00000000 ................<br />
01c13250: 00000000 00000000 00000000 00000000 ................<br />
01c13260: 00000000 00000000 00000000 00000000 ................<br />
01c13270: 00000000 00000000 00000000 00000000 ................<br />
01c13280: 00000000 00000000 00000000 00000000 ................<br />
01c13290: 00000000 00000000 00000000 00000000 ................<br />
01c132a0: 00000000 00000000 00000000 00000000 ................<br />
01c132b0: 00000000 00000000 00000000 00000000 ................<br />
01c132c0: 00000000 00000000 00000000 00000000 ................<br />
01c132d0: 00000000 00000000 00000000 00000000 ................<br />
01c132e0: 00000000 00000000 00000000 00000000 ................<br />
01c132f0: 00000000 00000000 00000000 00000000 ................<br />
01c13300: 00000000 00000000 00000000.00000000 ................<br />
01c13310: 00000000 00000000 00000000 00000000 ................<br />
01c13320: 00000000 00000000 00000000 00000000 ................<br />
01c13330: 00000000 00000000 00000000 00000000 ................<br />
01c13340: 00000000 00000000 00000000 00000000 ................<br />
01c13350: 00000000 00000000 00000000 00000000 ................<br />
01c13360: 00000000 00000000 00000000 00000000 ................<br />
01c13370: 00000000 00000000 00000000 00000000 ................<br />
01c13380: 00000000 00000000 00000000 00000000 ................<br />
01c13390: 00000000 00000000 00000000 00000000 ................<br />
01c133a0: 00000000 00000000 00000000 00000000 ................<br />
01c133b0: 00000000 00000000 00000000 00000000 ................<br />
01c133c0: 00000000 00000000 00000000 00000000 ................<br />
01c133d0: 00000000 00000000 00000000 00000000 ................<br />
01c133e0: 00000000 00000000 00000000 00000000 ................<br />
01c133f0: 00000000 00000000 00000000 00000000 ................<br />
</pre><br />
<br />
=== Common Registers ===<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! MUSB offset<br />
! Size<br />
! Description<br />
! Note<br />
|-<br />
| <tt>PCTL / POWER</tt><br />
| <tt>0x40</tt><br />
| <tt>0x01</tt><br />
| <tt>1 B</tt><br />
| USB Power Control<br />
|<br />
|-<br />
| <tt>DEVCTL</tt><br />
| <tt>0x41</tt><br />
| <tt>0x60</tt><br />
| <tt>1 B</tt><br />
| OTG Device Control<br />
|<br />
|-<br />
| <tt>EPIND / INDEX</tt><br />
| <tt>0x42</tt><br />
| <tt>0x0E</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>VEND0</tt><br />
| <tt>0x43</tt><br />
| <tt>0x??</tt><br />
| <tt>1 B</tt><br />
| Vendor specific register<br />
| Controls whether to use DMA mode<br />
|-<br />
| <tt>INTTx / INTRTX</tt><br />
| <tt>0x44</tt><br />
| <tt>0x02</tt><br />
| <tt>2 B</tt><br />
| Transmit interrupt status<br />
|<br />
|-<br />
| <tt>INTRx / INTRRX</tt><br />
| <tt>0x46</tt><br />
| <tt>0x04</tt><br />
| <tt>2 B</tt><br />
| Receive interrupt status<br />
|<br />
|-<br />
| <tt>INTTxE / INTRTXE</tt><br />
| <tt>0x48</tt><br />
| <tt>0x06</tt><br />
| <tt>2 B</tt><br />
| Transmit interrupt mask<br />
|<br />
|-<br />
| <tt>INTRxE / INTRRXE</tt><br />
| <tt>0x4A</tt><br />
| <tt>0x08</tt><br />
| <tt>2 B</tt><br />
| Receive interrupt mask<br />
|<br />
|-<br />
| <tt>INTUSB / INTRUSB</tt><br />
| <tt>0x4C</tt><br />
| <tt>0x0A</tt><br />
| <tt>1 B</tt><br />
| USB function interrupt status<br />
|<br />
|-<br />
| <tt>INTUSBE / INTRUSBE</tt><br />
| <tt>0x50</tt><br />
| <tt>0x0B</tt><br />
| <tt>1 B</tt><br />
| USB function interrupt mask<br />
|<br />
|-<br />
| <tt>FRNUM / FRAME</tt><br />
| <tt>0x54</tt><br />
| <tt>0x0C</tt><br />
| <tt>2 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>EPINFO</tt><br />
| <tt>0x78</tt><br />
| <tt>0x78</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>RAMINFO</tt><br />
| <tt>0x79</tt><br />
| <tt>0x79</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>LINKINFO</tt><br />
| <tt>0x7A</tt><br />
| <tt>0x7A</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>VPLEN</tt><br />
| <tt>0x7B</tt><br />
| <tt>0x7B</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>HSEOF / HS_EOF1</tt><br />
| <tt>0x7C</tt><br />
| <tt>0x7C</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>FSEOF / FS_EOF1</tt><br />
| <tt>0x7D</tt><br />
| <tt>0x7D</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|-<br />
| <tt>LSEOF / LS_EOF1</tt><br />
| <tt>0x7E</tt><br />
| <tt>0x7E</tt><br />
| <tt>1 B</tt><br />
| <br />
|<br />
|}<br />
<br />
==== PCTL / POWER ====<br />
Default value: 0x20<br /><br />
Offset: 0x40<br /><br />
MUSB offset: 0x01<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>ISOUPDATE</tt><br />
| <tt>7</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
| (device only)<br />
|-<br />
| <tt>SOFTCONN</tt><br />
| <tt>6</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
| (device only)<br />
|-<br />
| <tt>HSENAB</tt><br />
| <tt>5</tt><br />
| <tt>?</tt><br />
| <tt>1</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>HSMODE</tt><br />
| <tt>4</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>RESET</tt><br />
| <tt>3</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>RESUME</tt><br />
| <tt>2</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>SUSPENDM</tt><br />
| <tt>1</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>ENSUSPEND</tt><br />
| <tt>0</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|}<br />
<br />
==== DEVCTL ====<br />
Default value: 0x80<br /><br />
Offset: 0x41<br /><br />
MUSB offset: 0x60<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>B_DEVICE / BDEVICE</tt><br />
| <tt>7</tt><br />
| <tt>?</tt><br />
| <tt>1</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>FS_DEV / FSDEV</tt><br />
| <tt>6</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>LS_DEV / LSDEV</tt><br />
| <tt>5</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>VBUS</tt><br />
| <tt>4:3</tt><br />
| <tt>?</tt><br />
| <tt>10</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>HOST_MODE / HM</tt><br />
| <tt>2</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>HOST_REQ / HR</tt><br />
| <tt>1</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>SESSION</tt><br />
| <tt>0</tt><br />
| <tt>?</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|}<br />
<br />
==== VEND0 ====<br />
Default value: 0x20<br /><br />
Offset: 0x43<br /><br />
MUSB offset: 0x??<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>DRQ_SEL</tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|-<br />
| <tt>BUS_SEL</tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt> </tt><br />
|<br />
|}<br />
<br />
=== Endpoint Registers ===<br />
To access these under indexed mode, you must first write the endpoint number to the INDEX register.<br />
<br />
==== Endpoint 0 ====<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! MUSB offset<br />
! Size<br />
! Description<br />
! Note<br />
|-<br />
| <tt>CSR0</tt><br />
| <tt>0x82</tt><br />
| <tt>0x12</tt><br />
| <tt>2 B</tt><br />
| MUSB main control / status register<br />
| <br />
|-<br />
| <tt>COUNT0</tt><br />
| <tt>0x88</tt><br />
| <tt>0x18</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>EP0TYPE / TYPE0</tt><br />
| <tt>0x8A</tt><br />
| <tt>0x1A</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>NAKLIMIT0</tt><br />
| <tt>0x8B</tt><br />
| <tt>0x1B</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>CONFIGDATA</tt><br />
| <tt>0xC0</tt><br />
| <tt>0x1F</tt><br />
| <tt>2 B</tt><br />
| MUSB core hardware feature flags<br />
| <br />
|}<br />
<br />
==== Endpoint 1 ~ N ====<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! MUSB offset<br />
! Size<br />
! Description<br />
! Note<br />
|-<br />
| <tt>TXMAXP</tt><br />
| <tt>0x80</tt><br />
| <tt>0x10</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>TXCSR</tt><br />
| <tt>0x82</tt><br />
| <tt>0x12</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>RXMAXP</tt><br />
| <tt>0x84</tt><br />
| <tt>0x14</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>RXCSR</tt><br />
| <tt>0x86</tt><br />
| <tt>0x16</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>RXCOUNT</tt><br />
| <tt>0x88</tt><br />
| <tt>0x18</tt><br />
| <tt>2 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>TXTYPE</tt><br />
| <tt>0x8C</tt><br />
| <tt>0x1A</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>TXINTERVAL</tt><br />
| <tt>0x8D</tt><br />
| <tt>0x1B</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>RXTYPE</tt><br />
| <tt>0x8E</tt><br />
| <tt>0x1C</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>RXINTERVAL</tt><br />
| <tt>0x8F</tt><br />
| <tt>0x1D</tt><br />
| <tt>1 B</tt><br />
| <br />
| <br />
|-<br />
| <tt>TXFIFOSZ</tt><br />
| <tt>0x90</tt><br />
| <tt>0x62</tt><br />
| <tt>1 B</tt><br />
| TX FIFO size<br />
| size = 2 ^ (TXFIFOSZ + 3)<br />
|-<br />
| <tt>RXFIFOSZ</tt><br />
| <tt>0x94</tt><br />
| <tt>0x63</tt><br />
| <tt>1 B</tt><br />
| RX FIFO size<br />
| size = 2 ^ (RXFIFOSZ + 3)<br />
|-<br />
| <tt>TXFIFOADD</tt><br />
| <tt>0x92</tt><br />
| <tt>0x64</tt><br />
| <tt>2 B</tt><br />
| TX FIFO offset<br />
| TXFIFOADD = offset >> 3<br />
|-<br />
| <tt>RXFIFOADD</tt><br />
| <tt>0x96</tt><br />
| <tt>0x66</tt><br />
| <tt>2 B</tt><br />
| RX FIFO offset<br />
| RXFIFOADD = offset >> 3<br />
|}<br />
<br />
== USB Port Controller Registers ==<br />
<br />
=== Default Map ===<br />
<pre><br />
sun7i# md 0x01c13400 0x4<br />
01c13400: 40000000 00000000 00000000 00000000 ...@............<br />
</pre><br />
<br />
=== Register List ===<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
! Note<br />
|-<br />
| <tt>ISCR</tt><br />
| <tt>0x0</tt><br />
| <tt>4 B</tt><br />
| Interrupt status / control register<br />
|<br />
|-<br />
| <tt>PHY_CTRL</tt><br />
| <tt>0x4</tt><br />
| <tt>2 B</tt><br />
| PHY control<br />
|<br />
|-<br />
| <tt>PHY_BIST</tt><br />
| <tt>0x8</tt><br />
| <tt>4 B</tt><br />
| unknown<br />
|<br />
|-<br />
| <tt>PHY_TUNE</tt><br />
| <tt>0xC</tt><br />
| <tt>4 B</tt><br />
| PHY tuning<br />
|<br />
|}<br />
<br />
=== ISCR ===<br />
Default value: 0x40000000<br /><br />
Offset: 0x0<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>no operation</tt><br />
| <tt>31</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|<br />
|-<br />
| <tt>VBUS_VALID_FROM_DATA</tt><br />
| <tt>30</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Invalid<br />
1 = Valid<br />
</tt><br />
|<br />
VBUS_VALID_FROM_DATA = !<br />
(EXT_DM_STATUS | EXT_DP_STATUS)<br />
|-<br />
| <tt>VBUS_VALID_FROM_VBUS</tt><br />
| <tt>29</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Invalid<br />
1 = Valid<br />
</tt><br />
| Status of External VBUS pin<br />
(pin not available on A10/A20)<br />
|-<br />
| <tt>EXT_ID_STATUS</tt><br />
| <tt>28</tt><br />
| <tt>Read</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Low<br />
1 = High<br />
</tt><br />
| Status of External ID pin<br />
(pin not available on A10/A20)<br />
|-<br />
| <tt>EXT_DM_STATUS</tt><br />
| <tt>27</tt><br />
| <tt>Read</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Low<br />
1 = High<br />
</tt><br />
| Status of D- pin<br />
|-<br />
| <tt>EXT_DP_STATUS</tt><br />
| <tt>26</tt><br />
| <tt>Read</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Low<br />
1 = High<br />
</tt><br />
| Status of D+ pin<br />
|-<br />
| <tt>MERGED_VBUS_STATUS</tt><br />
| <tt>25</tt><br />
| <tt>Read</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Low<br />
1 = High<br />
</tt><br />
|<br />
MERGED_VBUS_STATUS = FORCE_VBUS | (VBUS_VALID_FROM_DATA ? VBUS_VALID_FROM_VBUS)<br />
|-<br />
| <tt>MERGED_ID_STATUS</tt><br />
| <tt>24</tt><br />
| <tt>Read</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Low<br />
1 = High<br />
</tt><br />
| MERGED_ID_STATUS = EXT_ID_STATUS | FORCE_ID<br />
|-<br />
| <tt>no operation</tt><br />
| <tt>23:18</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|<br />
|-<br />
| <tt>ID_PULLUP_EN</tt><br />
| <tt>17</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable pull-up<br />
1 = Enable pull-up<br />
</tt><br />
| Controls pull-up on ID pin<br />
|-<br />
| <tt>DPDM_PULLUP_EN</tt><br />
| <tt>16</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable pull-up<br />
1 = Enable pull-up<br />
</tt><br />
| Controls pull-up on USB D+/D- pins<br />
|-<br />
| <tt>FORCE_ID</tt><br />
| <tt>15:14</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
00 = Disable<br />
01 = unknown<br />
10 = Force ID to low<br />
11 = Force ID to high<br />
</tt><br />
| Force internal ID pin state<br />
|-<br />
| <tt>FORCE_VBUS_VALID</tt><br />
| <tt>13:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
00 = Disable<br />
01 = unknown<br />
10 = Force VBUS valid to low<br />
11 = Force VBUS valid to high<br />
</tt><br />
| Force internal VBUS pin state<br />
|-<br />
| <tt>VBUS_VALID_SRC</tt><br />
| <tt>11:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
00 = <br />
01 = <br />
10 = <br />
11 = <br />
</tt><br />
| unknown<br />
|-<br />
| <tt>no operation</tt><br />
| <tt>9:8</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|<br />
|-<br />
| <tt>HOSC_EN</tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = <br />
1 = <br />
</tt><br />
| <br />
|-<br />
| <tt>VBUS_CHANGE_DETECT</tt><br />
| <tt>6</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = No change<br />
1 = Changed<br />
</tt><br />
| Was VBUS changed? <br /><br />
Write 1 to clear<br />
|-<br />
| <tt>ID_CHANGE_DETECT</tt><br />
| <tt>5</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = No change<br />
1 = Changed<br />
</tt><br />
| Was ID changed? <br /><br />
Write 1 to clear<br />
|-<br />
| <tt>DPDM_CHANGE_DETECT</tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = No change<br />
1 = Changed<br />
</tt><br />
| Was D+/D- changed? <br /><br />
Write 1 to clear<br />
|-<br />
| <tt>IRQ_ENABLE</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable<br />
1 = Enable<br />
</tt><br />
| Interrupt on wake<br />
|-<br />
| <tt>VBUS_CHANGE_DETECT_EN</tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable<br />
1 = Enable<br />
</tt><br />
| Interrupt on VBUS change<br />
|-<br />
| <tt>ID_CHANGE_DETECT_EN</tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable<br />
1 = Enable<br />
</tt><br />
| Interrupt on ID change<br />
|-<br />
| <tt>DPDM_CHANGE_DETECT_EN</tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0 = Disable<br />
1 = Enable<br />
</tt><br />
| Interrupt on D+/D- status change<br />
|}<br />
<br />
=== PHY_CTRL ===<br />
Default value: 0x0000<br /><br />
Offset: 0x4<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>no operation</tt><br />
| <tt>31:19</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|<br />
|-<br />
| <tt>DATA</tt><br />
| <tt>16 + i ( i = 0 ~ 2 )</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Data bit read back, one bit per PHY<br />
|-<br />
| <tt>ADDR</tt><br />
| <tt>15:8</tt><br />
| <tt>Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Bit address to write to<br />
|-<br />
| <tt>DATA</tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Data bit to write<br />
|-<br />
| <tt>USBC_i</tt><br />
| <tt>i (i = 0 ~ 2)</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Pulse the corresponding bit to signal writing to a PHY<br />
|}<br />
<br />
== USB PHY Control Register Addresses ==<br />
{| class="wikitable" |<br />
! Name<br />
! Bit Address<br />
! Size<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>SET_PLL_BW</tt><br />
| <tt>0x03</tt><br />
| <tt>2</tt><br />
| <tt>0x2</tt><br />
| <tt>0x0 ~ 0x3</tt><br />
| Common to all PHYs, set USB PLL bandwidth<br />
|-<br />
| <tt>RES45_CAL_EN</tt><br />
| <tt>0x0c</tt><br />
| <tt>1</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0x0: Disable<br />
0x1: Enable<br />
</tt><br />
| Common to all PHYs, control 45 Ohm resistor calibration (?)<br />
|-<br />
| <tt>SET_TX_AMPLITUDE_TUNE</tt><br />
| <tt>0x20</tt><br />
| <tt>2</tt><br />
| <tt>0x0</tt><br />
| <tt>0x0 ~ 0x3</tt><br />
| Set USB TX signal amplitude<br />
|-<br />
| <tt>SET_TX_SLEWRATE_TUNE</tt><br />
| <tt>0x22</tt><br />
| <tt>3</tt><br />
| <tt>0x5</tt><br />
| <tt>0x0 ~ 0x7</tt><br />
| Set USB TX signal slew rate<br />
|-<br />
| <tt>SET_VBUS_VALID_THRESHOLD</tt><br />
| <tt>0x25</tt><br />
| <tt>2</tt><br />
| <tt>0x2</tt><br />
| <tt>0x0 ~ 0x3</tt><br />
| Set USB VBUS valid threshold<br />
|-<br />
| <tt>OTG_FUNC_ENABLE</tt><br />
| <tt>0x28</tt><br />
| <tt>1</tt><br />
| <tt>0x1</tt><br />
| <tt><br />
0x0: Disable<br />
0x1: Enable<br />
</tt><br />
| Control USB OTG function<br />
|-<br />
| <tt>VBUS_DET_ENABLE</tt><br />
| <tt>0x29</tt><br />
| <tt>1</tt><br />
| <tt>0x1</tt><br />
| <tt><br />
0x0: Disable<br />
0x1: Enable<br />
</tt><br />
| Control USB VBUS detection<br />
|-<br />
| <tt>SET_DISCON_DET_THRESHOLD</tt><br />
| <tt>0x2a</tt><br />
| <tt>3</tt><br />
| <tt>0x1</tt><br />
| <tt>0x0 ~ 0x3 </tt><br />
| Control USB disconnect detection threshold<br />
|}<br />
<br />
= Documentation =<br />
<br />
* [[File:Musbmhdrc.pdf]]<br />
<br />
[[Category:A10 Register guide]]<br />
[[Category:A13 Register guide]]<br />
[[Category:A20 Register guide]]<br />
[[Category:USB OTG]]</div>
Increscent
https://linux-sunxi.org/index.php?title=File:Musbmhdrc.pdf&diff=24914
File:Musbmhdrc.pdf
2022-06-23T20:07:26Z
<p>Increscent: Mentor Graphics Dual-Role OTG Controller</p>
<hr />
<div>Mentor Graphics Dual-Role OTG Controller</div>
Increscent