Olimex A20-OLinuXino-Lime2

The A20 Olinuxino LIME2 is an OSHW board produced by Olimex.

The A20-OLinuXino-LIME2 is an upgrade of the Olimex A20-OLinuXino-Lime, but it comes with 1GiB RAM and gigabit ethernet. There are also two extra variants with onboard storage: A20-OLinuXIno-LIME2-4GB with 4GB NAND and A20-OLinuXino-LIME2-eMMC with 4GB eMMC.

= Identification =

The board is marked as A20-OLinuXino-Lime on both the top and bottom of the PCB.

Note that it is not marked as Lime2. The Lime2 variant can be distinguished by the presence of two dram chips on the top of the board between the SoC and the USB connectors, also the ethernet phy is on the bottom of the board instead of the top.

= Sunxi support =

Current status
Supported.
 * Mainline kernel patches posted to linux-arm-kernel mailing list 2014-09-28
 * Mainline u-boot patches posted to u-boot mailing list 2014-09-28

Manual build
You can build things for yourself by following our Manual build howto and by choosing from the configurations available below.

Sunxi/Legacy U-Boot
Use the A20-OLinuXino_Lime2 build target. _FEL version is also available for USB booting.

Mainline U-Boot
Use the A20-OLinuXino-Lime2_defconfig build target.

Sunxi/Legacy Kernel
Use the a20-olinuxino_lime2.fex file. (Please note that this fex file adopted DRAM clock setting from the Lime2's predecessor - only dram_tpr4 differs for unknown reasons. Using this fex file the DRAM is clocked with just 384 MHz, which costs some few percent performance depending on the application used.)

Mainline kernel
Use the sun7i-a20-olinuxino-lime2.dtb device-tree binary.

= Tips, Tricks, Caveats =

FEL mode
The Recovery button (under sata connector, nearest hdmi connector) triggers FEL mode.



Expansion ports
The internal GPIO headers appear to be mirrored compared to the original Lime boards. Due to this there are specific A20-OLinuXino-Lime2-UEXT adapters, however as of 2014-09-28 these do not appear to be available directly from the Olimex shop.

SATA power connector
Unlike other sunxi boards the Olimex boards don't use the JST XH 0.1"/2.5mm header for SATA power but the smaller JST PHR-2 header normally used for connecting LiPo batteries.

DRAM clock speed limit
DRAM is clocked at 480 MHz by the hardware vendor (in fact even 532Mhz is mentioned in the blog). But the reliability still needs to be verified. The board uses somewhat non-standard resistors for ZQ calibration (ZQ = 330 Ohm, SZQ = 330 Ohm), but at least they seem to be the same in Lime2 revisions from Rev.B to Rev.E according to the board schematics. Still it's best to always mention the board revision in the results table in order to avoid any surprises.

= Adding a serial port =



There is a clearly marked UART0 connector on the edge of the board beside the ethernet connector. All you have to do is attach some leads according to our UART howto.

= Pictures =

= See also =


 * Olimex A10-OLinuXino-Lime
 * Olimex A20-OLinuXino-Lime
 * Lime2 schematics & CAD files

Manufacturer images
Olimex images for Lime2