AR100

= Overview =

The AR100 core in A31 is responsible for managing deep power save modes where the rest of the SoC is shut down. It's an OpenRISC based core with code loaded into internal SRAM.

= Specifications =


 * Name: AR100
 * Architecture: OpenRISC
 * Version: probably a version older than rev 808
 * Cache: 4K icache, no dcache
 * Byte ordering: Internally big endian. Byte-swapped on the data & instruction busses to little endian.

= SPR data =

= Memory Map =

- 0x40000- Interrupt vectors. Only one word at each 0x100 boundary - 0x44000- Internal SRAM - Have access to the same I/O as the main A31 core - All accesses are automatically byteswapped

= Known issues = It is a quite old OpenRISC core so likely have many issues - exceptions in delay slots?

= Links =
 * https://github.com/skristiansson/ar100-info/
 * http://opencores.org/or1k/OR1200_OpenRISC_Processor
 * http://git.openrisc.net/