INTC

Allwinner SoCs have a bespoke interrupt controller. It was originally the only interrupt controller on the chip. On SoCs with a GIC (sun6i and newer), it sits between the NMI pin and a GIC input. It is responsible for controlling the NMI trigger type (high/low/rising/falling). On SoCs with an AR100, it serves as the interrupt controller for that CPU.

INTC
sun4i/sun5i SoCs (A10, A13) did not have a GIC, and used this hardware exclusively. See the A13 manual for a detailed register description.

Driver
This interrupt controller uses the drivers/irqchip/irq-sun4i.c driver in Linux.

NMI Controller
After Allwinner switched to using a GIC, but before they added a power management coprocessor, there was no need for a full INTC. SoCs like the A20 have a stripped-down version of the hardware, that only manages the trigger type for the NMI.

Driver
This interrupt controller uses the drivers/irqchip/irq-sunxi-nmi.c driver in Linux.

R_INTC
The R_INTC is the secondary interrupt controller in sun8i/sun50i SoCs that contain the AR100 coprocessor. It is closely related to the original sun4i INTC. While stripped down some, it is much closer to the original feature set than it is to the A20 NMI controller.

Hardware Architecture
See the A13 manual for register descriptions. The image below shows how the various registers control the IRQ flow. Note that the NMI IRQ has a latch (separate from any rising/falling trigger) that must be ACKed before the output to the GIC will be deasserted.



The Allwinner AR100 blob only has code to access the first register of each type, so that is probably all that is implemented. The largest known IRQ number is 0x11, the MSGBOX IRQ on the A64/H5.

The priority logic appears not to be implemented, as setting any bit in the RESP register stops the AR100 from receiving interrupt exceptions.

Driver
This interrupt controller currently uses the drivers/irqchip/irq-sunxi-nmi.c driver in Linux as well, but a new driver is needed to support preconfiguring the wakeup IRQs for the AR100.