Reduced Serial Bus

The RSBTM is a push-pull two wire bus developed by Allwinner Technology. Its primary (only?) use is to connect an (Allwinner) SoC to an AXP-series power management controller (PMIC) from X-Powers.

= Features =
 * Related to the SMBus, which in turn is derived from I²C.
 * Connects to the SoC-internal AMBA Peripheral Bus (APB).
 * Supports speeds up to 20 MHz (in contrast to the 400 KHz of I²C).
 * Supports multiple devices, although most (all?) boards connect the pins to the only on-board PMIC.
 * Multiplexed with some I²C pins (allows driving slaves with I²C for compatibility).
 * Supports programmable output delay of CD signal.
 * Supports parity check for address and data transmission.
 * Included in A23, A33, A80, A83T, H3(?) and A64 SoCs.

= Documentation = The RSB is briefly mentioned (along with MMIO address and IRQ number) in the A23, A33 and A64 manuals, but explained in more detail (including a register description) in the A80 and A83 manuals.

= Registers = This list was originally gained from Allwinner code, but was later extended with the help of the manuals.

Register list
The DLEN register seems to be hardwired to 0 in most recent implementations and is redundant with the CMD register. According to documentation it holds the transfer length (1, 2 or 4 Bytes) in the lower two bits and the read(=1)/write(=0) indicator in bit 4.

CCR
This register controls the RSB bus clock (SCK) speed.

The reference clock is the 24 MHz oscillator, a common speed on most boards seems to be 3 MHz, so 0x103 is the value you most probably want to write into this register.

INTE
This register masks/unmasks interrupt events.

STATUS
This register shows interrupt and transfer status. Write 1 to the corresponding bit to clear each interrupt.

LCR
This register can seemingly be used to bit bang the bus.

PMCR
Educated guess: This register can be used to switch a PMIC from its reset-state configured I2C interface to RSB mode. This avoids configuring the pins to I2C and sending the switch sequence via standard I2C.

CMD
List of command codes

SADDR
This register is used with the SRTA command to connect a hardware address to a runtime address.

= Hardware Addresses = RSB has hardware addresses and runtime addresses. Runtime addresses are configured at initialization time, and are used to talk to the slave devices. Hardware addresses are used to identify and configure runtime addresses. The configured runtime addresses are not queryable.

Allwinner sources use a static mapping of hardware and runtime addresses.

= Example transactions = For setting up the RSB controller in the first place, you have to:
 * Configure the associated pins to connect to the RSB controller (Port Controller CPUs)
 * Configure the pins to be Pull-up level 2 drive strength (same Port Controller CPUs)
 * Un-gate the RSB clock (bit 3 in the APB0_CLK_GATING_REG (offset 0x28) in the R_PRCM block)
 * De-assert the RSB reset line (bit 3 in the APB0_SOFT_RST_REG (offset 0xB0) in the R_PRCM block)
 * Program the clock (CCR register) in the RSB block (1 cycle delay, 3 MHz)
 * Soft reset the RSB block (bit 0 in CTRL register)

After having setup the RSB block, a typical read transaction may look like: writel(rt_addr << 16, RSB_BASE + 0x30); /* set run-time address of slave */ writel(0x8b, RSB_BASE + 0x2c);         /* "Read-one-byte" command into CMD register */ writel(regnr, RSB_BASE + 0x10);        /* set register to be read */ writel(0x80, RSB_BASE + 0x00);         /* start transaction */ while (readl(RSB_BASE + 0x00) & 0x80)  /* poll for completion */ ; ret = readl(RSB_BASE + 0x0c);          /* read status register */ if (ret == 0x01)                       /* transaction completed without errors */ return 0; return ret;