User:Ssvb/Primo73 DRAM Calibration

Default DRAM settings for MSI Primo73, which are used in the stock Android firmware
static struct dram_para dram_para = { .clock = 384, .type = 3, .rank_num = 1, .density = 4096, .io_width = 16, .bus_width = 32, .cas = 9, .zq = 0x7f, .odt_en = 0, .size = 1024, .tpr0 = 0x42d899b7, .tpr1 = 0xa090, .tpr2 = 0x22a00, .tpr3 = 0, .tpr4 = 0, .tpr5 = 0, .emr1 = 0x4, .emr2 = 0x10, .emr3 = 0, };

Trying low dcdc3 voltage and DRAM clocked up to 480MHz   dcdc3_vol        = 1200 dram_clk          = 480 mbus_clk          = 400 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x7b (0x5294a00) dram_odt_en       = 0 dram_tpr0         = 0x30927790 dram_tpr1         = 0xa0b0 dram_tpr2         = 0x23200 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x06060606 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=3] Total number of successful memtester runs: 657  Best luminance at the height 0.5 is above 0x081111, score = 0.923 Best luminance at the height 1.0 is above 0x081111, score = 0.888 Best luminance at the height 2.0 is above 0x081111, score = 0.842 Best luminance at the height 4.0 is above 0x001111, score = 0.788  Read errors per lane: [0, 2, 1, 0]. Lane 2 is the most noisy/problematic. Errors from the lane 1 are not intersecting with the errors from the worst lane 2. Write errors per lane: [0, 0, 0, 0]. Lane 3 is the most noisy/problematic.