VE Register guide

= Video Engine Registers =

Base address:
 * 0x01c0e000 - A10/A13/A20 sun8iw1p1/sun8iw3p1/sun8iw5p1
 * 0x03a40000 - sun9iw1p1
 * 0x01c0e000 - sun8iw6p1

General Registers MPEG Engine Registers H264 Engine Registers VC1 Engine Registers RMVB Engine Registers HEVC Engine Registers ISP Engine Registers AVC Encoder Engine Registers

MPEG Engine Registers
Base address: 0x01c0e100

Used by engine 0x0 (MPEG)

H264 Engine Registers
Base address: 0x01c0e200

Used by engine 0x1 (H264)

VC1 Engine Registers
Base address: 0x01c0e300

Used by engine 0x2 (VC1)

RMVB Engine Registers
Base address: 0x01c0e400

Used by engine 0x3 (RMVB)

HEVC Engine Registers
Base address: 0x01c0e500

Only on H3, used by engine 0x4 (HEVC)

ISP Engine Registers
Base address: 0x01c0ea00

Used by engine 0x8 (MPEG enc), 0xa (ISP) and 0xb (AVC enc)

AVC Encoder Engine Registers
Base address: 0x01c0eb00

Used by engine 0xb (AVC enc)

= VE General Registers =

MACC_VE_CTRL
Default value: 0x00000007

Offset: 0x0000

MACC_VE_RESET
Default value: 0x00000000

Offset: 0x0004

MACC_VE_CYCLES_COUNTER
Default value: 0x00000000

Offset: 0x0008

MACC_VE_TIMEOUT
Default value: 0x00000000

Offset: 0x000C

MACC_VE_STATUS
Default value: 0x00000000

Offset: 0x001c

MACC_VE_RDDATA_COUNTER
Default value: 0x00000000

Offset: 0x0020

MACC_VE_WRDATA_COUNTER
Default value: 0x00000000

Offset: 0x0024

MACC_VE_ANAGLYPH_CTRL
Default value: 0x00000000

Offset: 0x0028

MACC_VE_IPD_DBLK_BUF_CTRL
Default value: 0x00000000

Offset: 0x0050

MACC_VE_LUMA_HIST_THRi
Default value: see table

Offset: 0x0080 + (i * 4)

MACC_VE_LUMA_HIST_VALi
Default value: 0x00000000

Offset: 0x0090 + (i * 4)

MACC_VE_OUTPUT_CHROMA_OFFSET
Default value: 0x00000000

Offset: 0x00c4

at least since VE Version 1680

MACC_VE_OUTPUT_STRIDE
Default value: 0x00000000

Offset: 0x00c8

at least since VE Version 1680

MACC_VE_EXTRA_OUT_STRIDE
Default value: 0x00000000

Offset: 0x00cc

at least since VE Version 1680

MACC_VE_EXTRA_OUT_FMT_OFFSET
Default value: 0x00000000

Offset: 0x00e8

VE Version 1633 and newer

MACC_VE_OUTPUT_FORMAT
Default value: 0x00000000

Offset: 0x00ec

at least since VE Version 1680

MACC_VE_VERSION
Offset: 0x00f0

Known values:
 * 0x16230055 (A10/A20)
 * 0x16250055 (A13)
 * 0x16330040 (A31s)
 * 0x16390028 (A80)
 * 0x16670040 (A33)
 * 0x16800040 (H3)
 * 0x16890040 (A64)
 * 0x17180040 (H5)
 * 0x16810040 (S3)

= MPEG Engine Registers =

MACC_MPEG_PHDR
Mostly from Picture_Coding_Extension

Default value: 0x00000000

Offset: 0x0100

MACC_MPEG_VOPHDR
Default value: 0x00000000

Offset: 0x0104

MACC_MPEG_SIZE
Default value: 0x00000000

Offset: 0x0108

MACC_MPEG_FRAME_SIZE
Default value: 0x00000000

Offset: 0x010c

MACC_MPEG_MBA
Default value: 0x00000000

Offset: 0x0110

MPEG4:

MPEG2:

MACC_MPEG_CTRL
Default value: 0x00000000

Offset: 0x0114

MACC_MPEG_TRIG
Default value: 0x00000000

Offset: 0x0118

MACC_MPEG_STATUS
Default value: 0x0000c000

Offset: 0x011c

MACC_MPEG_FRAME_DIST
Default value: 0x00000000

Offset: 0x0120

MACC_MPEG_TRBTRDFLD
Default value: 0x00000000

Offset: 0x0124

MACC_MPEG_VLD_ADDR
Default value: 0x00000000

Offset: 0x0128

MACC_MPEG_VLD_OFFSET
Default value: 0x00000000

Offset: 0x012c

MACC_MPEG_VLD_LEN
Default value: 0x00000000

Offset: 0x0130

MACC_MPEG_VBV_END
Default value: 0x00000000

Offset: 0x0134

MACC_MPEG_MBH_ADDR
Default value: 0x00000000

Offset: 0x0138

MACC_MPEG_DCAC_ADDR
Default value: 0x00000000

Offset: 0x013c

MACC_MPEG_BLK_OFFSET
Default value: 0x00000000

Offset: 0x0140

MACC_MPEG_NCF_ADDR
Default value: 0x00000000

Offset: 0x0144

MACC_MPEG_REC_LUMA
Default value: 0x00000000

Offset: 0x0148

MACC_MPEG_REC_CHROMA
Default value: 0x00000000

Offset: 0x014c

MACC_MPEG_FWD_LUMA
Default value: 0x00000000

Offset: 0x0150

MACC_MPEG_FWD_CHROMA
Default value: 0x00000000

Offset: 0x0154

MACC_MPEG_BACK_LUMA
Default value: 0x00000000

Offset: 0x0158

MACC_MPEG_BACK_CHROMA
Default value: 0x00000000

Offset: 0x015c

MACC_MPEG_SOCX
Default value: 0x00000000

Offset: 0x0160

MACC_MPEG_SOCY
Default value: 0x00000000

Offset: 0x0164

MACC_MPEG_SOL
Default value: 0x00000000

Offset: 0x0168

MACC_MPEG_SDLX
Default value: 0x00000000

Offset: 0x016c

MACC_MPEG_SDLY
Default value: 0x00000000

Offset: 0x0170

MACC_MPEG_SPRITESHFT
Default value: 0x00000000

Offset: 0x0174

MACC_MPEG_SDCX
Default value: 0x00000000

Offset: 0x0178

MACC_MPEG_SDCY
Default value: 0x00000000

Offset: 0x017c

MACC_MPEG_IQ_MIN_INPUT
Default value: 0x00000000

Offset: 0x0180

MACC_MPEG_IQ_INPUT
Default value: 0x00000000

Offset: 0x0184

MACC_MPEG_MSMPEG4_HDR
Default value: 0x00000000

Offset: 0x0188

MACC_MPEG_VP6_HDR
Default value: 0x00000000

Offset: 0x018c

MACC_MPEG_IQ_IDCT_INPUT
Default value: 0x00000000

Offset: 0x0190

MACC_MPEG_MB_HEIGHT
Default value: 0x00000000

Offset: 0x0194

MACC_MPEG_MB_V1
Default value: 0x00000000

Offset: 0x0198

MACC_MPEG_MB_V2
Default value: 0x00000000

Offset: 0x019c

MACC_MPEG_MB_V3
Default value: 0x00000000

Offset: 0x01a0

MACC_MPEG_MB_V4
Default value: 0x00000000

Offset: 0x01a4

MACC_MPEG_MB_V5
Default value: 0x00000000

Offset: 0x01a8

MACC_MPEG_MB_V6
Default value: 0x00000000

Offset: 0x01ac

MACC_MPEG_MB_V7
Default value: 0x00000000

Offset: 0x01b0

MACC_MPEG_MB_V8
Default value: 0x00000000

Offset: 0x01b4

MACC_MPEG_JPEG_SIZE
Default value: 0x00000000

Offset: 0x01b8

MACC_MPEG_JPEG_MCU
Default value: 0x00000000

Offset: 0x01bc

MACC_MPEG_JPEG_RES_INT
Default value: 0x00000000

Offset: 0x01c0

MACC_MPEG_ERROR
Default value: 0x00000000

Offset: 0x01c4

MACC_MPEG_CTR_MB
Default value: 0x00000000

Offset: 0x01c8

MACC_MPEG_ROT_LUMA
Default value: 0x00000000

Offset: 0x01cc

MACC_MPEG_ROT_CHROMA
Default value: 0x00000000

Offset: 0x01d0

MACC_MPEG_ROTSCALE_CTRL
Used for control Rotate/Scale buffer

Default value: 0x00000000

Offset: 0x01d4

MACC_MPEG_JPEG_MCU_START
Default value: 0x00000000

Offset: 0x01d8

MACC_MPEG_JPEG_MCU_END
Default value: 0x00000000

Offset: 0x01dc

MACC_MPEG_SRAM_RW_OFFSET
Default value: 0x00000000

Offset: 0x01e0

MACC_MPEG_SRAM_RW_DATA
Default value: 0x00000000

Offset: 0x01e4

Map for Jpeg decoding process:

Cedar Huffman Tables are 2KiB of data written through this register. First half contains description of Huffman-tree, second half contains the data.

+--+--+--+--+ - - - -- - - - -- - - - -+ | LumaDC  |  LumaAC  | ChromaDC | ChromaAC | Filled with zero (maybe more trees are possible) | | 64 bytes | 64 bytes | 64 bytes | 64 bytes |                   768 bytes                     | +--+--+--+--+ - - - -+ - - - -+ - - - -+ |               Luma DC Data               |  Luma AC Data  | Chroma DC Data | Chroma AC Data | |                 256 bytes                |   256 bytes    |   256 bytes    |   256 bytes    | +---+ - - - -+ - - - -+ - - - -+

Each of the 64 byte tree-description has the following format: First 16 halfwords: first bitstream used for datacodes in corresponding depth (or 0xffff if no more data) Next 16 bytes: offset in data section for corresponding depth Rest (16 bytes): Filled with zero

The 256 byte data sections contain the codes in same format as in JPEG.

MACC_MPEG_START_CODE_BITOFFSET
Default value: UNDEF

Offset: 0x01f0

= H264 Engine Registers =

MACC_H264_SEQ_HDR
Default value: 0x00000000

Offset: 0x0200

MACC_H264_PIC_HDR
Default value: 0x00000000

Offset: 0x0204

MACC_H264_SLICE_HDR
Default value: 0x00000000

Offset: 0x0208

MACC_H264_SLICE_HDR2
Default value: 0x00000000

Offset: 0x020c

MACC_H264_PRED_WEIGHT
Default value:

Offset: 0x0210

MACC_H264_VP8_HDR
Default value:

Offset: 0x0214

MACC_H264_QINDEX
Default value:

Offset: 0x0218

MACC_H264_QP
Default value: 0x00000000

Offset: 0x021c

MACC_H264_CTRL
Default value:

Offset: 0x0220

MACC_H264_TRIG
Default value:

Offset: 0x0224

MACC_H264_STATUS
Default value:

Offset: 0x0228

MACC_H264_CUR_MBNUM
Default value:

Offset: 0x022c

MACC_H264_VLD_ADDR
Default value:

Offset: 0x0230

MACC_H264_VLD_OFFSET
Default value:

Offset: 0x0234

MACC_H264_VLD_LEN
Default value:

Offset: 0x0238

MACC_H264_VLD_END
Default value:

Offset: 0x023c

MACC_H264_SDROT_CTRL
Default value:

Offset: 0x0240

MACC_H264_OUTPUT_FRAME_INDEX
Default value:

Offset: 0x024c

MACC_H264_VP8_ENTROPY_PROBS
Default value:

Offset: 0x024c

Size of entropy probabilities table is defined as 0x2400, but only first 0x11b0 bytes are used. The table contents buffer is null'ed after allocation and reused for every decoded frame. Memory layout of entropy probabilities table: 0x000 - 0x7ff : coef_probs (BLOCK_TYPES are 512 bytes aligned,                               COEF_BANDS are 64 bytes aligned,                               PREV_COEF_CONTEXTS are 16 bytes aligned) 0x800 - 0xfff : vp8_coef_update_probs (BLOCK_TYPES are 512 bytes aligned,                                          COEF_BANDS are 64 bytes aligned,                                          PREV_COEF_CONTEXTS are 16 bytes aligned) 0x1000 - 0x1003: vp8_kf_ymode_prob 0x1008 - 0x100b: ymode_prob 0x1010 - 0x1012: uv_mode_prob or vp8_kf_uv_mode_prob depending on frame type 0x1018 - 0x101a: mb_segment_tree_probs 0x101c        : prob_skip_false 0x101d        : prob_intra 0x101e        : prob_last 0x101f        : prob_gf 0x1020 - 0x1032: mvc[0].prob 0x1040 - 0x1052: mvc[1].prob 0x1060 - 0x1062: vp8_mbsplit_probs 0x1068 - 0x1070: vp8_bmode_prob 0x1088 - 0x109b: vp8_sub_mv_ref_prob2 (4 bytes aligned) 0x10a8 - 0x10bf: vp8_mode_contexts (4 bytes aligned) 0x1100 - 0x1107: vp8_kf_ymode_tree 0x1108 - 0x110f: vp8_ymode_tree 0x1110 - 0x1115: vp8_uv_mode_tree 0x1122 - 0x112f: vp8_small_mvtree 0x1142 - 0x114f: vp8_small_mvtree (again) 0x1160 - 0x1165: vp8_mbsplit_tree 0x1168 - 0x1179: vp8_bmode_tree 0x1188 - 0x118d: vp8_sub_mv_ref_tree 0x11a8 - 0x11af: vp8_mv_ref_tree

All trees should be in signed magnitude representation, e.g.  table[0x1168] = (vp8_bmode_tree[0] <= 0)?(128-vp8_bmode_tree[0]):vp8_bmode_tree[0];

MACC_H264_VP8_FSTDATA_PARTLEN
Default value:

Offset: 0x0254

MACC_H264_PIC_MBSIZE
Default value:

Offset: 0x0258

For VP8: MAC_H264_HORIZONTAL_MACROBLOCK_COUNT = (frame_width + 15)/16 MAC_H264_VERTICAL_MACROBLOCK_COUNT = (frame_height + 15)/16

MACC_H264_PIC_BOUNDARYSIZE
Default value:

Offset: 0x025c

MACC_H264_MB_ADDR
Default value:

Offset: 0x0260

MACC_H264_REC_LUMA
Default value:

Offset: 0x02ac

MACC_H264_FWD_LUMA
Default value:

Offset: 0x02b0

MACC_H264_BACK_LUMA
Default value:

Offset: 0x02b4

MACC_H264_ERROR
Default value:

Offset: 0x02b8

MACC_H264_REC_CHROMA
Default value:

Offset: 0x02d0

MACC_H264_FWD_CHROMA
Default value:

Offset: 0x02d4

MACC_H264_BACK_CHROMA
Default value:

Offset: 0x02d8

MACC_H264_BASIC_BITS_DATA
Default value:

Offset: 0x02dc

MACC_H264_RAM_WRITE_PTR
Default value:

Offset: 0x02e0

MACC_H264_RAM_WRITE_DATA
Default value:

Offset: 0x2e4

Memory layout for h.264 decoding: 0x000 - 0x2ff: Prediction weight table 0x400 - 0x63f: Framebuffer list 0x640 - ? : Reference Picture list 0 0x664 - ? : Reference Picture list 1 0x800 - 0x8df: Scaling lists

Prediction weight table: uint32_t luma_l0[32]; uint32_t chroma_l0[32][2]; uint32_t luma_l1[32]; uint32_t chroma_l1[32][2]; each has bit 24:16 = signed offset bit 8:0 = signed weight

Framebuffer list: struct { uint32_t top_pic_order_cnt; uint32_t bottom_pic_order_cnt; uint32_t flags; // bit 0-1: top ref type: 0x0 = short, 0x1 = long, 0x2 = no ref // bit 4-5: bottom ref type: 0x0 = short, 0x1 = long, 0x2 = no ref // bit 8-9: picture type: 0x0 = frame, 0x1 = field, 0x2 = mbaff uint32_t luma_addr; uint32_t chroma_addr; uint32_t extra_buffer_top_addr;   // prediction buffers? uint32_t extra_buffer_bottom_addr; // size = pic_width_in_mbs * pic_height_in_mbs * 32 uint32_t unknown; // = 0x0 } framebuffer_list[18];

Reference Picture lists: uint8_t ref_picture[?]; // (index to framebuffer list) * 2 + (bottom_field ? 1 : 0)

Scaling lists: uint8_t ScalingList8x8[2][64]; uint8_t ScalingList4x4[6][16];

MACC_H264_ALT_LUMA
Default value:

Offset: 0x02e8

MACC_H264_ALT_CHROMA
Default value:

Offset: 0x02ec

MACC_H264_SEG_MB_LV0
Default value:

Offset: 0x02f0

MACC_H264_SEG_MB_LV1
Default value:

Offset: 0x02f4

MACC_H264_REF_LF_DELTA
Default value:

Offset: 0x02f8

MACC_H264_MODE_LF_DELTA
Default value:

Offset: 0x02fc

= HEVC Engine Register =

MACC_HEVC_TILE_LIST_ADDR
Points to a list of entry point offsets and tile start/end CTBs

struct { uint32_t entry_point_offset; uint32_t zero; uint16_t tile_start_ctb_x; uint16_t tile_start_ctb_y; uint16_t tile_end_ctb_x; uint16_t tile_end_ctb_y; } tile_list[num_entry_point_offsets];

MACC_HEVC_SRAM_DATA
Memory layout for H.265 decoding: 0x000 - 0x01f Prediction Weight Luma List 0 0x020 - 0x05f Prediction Weight Chroma List 0 0x060 - 0x07f Prediction Weight Luma List 1 0x080 - 0x0bf Prediction Weight Chroma List 1 0x400 - 0x7ff Picture List 0x800 - 0xbdf Scaling Lists 0xc00 - 0xc0f Reference Picture List 0 0xc10 - 0xc1f Reference Picture List 1

Prediction Weight Luma Lists: struct { int8_t delta_luma_weight; int8_t luma_offset; } pred_weight_luma[16];

Prediction Weight Chroma Lists: struct { int8_t delta_chroma_weight_cb; int8_t ChromaOffset_cb; int8_t delta_chroma_weight_cr; int8_t ChromaOffset_cr; } pred_weight_chroma[16];

Picture List: struct { uint32_t pic_order_cnt; uint32_t pic_order_cnt; uint32_t extra_buffer_addr; uint32_t extra_buffer_addr; uint32_t luma_addr; uint32_t chroma_addr; uint32_t reserved; uint32_t reserved; } picture_list[32];

Scaling Lists (in horizontal scan order): struct { uint8_t ScalingList8x8[6][64]; uint8_t ScalingList32x32[2][64]; uint8_t ScalingList16x16[6][64]; uint8_t ScalingList4x4[6][16]; } scaling_lists;

Reference Picture Lists: uint8_t ref_picture[16]; // index to picture list (set bit7 for longterm reference)

= ISP Engine Registers =

MACC_ISP_SRAM_DATA
When scaler is enabled (MACC_ISP_CTRL_SCALER_EN), and MACC_ISP_SRAM_INDEX set to 0x400 the next 64 values written into MACC_ISP_SRAM_DATA are treated as coefficients for a polyphase filter in the following mode.

|0                            31|32                           64|            -| |            table A             |           table B             | -| All coefficients are signed 16 bit values. 0x0100 = 1.0 0x0080 = 0.5 0x0000 = 0.0 0xffff = -1/0x100 0xff00 = -1.0 (?)

Horizontal direction. Table A => 4-tap, 16-phase polyphase filter coefficients (h0, h1, h2, h3) | data written offset |31 16|15   0| -- 2*i+0  |  h1  |  h0  | 2*i+1 |  h3  |  h2  | --

Vertical direction. Table B => 2-tap, 32-phase polyphase filter coefficients (h0, h1) | data written offset |31 16|15   0| ---   i    |  h1  |  h0  |

= AVC Engine Register =

MACC_AVC_SRAM_DATA
For mpeg/mjpeg, MACC_AVC_SDRAM_INDEX is the start index to write the quantization matrix elements into MACC_AVC_SRAM_DATA. If index is 64, then the first 64 elements are for chroma component, and the next 64 wrap around to become luma.

0                                 63|64                                 127 |     luma quantization matrix       |      chroma quantization matrix     |  index by natural order MACC_AVC_SRAM_DATA[23:16] = (Q / 2) + 0.5 MACC_AVC_SRAM_DATA[15:0] = (0xffff / Q) When compared with libjpeg, there are still rounding errors in the coefficients value, around 1 unit of difference.

(Quantized coefficients) = round(C / Q)                         = floor((C + 0.5Q) / Q)

= References =