Timestamp Counter

Allwinner SoCs contain a timestamp counter that backs the ARM architectural timer. It provides two MMIO separate regions, one for control and one for status, so the control registers can be protected as secure-only.

Note that this hardware block appears to be unrelated to the TSGEN hardware, which looks to be part of the CoreSight debug system.

Status Register Layout
This block is called TIMESTAMP_STA or CNT_R in the memory map.

Control Register Layout
This block is called TIMESTAMP_CTRL or CNT_C in the memory map.

CNT_FREQID_REG is also called Cluster0CtrlReg1 in the BSP.

Register Descriptions
See the A83T user manual.