Xunlong Orange Pi PC

Orange Pi PC is H3 based development board produced by Xunlong.

= Identification = The PC PCB has the following silkscreened on it: Orange Pi PC V1.2

Since 2016 (maybe earlier?), an updated version with a bit thinner memory chips (see the spec sheets for differences between the memory types) is available with the following silkscreened on it: Orange Pi PC V1.3

The PC Plus PCB shows the following: Orange Pi PC Plus V1.1

= Expansion Port =

The Orange Pi PC has a Raspberry Pi model B+ compatible 40-pin, 0.1" connector with several low-speed interfaces.

= Tips, Tricks, Caveats =


 * Heat issues when using common OS images for the OPi PC. Without a heatsink the Orange Pi PC overheats easily and will drop cores to thwart further temperature increase and unfortunately the heatsink provided by the manufacturer does little to help. The low cost $15 variant does not have any heatsink included at all. This is the result of 'factory settings' overclocking/overvolting the H3 way too much. With adjusted dvfs entries and an upper limit of 1.2 GHz SoC temperature stays below 75°C without heatsink when running cpuburn-a7 on all 4 cores. Using a quality heatsink, some airflow and reasonable cpufreq settings the H3 remains below 60°C even under full load at an ambient temperature of 22°C.


 * It is also possible to power the device via GPIO pin header: connect +5V to either pin 2 or 4 (both are connected to DCIN test point) and GND to pin 6.

FEL mode
There is no dedicated FEL button. The Orange Pi PC will fail over to FEL mode if it doesn't detect a card present in the µSD slot. On the PC Plus it gets somewhat tricky to use FEL mode in case the eMMC is already populated with an OS (or at least a working boot loader). In this case it helps to grab the fel-sdboot.sunxi image from sunxi-tools github repo and write it to an SD card of any size as follows: sudo dd if=fel-sdboot.sunxi of=/dev/sdX bs=1024 seek=8 Then boot afterwards with this SD card inserted and H3 will be in FEL mode afterwards.

An alternative way is to power the board from Pin2 (5V GPIO)whilst connected to RX/TX with a USB Serial TTL Spam '2' over the serial console. This will place the board into FEL mode - no SD-Card image required. Tested and works on Pi PC Plus.

Not tested yet You can use "FAKE FEL BUTTON". See photo "H3_FAKE_BUTTON". According to the board's schematic UBOOT pin is connected to R124 (bottom leed, because top leed is connected to R38 which is connected to VCC). You can connect it to GND. The right R108 leed is the nearest GND pin (I've checked it). It is very close so it is not too hard. I draw it as yellow line. Enjoy!

LEDs


The board has two LEDs:
 * A red LED, connected to the PA15 pin.
 * A green LED, connected to the PL10 pin.

When using kernel 3.4 with Xunlong's or loboris' settings then the LEDs can only be switched on/off. By changing the definition in the fex file (see patch or fex with applied fix) both LEDs can be used the usual way (using different triggers and so on)

CPU clock speed limit
The Allwinner H3 manual does not provide the CPU clock speed information. But the following is a common comment in the FEX files from various H3 SDK variants: It means that this comment likely originates from Allwinner, rather than something added by Xunlong or any other H3 device manufacturer.
 * dvfs voltage-frequency table configuration
 * pmuic_type:0:none, 1:gpio, 2:i2c
 * pmu_gpio0: gpio config.
 * pmu_levelx: 0~9999: voltage(mV), 10000~90000:gpio0 state. voltage form high to low.
 * extremity_freq(Hz): cpu extremity frequency when run benckmark or demo apk
 * 1536MHz@1500mV with radiator, 1296MHz@1340mV without radiator
 * max_freq: cpu maximum frequency, based on Hz, can not be more than 1200MHz
 * min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz
 * LV_count: count of LV_freq/LV_volt, must be < 16
 * LV1: core vdd is 1.50v if cpu frequency is (1296Mhz, 1536Mhz]
 * LV2: core vdd is 1.34v if cpu frequency is (1200Mhz, 1296Mhz]
 * LV3: core vdd is 1.32v if cpu frequency is (1008Mhz, 1200Mhz]
 * LV4: core vdd is 1.20v if cpu frequency is (816Mhz,  1008Mhz]
 * LV5: core vdd is 1.10v if cpu frequency is (648Mhz,   816Mhz]
 * LV6: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV7: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV8: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV5: core vdd is 1.10v if cpu frequency is (648Mhz,   816Mhz]
 * LV6: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV7: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV8: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]

The Orange Pi PC board uses the SY8106A voltage regulator for providing the CPU core voltage (VDD_CPUX). The default CPU voltage is 1.2V after power-on (selected by the resistors on the PCB) and can be changed at runtime by software via I2C interface. According to the table above, this default voltage should be safe for using with the CPU clock frequencies up to 1008MHz. The H3 datasheet specifies 1.5V as the absolute maximum for the VDD_CPUX voltage and 1.4V as the recommended maximum.

DRAM clock speed limit
DRAM is clocked at 672 MHz by the hardware vendor. But the reliability still needs to be verified. One of the ways of doing reliability tests may be https://github.com/ssvb/lima-memtester/releases/tag/20151207-orange-pi-pc-fel-test (it checks the Orange Pi PC DRAM setup in the current mainline U-Boot v2016.01-rc2 + a bugfix).

'''We need still more test results in the table above in order to have more accurate statistics and finally pick a safe default DRAM clock speed for U-Boot. Preferably there should be at least 10 entries in the table (more is always better). And there are no "good" or "bad" test results. Even if your result looks very similar to the already reported results from the other people, please still add yours to the table! Because if people don't feel like reporting their "boring" results, then "interesting" outliers will unfortunately skew the statistics. Thanks!'''

DRAM clock speed limit (automated statistical analysis)
Below is an intermediate analysis of the currently reported results, using the lima-memtester-genchart script (run the script using this page URL as the command line argument). Assuming that the Gaussian distribution is a good approximation, try to predict what percentage of boards is expected to pass the lima-memetser test at different DRAM clock frequencies. The lima-memtester page provides more information.

Updating the analysis report: wget https://raw.githubusercontent.com/ssvb/lima-memtester/master/lima-memtester-genchart ruby lima-memtester-genchart https://linux-sunxi.org/Xunlong_Orange_Pi_PC
 * 1) copy/paste the script output into the linux-sunxi wiki

OpenRISC core
Also named as AR100, CPUS and "arisc" in various Allwinner materials, which may cause a bit of confusion. According to the Orange Pi PC schematics, VDD_CPUS is connected to VDD_RTC. It means that the voltage powering the OpenRISC core is programmable via the hardware register VDD_RTC_REG (at 0x1F00190) and can be configured between 0.7V and 1.4V. The H3 datasheet says that 1.4V is the absolute maximum for VDD_CPUS and 1.1V-1.3V is the recommended range. The reset default for VDD_RTC voltage is 1.1V.

Below is a quick evaluation of the potential clock speed limit of the OpenRISC core on just a single board (ssvb's) by running a naive recursive fibonacci function:

Without I-Cache, fetching each instruction from SRAM takes 3 cycles instead of just 1.

Please note that the intended use of the OpenRISC core in Allwinner devices is keeping a watch while the main Cortex-A7 CPU and the rest of the SoC peripherals are powered off in deep power save modes. In this usage scenario it is likely clocked at just the minimum possible clock frequency 32 KHz.

USB
It should be noted that unlike some of the more expensive Orange Pi models the 'PC' does not use an internal USB hub therefore the 4 available USB ports don't have to share bandwidth. First tests with kernel 4.4.0-rc4, a fast SSD and an enclosure capable of USB Attached SCSI show excellent sequential performance with mainline kernel: 39 MB/s write and 41.5 MB/s read (tests done with iozone using 4 GB test size and averaging the values of 4K/1M record size)

Camera module
Xunlong sells also a cheap 2MP camera (an attempt to fix the driver's limited resolutions can be found here). Unlike Orange Pi Plus/2 that can directly connect to the camera module for the PC an 'expansion board' is needed (see gallery below). If you order from Xunlong simply say that you need the camera for Orange Pi PC and they ship camera together with the small board.

1-Wire support
After applying a to the lichee kernel sources 1-wire can be used with H3 based Orange Pi's. After loading the approriate modules (w1-sunxi, w1-gpio and w1-therm) connected 1-wire slave devices should appear below /sys/bus/w1/devices/. To let 1-wire work the GPIO pin to be used has to be defined in fex/script.bin. All OS images that applied the 1-wire patch (all from loboris after applying his latest fixes, Armbian or the community's OpenELEC build) use "gpio = 20" in the fex file. Attention: This is a logical mapping that correlates with physical GPIO pin 37 (see the gallery image below). Please keep this in mind when following 1-wire tutorials for Raspberry Pi where GPIO pin 7 is normally used. On H3 devices the pin to connect the data line to is on the other end of the GPIO header.

CVBS pinout
According to schematics v1.2 plug config is: (tip) Right-Left-Video-Gnd (cable).

= Adding a serial port  =

Locating the UART
The UART pins are located between HDMI and power jack of the board. On some boards they are marked as TX, RX and GND on the PCB (simplified layout: ..DC-IN.. [GND][RX][TX] ..HDMI..). Just attach some leads according to our UART Howto.

= Pictures =

Orange Pi PC Plus
= Variants =


 * The Orange Pi PC Plus adds 8GB eMMC and Realtek RTL8189FTV SDIO-based WiFi directly on the board (as opposed to a soldered-on module). The physical dimensions and position of connectors are exactly the same as the Orange Pi PC. The same type of DRAM is used but tracing is different since one DRAM module moved to the bottom side of the PCB. Since a FEL button is missing on this board it's not that easy to verify DRAM reliability the usual way (through FEL boot) so we should stay with the failsafe value of 624 MHz DRAM clock. Regarding software support we can base on fex file and device tree for the PC and simply add the necessary WiFi chip mappings.

= Also known as =

= See also =


 * Xunlong Orange Pi site
 * Official Github Repository.
 * Official Orange Pi Forums.
 * H3_Manual_build_howto
 * Orange Pi PC Schematics 1.2
 * Schematics and other docs from manufacturer

Manufacturer images

 * A various amount of prebuilt images is provided via OrangePi's Website most of them not containing latest fixes.
 * Many people are also running images generated by forum user loboris (mirror available). It should be noted that when using loboris' images it's always useful to execute his update_kernel.sh to get latest kernel fixes and settings for the board in question (various script.bin variants for different Orange Pis and display settings). To adjust script.bin settings (overclocked/overvolted) to linux-sunxi defaults there's informations and a script available in this thread.

= References =