DRAM Controller/Quirks

This is a list of some strange things and unresolved mysteries.

Suspicious GPS manipulations
The current code in upstream u-boot: http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram.c;h=b43c4b41d3c53dc339b3f4f4229daa9fca7f9764;hb=3fe1a8545b55d31a6db2d9e60d962c4f6e048913#l218

The first commit introducing this code in the u-boot-sunxi says "if we don't reset the gps module, it will access sdram but sdram is not ready, and the system will die...".

The corresponding reference in the Allwinner boot0 bootloader is yet to be found.

SDR_SCSR register ('csel' in the sunxi_dram_reg struct) on Allwinner A10
The current code in upstream u-boot: not available yet.

The code in Allwinner boot1 bootloader: https://github.com/hno/allwinner-boot/blob/6fd439377f0f0f0305d61fe6b87c9e77666facb3/boot1/core/standby/dram_standby.c#L326

Unless a magic value 0x16237495 is written to this register on Allwinner A10, the DRAM controller fails to operate properly. This register always reads back as 0.

"super-standby"
The current code in upstream u-boot: http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/dram.c;h=b43c4b41d3c53dc339b3f4f4229daa9fca7f9764;hb=3fe1a8545b55d31a6db2d9e60d962c4f6e048913#l535

Is it a DDR3 Self-Refresh mode support for the sake of power saving (with everything else mostly powered off)?

Some messy commits in the Allwinner bootloader:
 * https://github.com/hno/allwinner-boot/commit/8bcc7de0e4cb166ad1e8db0debbadcfbfcdba079
 * https://github.com/hno/allwinner-boot/commit/a1baea05c83151b143bad629ac854cfa332c0635
 * https://github.com/hno/allwinner-boot/commit/386c71cd8fd57c7a860678a6c644f8d62ebf1db8