AXP152

The AXP152 is the PMIC (Power Management IC) developed by X-Powers, a sister company of Allwinner.

Overview
AXP152 is a highly integrated power management IC that provides easy and flexible power solution for applications that require multi-rail outputs. It has fully met the increasingly complex needs of application processors on accurate power control.

AXP152 integrates an adaptive and USB-compatible PWM charger, four step-down converters (Buck DC-DC converter), seven low dropout regulators. It also Featuress protection circuitry such as over/under-voltage protection (OVP/UVP), over-temperature protection, and over-current protection (OCP) to guarantee the power system security and stability.

In addition, AXP152 includes a Two Wire Serial Interface (TWSI), through which the application processor is capable of enabling/disabling some power outputs, programming the voltage to decrease the power consumption, and provides customers with unprecedented experience of power management.

AXP152 is available in an 5mm x 5mm 40-pin QFN package.

Features

 * 4*Buck DC-DC Converters
 * DC-DC1：PFM/PWM mode,scaling in 1.7-3.5V,50mV/step，Output current 1A
 * DC-DC2：PFM/PWM mode,scaling in 0.7-2.275V,25mV/step,Output current 2A, DVM
 * DC-DC3：PFM/PWM mode,scaling in 1.7-3.5V,50mV/step,Output current 1.2A
 * DC-DC4：PFM/PWM mode,scaling in 1.7-3.5V,25mV/step,Output current 1.2A


 * System Management
 * Support software shutdown or hardware power off
 * External wakeup source
 * Output monitor
 * PWROK signal for reset or power off
 * OVP/UVP
 * Programable power on voltage or sequence


 * 7 LDOs
 * LDO0：Output current 1.5A,Internal 500/900/1500mA current limited option
 * RTCLDO：On for RTC31,Output 3.1V, One for RTC13,Output 1.3/1.8V
 * ALDO1：Analog LDO,scaling in 1.2-3.3V, 300mA
 * ALDO2：Analog LDO,scaling in 1.2-3.3V, 300mA
 * DLDO1：Digtal LDO or Switch,scaling in 0.7-3.5V,100mV/step,300mA
 * DLDO2：Digtal LDO or Switch,scaling in 0.7-3.5V,100mV/step,300mA
 * GPIOLDO：Low noise LDO, scaling in 0.7-3.5V,100mV/step,30mA


 * Host Interface
 * Programable Interrupt and wakeup management
 * Multi-function Pins
 * Internal Timer

Regulators
This section corresponds to section 9.2 in the datasheet.

The AXP152 features 4 DC-DC step-down (buck) converters, and 7 linear regulators. The DC-DC converters operate in automatic (PFM + PWM) or PWM mode, controllable via reg 80h, at a default frequency of 2.25 MHz. The frequency is controlled via reg 37h. It also supports spread spectrum.

Interrupts
This section corresponds to section 9.6 in the datasheet.

The AXP221 pulls the IRQ pin low to signal an interrupt to the host, and stores the interrupt status in the interrupt status registers (48h ~ 4Ch). Writing 1 to the corresponding bit clears the interrupt. When there are no interrupts, the IRQ pin is pulled up (by an external 51KΩ resistor). Each interrupt can be masked via the interrupt control registers (40h ~ 44h).

REG 01H: Power operating mode and charge status indication

 * {| class="wikitable"

! Bit !! Description !! R/W 0: LDO0IN not present (< 3.5V); 1: LDO0IN present (> 3.8V)
 * 7-6 || Reserved || R
 * 5 || LDO0IN status when LDO0EN pin is high
 * 5 || LDO0IN status when LDO0EN pin is high
 * 5 || LDO0IN status when LDO0EN pin is high
 * R
 * 4 || TWI interface enabled (SIEN pin) || R
 * 3 || IRQ pin triggered power on || R
 * 2 || PWRON button triggered power on || R
 * 1 || Reserved || R
 * 0 || ALDOIN rising edge triggered power on || R
 * }
 * 1 || Reserved || R
 * 0 || ALDOIN rising edge triggered power on || R
 * }
 * 0 || ALDOIN rising edge triggered power on || R
 * }
 * }

REG 12H: Power output control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value
 * 7 || DC-DC1 on/off || RW || OTP
 * 6 || DC-DC2 on/off || RW || OTP
 * 5 || DC-DC3 on/off || RW || OTP
 * 4 || DC-DC4 on/off || RW || OTP
 * 3 || ALDO1 on/off || RW || OTP
 * 2 || ALDO2 on/off || RW || OTP
 * 1 || DLDO1 on/off || RW || OTP
 * 0 || DLDO2 on/off || RW || OTP
 * }
 * 3 || ALDO1 on/off || RW || OTP
 * 2 || ALDO2 on/off || RW || OTP
 * 1 || DLDO1 on/off || RW || OTP
 * 0 || DLDO2 on/off || RW || OTP
 * }
 * 0 || DLDO2 on/off || RW || OTP
 * }
 * }

REG 13H: ALDO1/2 operation mode control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: low noise; 1: low power 0: low noise; 1: low power
 * 7-4 || none
 * 3 || ALDO1 operation mode
 * 3 || ALDO1 operation mode
 * 3 || ALDO1 operation mode
 * RW || 0
 * 2 || ALDO2 operation mode
 * 2 || ALDO2 operation mode
 * RW || 0
 * 1-0 || Reserved || RW || 00
 * }
 * }

REG 15H: LDO0 control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value no effect if LDO0EN is connected to LDO0IN 00: 5V  ; 01: 3.3V 10: 2.8V ; 11: 2.5V 00: no limit 01: 1500mA 10: 900mA 11: 500mA
 * 7 || LDO0 on/off
 * 7 || LDO0 on/off
 * RW || 0
 * 6 || Reserved || RW || 0
 * 5-4 || LDO0 voltage
 * 5-4 || LDO0 voltage
 * 5-4 || LDO0 voltage
 * RW || 00
 * 3-2 || Reserved || RW || 00
 * 1-0 || LDO0 current limit
 * 1-0 || LDO0 current limit
 * 1-0 || LDO0 current limit
 * RW || 00
 * }

Reg 23h: DC-DC2 output voltage

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value
 * 7-6 || Reserved ||
 * 5-0 || 0.7 - 2.275 V, 25 mV/step || RW || OTP
 * }
 * 5-0 || 0.7 - 2.275 V, 25 mV/step || RW || OTP
 * }

Reg 25h: DC-DC 2 Voltage Ramp Control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: 25mV/15.625μs = 1.6mV/μs 1: 25mV/31.250μs = 0.8mV/μs
 * 7-4 || None
 * 3 || Reserved || RW || 0
 * 2 || DC-DC2 VRC enable || RW || 0
 * 1 || Reserved || RW || 0
 * 0 || DC-DC2 voltage ramp rate
 * 2 || DC-DC2 VRC enable || RW || 0
 * 1 || Reserved || RW || 0
 * 0 || DC-DC2 voltage ramp rate
 * 0 || DC-DC2 voltage ramp rate
 * 0 || DC-DC2 voltage ramp rate
 * RW || 0
 * }

Reg 26h: DC-DC1 output voltage

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0000: 1.7V 0001: 1.8V  0010: 1.9V  0011: 2.0V 0100: 2.1V 0101: 2.4V  0110: 2.5V  0111: 2.6V 1000: 2.7V 1001: 2.8V  1010: 3.0V  1011: 3.1V 1100: 3.2V 1101: 3.3V  1110: 3.4V  1111: 3.5V
 * 7-4 || None
 * 3-0 ||
 * 3-0 ||
 * 3-0 ||
 * RW || OTP
 * }

Reg 27h: DC-DC3 output voltage

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value
 * 7-6 || Reserved || RW || 00
 * 5-0 || 0.7 - 3.5 V, 50 mV/step || RW || OTP & DC3SET pin
 * }
 * 5-0 || 0.7 - 3.5 V, 50 mV/step || RW || OTP & DC3SET pin
 * }

Reg 28h: ALDO1/2 output voltage

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0000: 1.2V 0001: 1.3V  0010: 1.4V  0011: 1.5V 0100: 1.6V 0101: 1.7V  0110: 1.8V  0111: 1.9V 1000: 2.0V 1001: 2.5V  1010: 2.7V  1011: 2.8V 1100: 3.0V 1101: 3.1V  1110: 3.2V  1111: 3.3V 0000: 1.2V 0001: 1.3V  0010: 1.4V  0011: 1.5V 0100: 1.6V 0101: 1.7V  0110: 1.8V  0111: 1.9V 1000: 2.0V 1001: 2.5V  1010: 2.7V  1011: 2.8V 1100: 3.0V 1101: 3.1V  1110: 3.2V  1111: 3.3V
 * 7-4 || ALDO1 output voltage
 * 7-4 || ALDO1 output voltage
 * RW || OTP
 * 3-0 || ALDO2 output voltage
 * 3-0 || ALDO2 output voltage
 * RW || OTP
 * }

Reg 29h: DLDO1 voltage control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: LDO mode, voltage controlled by bits [4:0] 1: Switch mode, voltage close to DLDOIN
 * 7 || DLDO1 mode
 * 7 || DLDO1 mode
 * RW || 0
 * 6-5 || Reserved || RW || 00
 * 4-0 || 0.7 - 3.3 V, 100 mV/step || RW || OTP
 * }
 * 4-0 || 0.7 - 3.3 V, 100 mV/step || RW || OTP
 * }

Reg 2Ah: DLDO2 voltage control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: LDO mode, voltage controlled by bits [4:0] 1: Switch mode, voltage close to DLDOIN
 * 7 || DLDO2 mode
 * 7 || DLDO2 mode
 * RW || 0
 * 6-5 || Reserved || RW || 00
 * 4-0 || 0.7 - 3.3 V, 100 mV/step || RW || OTP
 * }
 * 4-0 || 0.7 - 3.3 V, 100 mV/step || RW || OTP
 * }

Reg 2Bh: DC-DC4 output voltage

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value
 * 7 || Reserved || RW || 0
 * 6-0 || 0.7 - 3.5 V, 25 mV/step || RW || OTP
 * }
 * 6-0 || 0.7 - 3.5 V, 25 mV/step || RW || OTP
 * }

Reg 31h: Power recovery and VOFF control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: Don't pull down PWROK 1: Pull down PWROK during wakeup 0: Not enabled; 1: Enabled;  Auto-cleared 2.6 - 3.3V, 100 mV/step
 * 7 || Pull down PWROK when power recovers
 * 7 || Pull down PWROK when power recovers
 * RW || 0
 * 6-4 || Reserved || RW || 000
 * 3 || Power recovery enable ||
 * 3 || Power recovery enable ||
 * 3 || Power recovery enable ||
 * RW || 0
 * 2-0 || VOFF voltage:
 * 2-0 || VOFF voltage:
 * RW || 111
 * }

REG 32h: Shutdown control

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 0: Turn off all outputs at the same time 1: Reverse of power on sequence
 * 7 || Shutdown; Writing 1 turns off AXP152; auto-cleared || RW || 0
 * 6-3 || Reserved || RW || 0000
 * 2 || Output power off sequence
 * 6-3 || Reserved || RW || 0000
 * 2 || Output power off sequence
 * 2 || Output power off sequence
 * RW || 0
 * 1-0 || Reserved || RW || 00
 * }
 * }
 * }

REG 36h: PEK button parameters

 * {| class="wikitable"

! Bit !! Description !! R/W !! Default Value 00: 128ms; 01: 3s; 10: 1s; 11: 2s 0: 8ms ; 1: 64ms
 * 7-6 || Power on timing
 * 7-6 || Power on timing
 * RW || 10
 * 5-4 || Long press timing T = [ 1 + (bit 1-0) * 0.5 ] S; default: 1.5S || RW || 01
 * 3 || Automatic shutdown when pressed longer than Tshutdown || RW || 1
 * 2 || PWROK delay after power on
 * 3 || Automatic shutdown when pressed longer than Tshutdown || RW || 1
 * 2 || PWROK delay after power on
 * 2 || PWROK delay after power on
 * RW || 1
 * 1-0 || Tshutdown = [ 4 + (bit 1-0) * 2 ] s; default: 6s || RW || 01
 * }
 * }

Reg 37h: DC-DC operating frequency
Default value: 08h

REG 80h: DC-DC operation mode

 * {| class="wikitable"

! Bit !! Description !! Value !! R/W !! Default Value 1: PWM
 * 7-4 || Reserved || || RW || 0000
 * 3 || DC-DC1 operation mode
 * rowspan="4" | 0: PFM+PWM
 * 3 || DC-DC1 operation mode
 * rowspan="4" | 0: PFM+PWM
 * RW || 0
 * 2 || DC-DC2 operation mode || RW || 0
 * 1 || DC-DC3 operation mode || RW || 0
 * 0 || DC-DC4 operation mode || RW || 0
 * }
 * 0 || DC-DC4 operation mode || RW || 0
 * }
 * }
 * }

REG 90H: GPIO0 control

 * {| class="wikitable"

! Bit !! Description !! Values || R/W !! Default Value 000: output low 001: output high (DC-DC1) 010: PWM0 output (DC-DC1) 011: input 1XX: floating
 * 7 || Enable GPIO0 rising edge IRQ/wakeup || 1 to enable || RW || 0
 * 6 || Enable GPIO0 falling edge IRQ/wakeup || 1 to enable || RW || 0
 * 5-3 || Reserved ||
 * 2
 * rowspan="3" | GPIO0 pin function
 * rowspan="3" |
 * 2
 * rowspan="3" | GPIO0 pin function
 * rowspan="3" |
 * rowspan="3" |
 * rowspan="3" | RW
 * rowspan="3" | 111
 * 1
 * 0
 * }
 * 0
 * }

REG 91H: GPIO1 control

 * {| class="wikitable"

! Bit !! Description !! Values || R/W !! Default Value 000: output low 001: output high (DC-DC1) 010: PWM1 output (DC-DC1) 011: input 1XX: floating
 * 7 || Enable GPIO1 rising edge IRQ/wakeup || 1 to enable || RW || 0
 * 6 || Enable GPIO1 falling edge IRQ/wakeup || 1 to enable || RW || 0
 * 5-3 || Reserved ||
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * rowspan="3" |
 * rowspan="3" | RW
 * rowspan="3" | 111
 * 1
 * 0
 * }
 * 0
 * }

REG 92H: GPIO2 (SYSEN) control

 * {| class="wikitable"

! Bit !! Description !! Values || R/W !! Default Value 000: output low 001: floating 010: low noise LDO 011: input 1XX: floating
 * 7 || Enable GPIO2 rising edge IRQ/wakeup || 1 to enable || RW || 0
 * 6 || Enable GPIO2 falling edge IRQ/wakeup || 1 to enable || RW || 0
 * 5-3 || Reserved ||
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * rowspan="3" |
 * rowspan="3" | RW
 * rowspan="3" | 111
 * 1
 * 0
 * }
 * 0
 * }

REG 93H: GPIO3 (PWREN) control

 * {| class="wikitable"

! Bit !! Description !! Values || R/W !! Default Value 000: output low 001: floating 010: floating 011: input 1XX: floating
 * 7 || Enable GPIO3 rising edge IRQ/wakeup || 1 to enable || RW || 0
 * 6 || Enable GPIO3 falling edge IRQ/wakeup || 1 to enable || RW || 0
 * 5-3 || Reserved ||
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * 2
 * rowspan="3" | GPIO1 pin function
 * rowspan="3" |
 * rowspan="3" |
 * rowspan="3" | RW
 * rowspan="3" | 111
 * 1
 * 0
 * }
 * 0
 * }

REG 96h: GPIO2 LDO voltage control

 * {| class="wikitable"

! Bit !! Description !! Values || R/W !! Default Value
 * 7-4 || Reserved ||
 * 3-0 || GPIO2 LDO output voltage || Vout = 1.8 + 0.1 * (Bit 3-0) V || RW || 1010
 * }
 * 3-0 || GPIO2 LDO output voltage || Vout = 1.8 + 0.1 * (Bit 3-0) V || RW || 1010
 * }

REG 97h: GPIO [3:0] input

 * {| class="wikitable"

! Bit !! Description !! Values || R/W
 * 7-4 || Reserved ||
 * 3 || GPIO 3 input value || || R
 * 2 || GPIO 2 input value || || R
 * 1 || GPIO 1 input value || || R
 * 0 || GPIO 0 input value || || R
 * }
 * 1 || GPIO 1 input value || || R
 * 0 || GPIO 0 input value || || R
 * }
 * 0 || GPIO 0 input value || || R
 * }

REG 98h: PWM0 frequency control X0

 * {| class="wikitable"

! Bit !! Description !! Values || R/W PWM0 frequency = 2.25 MHz / (X0 + 1) / Y0
 * 7-0 || PWM0 frequency (X0) || 0 ~ 255 || RW
 * }
 * }

REG 99h: PWM0 frequency / duty cycle control Y0

 * {| class="wikitable"

! Bit !! Description !! Values || R/W
 * 7-0 || PWM0 frequency / duty cycle (Y0) || 0 ~ 255 || RW
 * }
 * }

REG 9Ah: PWM0 duty cycle control Z0

 * {| class="wikitable"

! Bit !! Description !! Values || R/W PWM0 duty cycle = Z0 / Y0
 * 7-0 || PWM0 duty cycle (Z0) || 0 ~ Y0 || RW
 * }
 * }

REG 9Bh: PWM1 frequency control X1

 * {|class="wikitable"

! Bit !! Description !! Values || R/W PWM1 frequency = 2.25 MHz / (X1 + 1) / Y1
 * 7-0 || PWM1 frequency (X1) || 0 ~ 255 || RW
 * }
 * }

REG 9Ch: PWM1 frequency / duty cycle control Y0

 * {| class="wikitable"

! Bit !! Description !! Values || R/W
 * 7-0 || PWM1 frequency / duty cycle (Y1) || 0 ~ 255 || RW
 * }
 * }

REG 9Dh: PWM1 duty cycle control Z1

 * {| class="wikitable"

! Bit !! Description !! Values || R/W PWM1 duty cycle = Z1 / Y1
 * 7-0 || PWM1 duty cycle (Z1) || 0 ~ Y1 || RW
 * }
 * }

Interrupts
See Interrupts section.

Spec Sheets
AXP152 Datasheet v1.0 (PDF, 34 pages, 2012-04-01)