AR100

= Overview =

The AR100 core is responsible for managing deep power save modes where the rest of the SoC is shut down. It's an OpenRISC based core with code loaded into internal SRAM.

= Specifications =


 * Name: AR100
 * Architecture: OpenRISC 1000
 * Implementation: OR1200 rev 1
 * Cache: 4K icache, no dcache
 * MMU: not present
 * FPU: not present
 * Byte ordering: Internally big endian. Byte-swapped on the data & instruction busses to little endian.
 * Instruction set(s) support: ORBIS32
 * Multiply-Accumulate (MAC) unit
 * Debug unit
 * Power management
 * Interrupt controller
 * Timer

= SPR data =

= Memory Map =


 * Have access to the same I/O as the main A31 core
 * Have access to the DRAM
 * All accesses are automatically byteswapped

H3
To be investigated: something seems to be weird about the SRAM A1 and DRAM access times in H3 when compared to A31. Maybe the MBUS clock speed makes some difference too?

= Clocking = The CPU clock can be configured with a register referenced as CCMU_CPUS_CFG in the Allwinner sun6i Linux source code.

CCMU_CPUS_CFG
Address: 0x01f01400

= Known issues = It is a quite old OpenRISC core so likely have many issues - exceptions in delay slots?

= Documentation =


 * OpenRISC 1000 Architecture Manual
 * OpenRISC 1200 IP Core Specification (Preliminary Draft)
 * OpenRISC 1200 Supplementary Programmer's Reference Manual

= Links =
 * https://github.com/skristiansson/ar100-info/
 * http://opencores.org/or1k/
 * http://github.com/openrisc/
 * http://www.openrisc.net/