USB OTG Controller Register Guide

= USB OTG = All Allwinner A-series SoCs come with one USB OTG controller. The controller has been identified as a Mentor Graphics Inventra HDRC (High-speed Dual Role Controller), which is supported by the "musb" driver. However, the register addresses are scrambled.

The A20 manual lists the following features
 * Complies with USB 2.0 specification
 * Supports high-speed, full-speed, and low-speed in host mode
 * Supports high-speed and full-speed in device mode
 * 64 byte endpoint 0 for control transfer
 * Supports up to 5 user configurable endpoints for bulk, isochronous, control, and interrupt bi-directional transfers

The USB OTG controller is connected to a port controller. Only the data pins are exported from the SoC. The port controller is also used to control or tune the USB PHYs for the other USB host controllers.

Info

 * USB OTG Controller base address: 0x01c13000
 * USB Port Controller base address: 0x01c13400

PCTL / POWER
Default value: 0x20

Offset: 0x40

MUSB offset: 0x01

DEVCTL
Default value: 0x20

Offset: 0x41

MUSB offset: 0x60

VEND0
Default value: 0x20

Offset: 0x43

MUSB offset: 0x??

Endpoint Registers
To access these under indexed mode, you must first write the endpoint number to the INDEX register.

ISCR
Default value: 0x40000000

Offset: 0x0

PHY_CTRL
Default value: 0x0000

Offset: 0x0