PPU

H6-generation and newer Allwinner SoCs feature a PPU power domain controller that contains controls for major hardware blocks, such as the GPU and Video Engine. On the D1, the PPU replaces the CPUIDLE block for hardware power sequencing of CPU idle states.

Register Layout (A100/A133)
See the BSP driver source. This version has a different register layout and only controls the GPU power domain. This might be specific to PowerVR versions of the SoC.

Register Layout (D1/R528/T113/TV303)
The "n" refers to the power domain ID (see above).

See also the BSP driver source.

PD_ACTIVE_CTRL_REG
This register likely only exists for the CPU power domain.