User:Ssvb/pcDuino2 with NANYA DDR3

= DRAM clock speed limit with the default settings =

Below are a10-tpr3-scan results from four LinkSprite pcDuino2 boards with NANYA DDR3 chips. Three boards (#1, #2 and #3) fail the lima-memtester check at 456MHz and one board (#4) fails it at just 432MHz. It means that the 408MHz DRAM clock speed, selected by LinkSprite for this board can be considered a safe choice.

#1 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]   dcdc3_vol        = 1250 dram_clk          = 456 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b96900) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=60, solidbits=2] Total number of successful memtester runs: 186  Best luminance at the height 0.5 is above 0x052222, score = 0.713 Best luminance at the height 1.0 is above 0x051111, score = 0.593 Best luminance at the height 2.0 is above 0x051111, score = 0.459 Best luminance at the height 4.0 is above 0x051111, score = 0.333  Read errors per lane: [10, 3, 4, 8]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are 12.5% eclipsed by the worst lane 3. Errors from the lane 1 are 25.0% eclipsed by the worst lane 3. Errors from the lane 2 are not intersecting with the errors from the worst lane 3. Write errors per lane: [7, 27, 15, 16]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 25.0% eclipsed by the worst lane 2. Errors from the lane 1 are 33.3% eclipsed by the worst lane 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2. #2 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,11,09]   dcdc3_vol        = 1250 dram_clk          = 456 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b96900) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x06060506 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=47, solidbits=7] Total number of successful memtester runs: 282  Best luminance at the height 0.5 is above 0x041111, score = 0.786 Best luminance at the height 1.0 is above 0x041111, score = 0.693 Best luminance at the height 2.0 is above 0x041111, score = 0.582 Best luminance at the height 4.0 is above 0x041111, score = 0.461  Read errors per lane: [2, 3, 4, 4]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 25.0% eclipsed by the worst lane 1. Errors from the lane 2 are not intersecting with the errors from the worst lane 1. Errors from the lane 3 are not intersecting with the errors from the worst lane 1. Write errors per lane: [2, 13, 21, 26]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 57.1% eclipsed by the worst lane 0. Errors from the lane 2 are 46.2% eclipsed by the worst lane 0. Errors from the lane 3 are 50.0% eclipsed by the worst lane 0. #3 pcDuino2, NANYA DDR3 456MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]   dcdc3_vol        = 1250 dram_clk          = 456 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x73d1800) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x06050506 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=44, solidbits=5] Total number of successful memtester runs: 345  Best luminance at the height 0.5 is above 0x031111, score = 0.814 Best luminance at the height 1.0 is above 0x031111, score = 0.734 Best luminance at the height 2.0 is above 0x031111, score = 0.638 Best luminance at the height 4.0 is above 0x031111, score = 0.530  Read errors per lane: [0, 4, 6, 8]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are not intersecting with the errors from the worst lane 0. Errors from the lane 2 are not intersecting with the errors from the worst lane 0. Write errors per lane: [3, 3, 31, 6]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. Errors from the lane 3 are 100.0% eclipsed by the worst lane 1. #4 pcDuino2, NANYA DDR3 432MHz, dcdc3=1.250V, emr1=0x00, zdata=[__,__,08,24]   dcdc3_vol        = 1250 dram_clk          = 432 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b91800) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=36, solidbits=9] Total number of successful memtester runs: 456  Best luminance at the height 0.5 is above 0x041111, score = 0.894 Best luminance at the height 1.0 is above 0x041111, score = 0.844 Best luminance at the height 2.0 is above 0x041111, score = 0.770 Best luminance at the height 4.0 is above 0x031111, score = 0.668  Read errors per lane: [0, 6, 0, 0]. Lane 2 is the most noisy/problematic. Write errors per lane: [1, 32, 6, 16]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 56.2% eclipsed by the worst lane 2. Errors from the lane 1 are 66.7% eclipsed by the worst lane 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2.

= DRAM clock speed limit with tuned settings =

Tests with 480MHz DRAM clock speed
#1 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]   dcdc3_vol        = 1250 dram_clk          = 480 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x32b27790 dram_tpr1         = 0xa0c0 dram_tpr2         = 0x23200 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=19, solidbits=6] Total number of successful memtester runs: 579  Best luminance at the height 0.5 is above 0x001111, score = 0.914 Best luminance at the height 1.0 is above 0x001111, score = 0.874 Best luminance at the height 2.0 is above 0x001111, score = 0.820 Best luminance at the height 4.0 is above 0x011111, score = 0.749  Read errors per lane: [0, 7, 2, 2]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2. Write errors per lane: [0, 3, 13, 10]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 90.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. #2 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]   dcdc3_vol        = 1250 dram_clk          = 480 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x32b27790 dram_tpr1         = 0xa0c0 dram_tpr2         = 0x23200 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=25, solidbits=9] Total number of successful memtester runs: 446  Best luminance at the height 0.5 is above 0x021111, score = 0.879 Best luminance at the height 1.0 is above 0x021111, score = 0.823 Best luminance at the height 2.0 is above 0x021111, score = 0.746 Best luminance at the height 4.0 is above 0x021111, score = 0.646  Read errors per lane: [4, 2, 1, 1]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 3. Errors from the lane 1 are not intersecting with the errors from the worst lane 3. Errors from the lane 2 are not intersecting with the errors from the worst lane 3. Write errors per lane: [0, 0, 8, 25]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 87.5% eclipsed by the worst lane 0. #3 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]   dcdc3_vol        = 1250 dram_clk          = 480 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x32b27790 dram_tpr1         = 0xa0c0 dram_tpr2         = 0x23200 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=14, solidbits=3, bitspread=2] Total number of successful memtester runs: 651  Best luminance at the height 0.5 is above 0x081111, score = 0.938 Best luminance at the height 1.0 is above 0x081111, score = 0.909 Best luminance at the height 2.0 is above 0x001111, score = 0.867 Best luminance at the height 4.0 is above 0x001111, score = 0.812  Read errors per lane: [0, 6, 0, 5]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Write errors per lane: [0, 0, 8, 0]. Lane 1 is the most noisy/problematic. #4 pcDuino2, NANYA DDR3 480MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30]   dcdc3_vol        = 1250 dram_clk          = 480 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x32b27790 dram_tpr1         = 0xa0c0 dram_tpr2         = 0x23200 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=36, solidbits=10] Total number of successful memtester runs: 350  Best luminance at the height 0.5 is above 0x051111, score = 0.836 Best luminance at the height 1.0 is above 0x051111, score = 0.763 Best luminance at the height 2.0 is above 0x041111, score = 0.670 Best luminance at the height 4.0 is above 0x041111, score = 0.557  Read errors per lane: [0, 4, 0, 0]. Lane 2 is the most noisy/problematic. Write errors per lane: [0, 0, 42, 13]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.

Tests with 504MHz DRAM clock speed
#1 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30] <table border=1 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> <table border=0 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> dcdc3_vol        = 1250 dram_clk          = 504 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x34d37790 dram_tpr1         = 0xa0d0 dram_tpr2         = 0x23600 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=17, solidbits=16] Total number of successful memtester runs: 428  Best luminance at the height 0.5 is above 0x021111, score = 0.860 Best luminance at the height 1.0 is above 0x021111, score = 0.798 Best luminance at the height 2.0 is above 0x021111, score = 0.718 Best luminance at the height 4.0 is above 0x021111, score = 0.621  Read errors per lane: [0, 7, 4, 6]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 16.7% eclipsed by the worst lane 2. Errors from the lane 1 are 25.0% eclipsed by the worst lane 2. Write errors per lane: [0, 3, 20, 15]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. #2 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30] <table border=1 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> <table border=0 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> dcdc3_vol        = 1250 dram_clk          = 504 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x34d37790 dram_tpr1         = 0xa0d0 dram_tpr2         = 0x23600 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=36, bitflip=8, xor=1] Total number of successful memtester runs: 283  Best luminance at the height 0.5 is above 0x041111, score = 0.786 Best luminance at the height 1.0 is above 0x041111, score = 0.694 Best luminance at the height 2.0 is above 0x041111, score = 0.583 Best luminance at the height 4.0 is above 0x041111, score = 0.463  Read errors per lane: [3, 0, 0, 3]. Lane 3 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 3. Write errors per lane: [0, 2, 15, 39]. Lane 0 is the most noisy/problematic. Errors from the lane 1 are 100.0% eclipsed by the worst lane 0. Errors from the lane 2 are 100.0% eclipsed by the worst lane 0. #3 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30] <table border=1 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> <table border=0 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> dcdc3_vol        = 1250 dram_clk          = 504 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x34d37790 dram_tpr1         = 0xa0d0 dram_tpr2         = 0x23600 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=19, solidbits=10, bitspread=1] Total number of successful memtester runs: 472  Best luminance at the height 0.5 is above 0x001111, score = 0.875 Best luminance at the height 1.0 is above 0x011111, score = 0.818 Best luminance at the height 2.0 is above 0x011111, score = 0.745 Best luminance at the height 4.0 is above 0x011111, score = 0.656  Read errors per lane: [0, 9, 1, 4]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2. Write errors per lane: [0, 0, 17, 2]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. #4 pcDuino2, NANYA DDR3 504MHz, dcdc3=1.250V, emr1=0x42, zdata=[04,04,26,30] <table border=1 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> <table border=0 style='border-collapse: collapse; empty-cells: show; font-family: Consolas,Monaco,Lucida Console,Liberation Mono,DejaVu Sans Mono,Bitstream Vera Sans Mono,Courier New, monospace; font-size: small; white-space: nowrap; background: #F0F0F0;'> dcdc3_vol        = 1250 dram_clk          = 504 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x2135e00 dram_odt_en       = 3 dram_tpr0         = 0x34d37790 dram_tpr1         = 0xa0d0 dram_tpr2         = 0x23600 dram_tpr3         = 0x61111 dram_emr1         = 0x42 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=37, bitflip=14] Total number of successful memtester runs: 211  Best luminance at the height 0.5 is above 0x051111, score = 0.747 Best luminance at the height 1.0 is above 0x051111, score = 0.638 Best luminance at the height 2.0 is above 0x051111, score = 0.508 Best luminance at the height 4.0 is above 0x051111, score = 0.375  Read errors per lane: [0, 3, 1, 1]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 2. Errors from the lane 1 are not intersecting with the errors from the worst lane 2. Write errors per lane: [2, 6, 43, 14]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 50.0% eclipsed by the worst lane 1. Errors from the lane 3 are 50.0% eclipsed by the worst lane 1.