PRCM

The A31 and A23 SoCs contain a seperate module called PRCM, or "Power, Reset & Clock Management".

The neighboring address space also has new IP blocks, such as a GPIO controller for PL/PM pins,

shared UART, TWI, and the new P2WI (A31) or RSB (A23) controllers. These are not documented in the

user manuals, but the address spaces and registers can be found in the A23 SDK.

= Power, Reset & Clock Management =

Overview
This module controls APB0 clocks, resets, and power domains.

Features

 * Support clock configuration
 * Support module reset
 * Support GPU power clamp control
 * Support system core power clamp control
 * Support one clock output channel

Clocks
This module controls the clocks for the AR100 OpenRISC core (named CPU0 in some Allwinner sources), AHB0, APB0, and some special clocks in this cluster of IP blocks.

Registers
Base address: 0x01f01400

The registers are documented using the A23 user manual, with A31 bits added from Allwinner code.

CPUS_CFG
Default value: unknown

Offset: 0x0000

$$CPU0\_CLK = \frac{\mathrm{CPU0\_CLK\_SRC}}{M \times N}$$

APB0_CLK_DIV_REG
Default value: 0x00000000

Offset: 0x000C

A31
Allwiner A31 u-boot sources states:

A23
The A23 manual states:

APB0_GATING_REG
Default value: 0x00000000

Offset: 0x0028

APB0_MODULE_RST_REG
Default value: 0x00000000

Offset: 0x00B0

= R_PIO = The A31 SoC (and SoCs based on the A31, such as the A23) has a separate pinmux/GPIO controller

for the PL and PM pins. Sources for sun9iw1 in the A23 SDK also mention PN pins, possibly

controlled from the same IP block. The SDK sources list this new controller as "R_PIO".

Registers
Base address: 0x01f02c00

The register format is the same as the PIO controller.