DRAM Calibration Results/Olimex A20-OLinuXino-Micro Rev.E

DRAM calibration results for Olimex A20-OLinuXino-Micro rev. E board. = dram_emr1 =

432MHz, emr1=0x4   dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 300 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x7f (0x5294a00) dram_odt_en       = 0 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x0 dram_emr1         = 0x4 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05060505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=20, bitflip=18] Total number of successful memtester runs: 309  Best luminance at the height 0.5 is above 0x021111, score = 0.760 Best luminance at the height 1.0 is above 0x021111, score = 0.662 Best luminance at the height 2.0 is above 0x021111, score = 0.559 Best luminance at the height 4.0 is above 0x021111, score = 0.462  Read errors per lane: [0, 0, 15, 9]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 1. Write errors per lane: [0, 0, 14, 14]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1.

432MHz, emr1=0x44   dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 300 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x7f (0x5294a00) dram_odt_en       = 0 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x21111 dram_emr1         = 0x44 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05060605 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=20, bitflip=12] Total number of successful memtester runs: 267  Best luminance at the height 0.5 is above 0x031111, score = 0.745 Best luminance at the height 1.0 is above 0x031111, score = 0.640 Best luminance at the height 2.0 is above 0x031111, score = 0.528 Best luminance at the height 4.0 is above 0x031111, score = 0.421  Read errors per lane: [0, 0, 13, 6]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 16.7% eclipsed by the worst lane 1. Write errors per lane: [1, 1, 14, 13]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.

432MHz, emr1=0x40   dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 300 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x7f (0x5294a00) dram_odt_en       = 0 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x21111 dram_emr1         = 0x40 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x05060606 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=17, bitflip=11] Total number of successful memtester runs: 264  Best luminance at the height 0.5 is above 0x031111, score = 0.746 Best luminance at the height 1.0 is above 0x031111, score = 0.642 Best luminance at the height 2.0 is above 0x031111, score = 0.529 Best luminance at the height 4.0 is above 0x031111, score = 0.421  Read errors per lane: [0, 0, 12, 8]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 1. Write errors per lane: [1, 1, 8, 7]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 100.0% eclipsed by the worst lane 1. Errors from the lane 3 are 100.0% eclipsed by the worst lane 1.

= zq =

 dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 300 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x4e (0x199cb00) dram_odt_en       = 3 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x41111 dram_emr1         = 0x4 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x06060606 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=18, bitflip=4] Total number of successful memtester runs: 180  Best luminance at the height 0.5 is above 0x061111, score = 0.709 Best luminance at the height 1.0 is above 0x061111, score = 0.587 Best luminance at the height 2.0 is above 0x061111, score = 0.451 Best luminance at the height 4.0 is above 0x061111, score = 0.324  Read errors per lane: [1, 1, 0, 2]. Lane 0 is the most noisy/problematic. Errors from the lane 2 are not intersecting with the errors from the worst lane 0. Errors from the lane 3 are not intersecting with the errors from the worst lane 0. Write errors per lane: [5, 5, 16, 16]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 40.0% eclipsed by the worst lane 1. Errors from the lane 3 are 40.0% eclipsed by the worst lane 1. A20-new-u-boot   dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 400 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x5e (0x31deb00) dram_odt_en       = 3 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x41111 dram_emr1         = 0x4 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x06060606 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=15, bitflip=11] Total number of successful memtester runs: 436  Best luminance at the height 0.5 is above 0x031111, score = 0.890 Best luminance at the height 1.0 is above 0x031111, score = 0.838 Best luminance at the height 2.0 is above 0x031111, score = 0.763 Best luminance at the height 4.0 is above 0x031111, score = 0.656  Read errors per lane: [0, 0, 0, 4]. Lane 0 is the most noisy/problematic. Write errors per lane: [6, 6, 19, 19]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 50.0% eclipsed by the worst lane 1. Errors from the lane 3 are 50.0% eclipsed by the worst lane 1.

A20-new-u-boot   dcdc3_vol        = 1300 dram_clk          = 432 mbus_clk          = 300 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 7 dram_zq           = 0x6e (0x31deb00) dram_odt_en       = 3 dram_tpr0         = 0x2a906690 dram_tpr1         = 0xa068 dram_tpr2         = 0x22e00 dram_tpr3         = 0x41111 dram_emr1         = 0x4 dram_emr2         = 0x8 dram_emr3         = 0x0 dqs_gating_delay  = 0x06060606 active_windowing  = 1 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=22, bitflip=6, bitspread=1] Total number of successful memtester runs: 470  Best luminance at the height 0.5 is above 0x031111, score = 0.905 Best luminance at the height 1.0 is above 0x031111, score = 0.859 Best luminance at the height 2.0 is above 0x031111, score = 0.791 Best luminance at the height 4.0 is above 0x031111, score = 0.692  Read errors per lane: [0, 0, 0, 2]. Lane 0 is the most noisy/problematic. Write errors per lane: [17, 16, 19, 19]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are 100.0% eclipsed by the worst lane 1. Errors from the lane 2 are 56.2% eclipsed by the worst lane 1. Errors from the lane 3 are 52.9% eclipsed by the worst lane 1.