A10 DRAM Controller Calibration

The DRAM controller supports setting quite a number of various delays and phase shifts to improve signal integrity. Some calibration may be necessary for getting the best results out of it. Allwinner offers the dram_tpr3 parameter for such tuning. And it can be already used to improve dram overclocking potential quite significantly. For example, setting dram_tpr3=0x72222 for the Cubietruck allows to clock DRAM nearly up to 600MHz on some devices.

It is suspected that we have Synopsys DesignWare DDR2/3-Lite Memory Controller IP (MCTL) (or maybe MCTL from C*Core Technology) combined with DDR2/3-Lite PHY IP in A10/A13/A20. The documentation at least for the PHY part can be found in the RK30XX manual, but unfortunately it seems like RK30XX is using DDR2/3-Lite SDRAM Protocol Controller IP (PCTL) instead of MCTL.

=ZQ calibration=


 * DDR3 Dynamic On-Die Termination
 * DDR3 ZQ Calibration

=CLK-DQS timing de-skew=

A bit of it is covered in New Features of DDR3 SDRAM

=Other links=

Some links, which are not directly describing sunxi hardware, but may be useful for grasping the general concept:
 * Altera - Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
 * Freescale - i.MX 6 Series DDR Calibration
 * DDR3 introduction slides