Xunlong Orange Pi PC

Orange Pi PC is H3 based development board produced by Xunlong.

= Identification = The PCB has the following silkscreened on it: Orange Pi PC V1.2

= Sunxi support =

Current status
Unsupported.

Images
A bit tricky to get this thing booting up with a working image.

My unit works with any of the downloads from http://www.orangepi.org/orangepibbsen/forum.php?mod=viewthread&tid=342

Look in the vfat partition after you make the SD card. There are two uImage files and a number of device tables. There is no default 'script.bin', I copied the script.bin.OPI-Pc_1080p60 to script.bin and copied uImage_OPI-2 to uImage. This got the ethernet working.

Manual build
You can build things for yourself by following our Manual build howto and by choosing from the configurations available below.

Mainline U-Boot
Use the orangepi_pc build target (supported since v2016.01-rc2).

Sunxi/Legacy Kernel
Use the  file.

Mainline kernel
As yet there is no support for the Orange Pi PC in the mainline kernel


 * Some patches for mainline support for the h3 can be found on mripard's kernel fork
 * There are signs of work on 4.3 here and he claims that he had a working 4.2 kernel.

Use the  device-tree binary.

= Tips, Tricks, Caveats =


 * Heat issues when using common OS images for the OPi PC. Without a heatsink the Orange Pi PC overheats easily and will drop cores to thwart further temperature increase and unfortunately the heatsink provided by the manufacturer does little to help. The low cost $15 variant does not have any heatsink included at all. This is the result of 'factory settings' overclocking/overvolting the H3 way too much. With adjusted dvfs entries and an upper limit of 1.2 GHz SoC temperature stays below 75°C without heatsink when running cpuburn-a7 on all 4 cores. Using a quality heatsink, some airflow and reasonable cpufreq settings the H3 remains below 60°C even under full load at an ambient temperature of 22°C.


 * It is also possible to power the device via GPIO pin header: connect +5V to either pin 2 or 4 (both are connected to DCIN test point) and GND to pin 6.

FEL mode
The Orange Pi PC will fail over to FEL mode if it doesn't detect a card present in the µSD slot. There is no dedicated FEL button.

LEDs


The board has two LEDs:
 * A red LED, connected to the PA15 pin.
 * A green LED, connected to the PL10 pin.

Unlike other sunxi SoCs that are accompanied with a PMU it's not possible to use the more advanced LED driver in Allwinner's kernel (no different triggers available, just on/off)

CPU clock speed limit
All H3 based Orange Pis have been advertised falsely as being capaple to run at 1.6GHz from the beginning. But Steven Zhao, the person behind Xunlong, knew already back in March 2015 about anything beyond 1.2 GHz being an "extremity_freq" and useable for benchmarks only but not for stable useage.

The following is a common comment in the FEX files from various H3 SDK variants (and which appears to originate from Allwinner):
 * dvfs voltage-frequency table configuration
 * pmuic_type:0:none, 1:gpio, 2:i2c
 * pmu_gpio0: gpio config.
 * pmu_levelx: 0~9999: voltage(mV), 10000~90000:gpio0 state. voltage form high to low.
 * extremity_freq(Hz): cpu extremity frequency when run benckmark or demo apk
 * 1536MHz@1500mV with radiator, 1296MHz@1340mV without radiator
 * max_freq: cpu maximum frequency, based on Hz, can not be more than 1200MHz
 * min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz
 * LV_count: count of LV_freq/LV_volt, must be < 16
 * LV1: core vdd is 1.50v if cpu frequency is (1296Mhz, 1536Mhz]
 * LV2: core vdd is 1.34v if cpu frequency is (1200Mhz, 1296Mhz]
 * LV3: core vdd is 1.32v if cpu frequency is (1008Mhz, 1200Mhz]
 * LV4: core vdd is 1.20v if cpu frequency is (816Mhz,  1008Mhz]
 * LV5: core vdd is 1.10v if cpu frequency is (648Mhz,   816Mhz]
 * LV6: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV7: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV8: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV5: core vdd is 1.10v if cpu frequency is (648Mhz,   816Mhz]
 * LV6: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV7: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]
 * LV8: core vdd is 1.04v if cpu frequency is (0Mhz,     648Mhz]

The Orange Pi PC board uses the SY8106A voltage regulator for providing the CPU core voltage (VDD_CPUX). The default CPU voltage is 1.2V after power-on (selected by the resistors on the PCB) and can be changed at runtime by software via I2C interface. According to the table above, this default voltage should be safe for using with the CPU clock frequencies up to 1008MHz. The H3 datasheet specifies 1.5V as the absolute maximum for the VDD_CPUX voltage and 1.4V as the recommended maximum.

DRAM clock speed limit
DRAM is clocked at 672 MHz by the hardware vendor. But the reliability still needs to be verified. One of the ways of doing reliability tests may be https://github.com/ssvb/lima-memtester/releases/tag/20151207-orange-pi-pc-fel-test (it checks the Orange Pi PC DRAM setup in the current mainline U-Boot v2016.01-rc2 + a bugfix).

Note that these are just preliminary results and some tuning/bugfixing may be still possible.

OpenRISC core
Also named as AR100, CPUS and "arisc" in various Allwinner materials, which may cause a bit of confusion. According to the Orange Pi PC schematics, VDD_CPUS is connected to VDD_RTC. It means that the voltage powering the OpenRISC core is programmable via the hardware register VDD_RTC_REG (at 0x1F00190) and can be configured between 0.7V and 1.4V. The H3 datasheet says that 1.4V is the absolute maximum for VDD_CPUS and 1.1V-1.3V is the recommended range. The reset default for VDD_RTC voltage is 1.1V.

Below is a quick evaluation of the potential clock speed limit of the OpenRISC core on just a single board (ssvb's) by running a naive recursive fibonacci function:

Without I-Cache, fetching each instruction from SRAM takes 3 cycles instead of just 1.

Please note that the intended use of the OpenRISC core in Allwinner devices is keeping a watch while the main Cortex-A7 CPU and the rest of the SoC peripherals are powered off in deep power save modes. In this usage scenario it is likely clocked at just the minimum possible clock frequency 32 KHz.

Camera module
Xunlong sells also a cheap 2MP camera (an attempt to fix the driver's limited resolutions can be found here). Unlike Orange Pi Plus/2 that can directly connect to the camera module for the PC an 'expansion board' is needed (see gallery below). If you order from Xunlong simply say that you need the camera for Orange Pi PC and they ship camera together with the small board.

Locating the UART
The UART pins are located between HDMI and power jack of the board. They are marked as TX, RX and GND on the PCB. Just attach some leads according to our UART Howto.

= Pictures =

= Also known as =

= See also =


 * Xunlong Orange Pi site
 * Official Github Repository.
 * Official Orange Pi Form.
 * H3_Manual_build_howto
 * Orange Pi PC Schematics 1.2

Manufacturer images
A various amount of prebuilt images is provided via OrangePi's Website. Some people are also running images generated by forum user loboris

= References =