Timers Controller Register guide

= Timer Controller = The A10 SoC has 6 timers, an RTC, alarm timer and an AVS-timer.

Timer 0 and 1 can configure their input to come from various sources, the internal oscillator, the external 32K crystal or the external 24MHz crystal. Their main function is the provide an interrupt for the scheduler in the kernel. They both are programmable, 24bit wide and can safely overflow. Reload mode can be programmed to auto-reload or not.

Timer 2 is usable by the kernel to generate periodic interrupts.

Timers 3, 4 and 5 are general purpose timers.

The watchdog timer resets the system in case of system errors. It can be re-purposed as a regular 16bit interval timer to request an interrupt. The generated signal is a the reset signal.

The Real Time Clock (RTC) timer is normally a battery powered timer to be used as a timekeeping device. If software tells it that the current year is a leap year, it will automatically correct the dates for this year. On the SoC it has a dedicated power pin (RTCVDD) to supply either battery or live power.

The Alarm timer can trigger an alarm even when battery powered (via the RTC). When running from battery only the power-management wakeup signal is activated. Otherwise the power-management wakeup signal and the alarm interrupt are triggered.

An Audio Video Sync (AVS) timer with as purpose to synchronize audio and video data.

One large 64bit counter, actually split up into two 32bit registers.

Info
Timer Base address: 0x01c20d00

TMR_IRQ_EN
Default value: 0x00000000

Offset: 0x0000

TMR_IRQ_STA
Default value: 0x00000000

Offset: 0x0004

TMR_0_CTRL
Default value: 0x00000004

Offset: 0x0010
 * ) A Timer Cycle (T-Cycle) is defined as Timer clock source/pre-scale

TMR_0_INTR_VAL
Default value: undefined

Offset: 0x0014

TMR_0_CUR_VAL
Default value: undefined

Offset: 0x0018

TMR_1_CTRL
Default value: 0x00000004

Offset: 0x0020

TMR_1_INTR_VAL
Default value: undefined

Offset: 0x0024

TMR_1_CUR_VAL
Default value: undefined

Offset: 0x0028

TMR_2_CTRL
Default value: 0x00000004

Offset: 0x0030

TMR_2_INTR_VAL
Default value: undefined

Offset: 0x0034

TMR_2_CUR_VAL
Default value: undefined

Offset: 0x0038

TMR_3_CTRL
Default value: 0x00000000

Offset: 0x0040

TMR_3_INTR_VAL
Default value: undefined

Offset: 0x0044

TMR_4_CTRL
Default value: 0x00000004

Offset: 0x0050

TMR_4_INTR_VAL
Default value: undefined

Offset: 0x0054

TMR_4_CUR_VAL
Default value: undefined

Offset: 0x0058

TMR_5_CTRL
Default value: 0x00000004

Offset: 0x0060

TMR_5_INTR_VAL
Default value: undefined

Offset: 0x0064

TMR_5_CUR_VAL
Default value: undefined

Offset: 0x0068

TMR_AVS_CTRL
Default value: 0x00000000

Offset: 0x0080

TMR_AVS0_VAL
Default value: 0x00000000

Offset: 0x0084

TMR_AVS1_VAL
Default value: 0x00000000

Offset: 0x0088

TMR_AVS_DIV
Default value: 0x05db05db

Offset: 0x008c

TMR_WDT_CTRL
Default value: undefined

Offset: 0x0090

TMR_WDT_MODE
Default value: 0x00000000

Offset: 0x0094

TMR_CNT64_CTRL
Default value: 0x00000000

Offset: 0x00a0

TMR_CNT64_LO
Default value: 0x00000000

Offset: 0x00a4

TMR_CNT64_HI
Default value: 0x00000000

Offset: 0x00a8

TMR_32KHZ_OSC_CTRL
Default value: 0x00004000

Offset: 0x0100

TMR_RTC_DATE
Default value: undefined

Offset: 0x0104

TMR_RTC_TIME
Default value: undefined

Offset: 0x0108

TMR_ALARM_CNT
Default value: undefined

Offset: 0x010c

TMR_ALARM_WK
Default value: undefined

Offset: 0x0110

TMR_ALARM_EN
Default value: undefined

Offset: 0x0114

TMR_ALARM_IRQ
Default value: undefined

Offset: 0x0118

TMR_ALARM_IRQ_STATUS
Default value: undefined

Offset: 0x011c

TMR_GP0
Default value: undefined

Offset: 0x0120

TMR_GP1
Default value: undefined

Offset: 0x0124

TMR_GP2
Default value: undefined

Offset: 0x0128

TMR_GP3
Default value: undefined

Offset: 0x012c

CPU_CFG
Default value: 0x000000c0

Offset: 0x013c