A80/Clock Control Module

= Clock Control Module =

Overview
Allwinner's A80 has 12 Phase Locking Loop's (PLL's), and a 24MHz main crystal oscillator. A low power 32.768 KHz clock is supplied externally, by the AC100 chip.

The 24MHz crystal oscillator is mandatory and is responsible for supplying a clock source for the PLL. The 32kHz clock is only used by a few devices.

Many devices being driving by any of these clocks have often 2 clocks connected to them. One of the clocks drives the module itself, the other clock matches the bus to whatever it is connected (usually the CPU).

Clock generation
All PLL's are fed from the 24 MHz reference clock.

Clock Control Module Registers
Clock Control Module Base address: 0x06000000

CCM_PLL1_CFG
Default value: ??

Offset: 0x0000

CCM_PLL2_CFG
Default value: ??

Offset: 0x0004

CCM_PLL4_CFG
Default value: ??

Offset: 0x000c

CCM_PLL12_CFG
Default value: ??

Offset: 0x002c

CCM_APB0_GATE
Default value: 0x00000000

Offset: 0x0590

CCM_APB1_GATE
Default value: 0x00000000

Offset: 0x0594

CCM_APB0_RST
Default value: 0x00000000

Offset: 0x0590

CCM_APB1_RST
Default value: 0x00000000

Offset: 0x05b4