Xunlong Orange Pi Zero

Orange Pi Zero is H2+ based development board produced by Xunlong.

= Identification = The PCB has the following silkscreened on it: Orange Pi Zero V1.1

= Sunxi support =

Current status
Unsupported but a preliminary Armbian legacy image with nearly full hardware support already exists. To discuss issues or look for tweaks see the respective thread in Armbian forum.

Mainline U-Boot
Just use the orangepi_one_defconfig until specific Zero support has materialized.

You can define CONFIG_SPL_SPI_SUNXI=y and CONFIG_SPL_SPI_FLASH_SUPPORT=y to get SPI flash support (if you have a chip soldered). If the U-Boot build boots (test by either writing u-boot-sunxi-with-spl.bin to a uSD card or booting via FEL), you can write this very image to the SPI flash to boot from there: $ sunxi-fel -v -p spiflash-write 0 u-boot-sunxi-with-spl.bin

Mainline kernel
Use the sun8i-h3-orangepi-one.dtb with an H3 enabled kernel.

= Expansion Port =

The Orange Pi Zero has a 26-pin, 0.1" unpopulated connector with several low-speed interfaces.

The Orange Pi Zero has another 13-pin, 0.1" header with several low-speed interfaces.

A cheap 'Expansion board' for this connector is now available exposing all interfaces (2 x USB, IR receiver, microphone and combined AV TRRS jack) and can be ordered together with the board on Aliexpress. Attention: Expect problems when using the Expansion board to connect more USB devices when you want to power the board through the Micro USB connector (known to cause all sorts of troubles). Voltage drops affecting stability are likely to happen so better think about providing power through 5V/GND pins on the 26 pin header in this case.

= Tips, Tricks, Caveats =

Compatibility
The H2+ SoC used on this board seems to be a featureless H3 (no Gbit Ethernet MAC and no 4K HDMI output). Orange Pi Zero uses the same SY8113B (datasheet) voltage regulator as used on Orange Pi One/Lite that can adjust its output voltage driven by two resistors between 1.1V and 1.3V. DVFS configuration and settings for Orange Pi One/Lite work exactly the same on OPi Zero.

It should be noted that the official OS images from orangepi.org currently use broken settings leading to VDD_CPUX voltage remaining at 1.3V all the time and leading to unnecessary overheating (see here for details).

Powering the board
Orange Pi Zero unlike all other Orange Pi boards so far can be powered through the Micro USB jack (being a normal USB OTG port otherwise) or via one of the Expansion Port pin headers (using 5V/GND pins).

Passive PoE
The board also provides a PoE (Power over Ethernet) option since Ethernet pins 4/5 and 7/8 are routed to solder pads (see picture on the right and below in gallery).

By soldering zero ohm resistors to R29 and R358 passive PoE providing 5V could be used to power the board. Note that 5V won't work over large distances (greater than ~4m) since cable resistance is too high and the voltage will drop.

It's also possible to solder a buck converter between the R29 pads (PoE+ to 5V VBUS) and R358 (GND) so that passive PoE with the higher voltages (24V or 48V) can be used. The buck converter is used to step the input voltage (24/48V) down to 5V.

Using Orange Pi Zero as a PoE injector
If you solder 0 Ohm resistors to R29 and R358 and power the Orange Pi Zero via Micro USB or GPIO as described in Powering the board then 5V power will also be output via the Ethernet port.

802.3af/at PoE
The Orange Pi Zero does not support 802.3af Mode A, which means it is not compliant with the PoE and PoE+ standards. PoE switches do not negotiate the output voltage, only the output power (12.95W for 802.3af and 25.5W for 802.3at).

Soldering 0 Ohm resistors to R29 and R358 will not make the Orange Pi Zero work with switches implementing PoE/PoE+

You need an 802.3af/at compliant power supply like the TP-Link TL-POE10R to use the Orange Pi Zero with a PoE switch. This is the same procedure you would use for any other non-PoE enabled device.

SPI NOR flash
Xunlong has been asked to add support for Bootable SPI flash and while Orange Pi PC 2 came already with SPI NOR flash soldered it was optional on first Orange Pi Zero production batches. Starting in mid Dec 2016 Xunlong sells the 512 MiB variant with 16 Mb (2 MB) flash pre-populated and next production batch of the 256 MiB version will have NOR flash soldered too.

Putting u-boot on SPI NOR
It's possible to put u-boot on SPI NOR but you can't currently load a kernel etc from the SPI NOR (missing higher level driver for the SPI controller) so you still need another boot media. Also if you want to save the environment you'll need an SD card.

To put u-boot on SPI NOR you first need to solder on an SPI flash. The W25Q128FVSIG is 16 megabytes, cheap and easy to source and the correct package for the footprint on the orangepi zero PCB. Soldering it on is relatively easy. Clean the footprint with solder wick first to make it flat and be careful of all of the small SMD passives close by.

To make u-boot bootable from SPI flash you seem to need these 3 options enabled: CONFIG_SPL_SPI_FLASH_SUPPORT, CONFIG_SPI_BOOT, CONFIG_SPL_SPI_SUNXI.

Because u-boot can't actually interact with the flash once it's booted you need to write u-boot to it from linux. With a mainline kernel you need to enable the SPI NOR drivers in the kernel config and add a DT node something like this:

&spi0 { status = "okay"; flash: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q128"; reg = <0>; spi-max-frequency = ; }; };

This will give you /dev/mtd0 that you can use to write u-boot to the flash. Using flashcp from mtd-utils caused SPI transfer errors. Using dd with a blocksize of 32 causes the kernel to complain about the erase size not being optimal for the flash but copied a working copy of u-boot to it. Using flash_erase from mtd-utils to erase the area u-boot is going to be copied to before doing so is probably a good idea.

flash_erase /dev/mtd0 0 128 dd if=u-boot-sunxi-with-spl.bin of=/dev/mtd0 bs=32

Once Linux is running you could mount a filesystem from the flash etc but it's currently a bit pointless if you have to load the kernel and device try from somewhere else first.

WiFi
On OPi Zero PG10 pin seems to be used to implement WoWLAN. XR819 module contains an own ARM core and iw list when used with Allwinner's BSP driver mentions: WoWLAN support: * wake up on anything (device continues operating normally) * wake up on disconnect



Locating the UART
The UART pins are located next to Ethernet jack on the board. They are marked as TX, RX and GND on the PCB. Just attach some leads according to our UART Howto.

LEDs
The board has two LEDs next to DRAM:
 * A red LED, connected to the PA17 pin.
 * A green LED, connected to the PL10 pin.

Note: All other H3 devices currently supported connect the red led to PA15 pin so in case you want to toggle led status in u-boot pretty early OPi Zero needs special treatment.

JTAG
Connect gnd and target voltage to any of the gnd and vcc3v3-ext pins on the 2x13 expansion connector (con4). Pin 11 (uart2_rx) is TCK, pin 13 (uart2_tx) is TMS, pin 15 (uart2_cts) is TDI and pin 22 (uart2_rts) is TDO.

The JTAG sel pins that seem to be used to enable JTAG at chip power on aren't broken out but you can enable JTAG on the expansion connector once uboot has started with this command (add it to boot script and compile  again to make it permanent):

OpenOCD configuration should look something like this (based on the config from this page in Japanese): source [find interface/ftdi/dp_busblaster_kt-link.cfg] adapter_khz 300 transport select jtag reset_config none gdb_breakpoint_override hard

if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { set _CHIPNAME sun8iw7 }

if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID } else { set _DAP_TAPID 0x5ba00477 }

jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4 -ircapture 0x01 -irmask 0x0f

set _TARGETNAME0 $_CHIPNAME.cpu0 set _TARGETNAME1 $_CHIPNAME.cpu1 set _TARGETNAME2 $_CHIPNAME.cpu2 set _TARGETNAME3 $_CHIPNAME.cpu3

target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap -coreid 2 target create $_TARGETNAME3 cortex_a -chain-position $_CHIPNAME.dap -coreid 3 target smp $_TARGETNAME0 $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3

$_TARGETNAME0 configure -event gdb-attach { cortex_a dbginit } $_TARGETNAME1 configure -event gdb-attach { cortex_a dbginit } $_TARGETNAME2 configure -event gdb-attach { cortex_a dbginit } $_TARGETNAME3 configure -event gdb-attach { cortex_a dbginit }

This is a little bit fragile but it works well enough to set breakpoints in the kernel with GDB so should be useful when debugging drivers etc.

= Pictures =

= Variants =

= Also known as =

= See also =


 * Xunlong Orange Pi site
 * Official Github Repository.
 * Official Orange Pi Forums.
 * Orange Pi Zero Schematics 1.1

Manufacturer images
= References =