User:Ssvb/pcDuino2 with HYNIX DDR3 reliability test

= The a10-tpr3-scan results and their interpretation =

DRAM reliability test results for LinkSprite pcDuino2 board with HYNIX DDR3 chips, using the default DRAM configuration from Linksprite_pcDuino_defconfig in U-Boot b2015.10-rc4.

Because some of the parameters (ZQ and DQS gating delay) are auto-configured by the DRAM controller on every reboot, there may be slight variations between the DRAM controller state. Basically, one of 3 possible configurations gets randomly selected. One of these configurations (ZDATA = 0x6b91800) is very unreliable and fails the lima-memtester check very fast (usually needs less than a minute). Two other states are mildly unreliable and it takes several hours to detect and report a problem.

Reading the tables is not difficult. Any table cell color other than green is bad. The numbers inside table cells represent different 'dram_tpr3' values. The rest of the dram configuration settings are the same and listed on the left side. The default tpr3 value is 0x00000 (located in the center of the table), so we want to have a green cell there. For additional safety headroom, the surrounding cells around the selected 'tpr3' should be preferably green too.

Because the a10-tpr3-scan script has timing constraints and can't test every 'tpr3' value long enough, green cells in the tables do not mean perfect reliability. What we can be certain is that the non-green cells mean unreliable configuration for sure. As we can see in the tables, the tpr3=0x00000 cell is green for "reboot state #2" and "reboot state #3", however it has non-green neighbours. And long overnight lima-memtester runs still fail for tpr3=0x00000.

The DRAM clock speed needs to be dropped to 360MHz in order to make sure that it does not fail lima-memtester (reducing to just 384MHz is not enough).

For more information about a10-tpr3-scan, you can check the A10 DRAM Controller Calibration page.

pcDuino2 with HYNIX DDR3 @408MHz (reboot state #1) - very unreliable   dcdc3_vol        = 1250 dram_clk          = 408 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b91800) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x06050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=20, bitflip=4] Total number of successful memtester runs: 33  Best luminance at the height 0.5 is above 0x201111, score = 0.386 Best luminance at the height 1.0 is above 0x201111, score = 0.215 Best luminance at the height 2.0 is above 0x201111, score = 0.118 Best luminance at the height 4.0 is above 0x201111, score = 0.068  Read errors per lane: [0, 0, 0, 0]. Lane 3 is the most noisy/problematic. Write errors per lane: [0, 0, 24, 0]. Lane 1 is the most noisy/problematic. pcDuino2 with HYNIX DDR3 @408MHz (reboot state #2) - mildly unreliable   dcdc3_vol        = 1250 dram_clk          = 408 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b96900) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=45, bitflip=14] Total number of successful memtester runs: 354  Best luminance at the height 0.5 is above 0x201111, score = 0.836 Best luminance at the height 1.0 is above 0x181111, score = 0.763 Best luminance at the height 2.0 is above 0x181111, score = 0.669 Best luminance at the height 4.0 is above 0x181111, score = 0.553  Read errors per lane: [1, 0, 7, 0]. Lane 1 is the most noisy/problematic. Errors from the lane 3 are 100.0% eclipsed by the worst lane 1. Write errors per lane: [0, 10, 42, 0]. Lane 1 is the most noisy/problematic. Errors from the lane 2 are not intersecting with the errors from the worst lane 1. pcDuino2 with HYNIX DDR3 @408MHz (reboot state #3) - mildly unreliable   dcdc3_vol        = 1250 dram_clk          = 408 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b96900) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x06050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=35, bitflip=20] Total number of successful memtester runs: 383  Best luminance at the height 0.5 is above 0x181111, score = 0.857 Best luminance at the height 1.0 is above 0x181111, score = 0.792 Best luminance at the height 2.0 is above 0x181111, score = 0.703 Best luminance at the height 4.0 is above 0x181111, score = 0.589  Read errors per lane: [0, 0, 11, 0]. Lane 1 is the most noisy/problematic. Write errors per lane: [0, 11, 33, 1]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 1. Errors from the lane 2 are not intersecting with the errors from the worst lane 1.