User:Wens

timer_init
Used for mdelay & udelay


 * Enable AVS (A/V sync) clock
 * Setup AVS timer
 * Enable AVS counter 0 & 1
 * divider = 0xC2ee0
 * reset AVS counters

config_pll1_para
nothing for A80

set_vldo_for_pll
nothing for A80

disable_cpus
nothing for A80

PLL config

 * PLL12 (Peripheral 1) = 1200 MHz
 * PLL1 (CPU cluster 0) = 408 MHz
 * PLL2 (CPU cluster 1) = 408 MHz
 * PLL4 (Peripheral 0) = 960 MHz
 * DMB / ISB
 * AXI0 & ATB0 divider = /2 & /2
 * AHB0 = PLL4 / 8 = 120 MHz
 * AHB0 divider = /8
 * Clock AHB0 from PLL4
 * AHB1 = PLL4 / 4 = 240 MHz
 * AHB1 divider = /4
 * Clock AHB1 from PLL12
 * AHB2 = PLL4 / 8 = 120 MHz
 * AHB2 divider = /8
 * Clock AHB2 from PLL4
 * APB0 = PLL4 / 8 = 120 MHz
 * APB0 divider = /8
 * Clock APB0 from PLL4
 * APB1 = OSC24M = 24 MHz
 * APB1 divider = /1
 * Clock APB1 from OSC24M
 * Default
 * GTBUS = PLL12 / 3 = 400 MHz
 * GTBUS divider = /3
 * Clock GTBUS from PLL12
 * CCI400 = PLL4 / 2 = 480 MHz
 * CCI400 divider = /2
 * Clock CCI400 from PLL4
 * udelay(100)
 * DMB / ISB
 * Clock Cluster 0 from PLL1
 * Clock Cluster 1 from PLL2
 * udelay(100)
 * DMB / ISB


 * Enable clock gate for PIO
 * Enable clock gate for R_PIO
 * Enable clock gate and deassert reset control for DMA
 * Enable timestamp (for arch timer)

set_pll_bias

 * for all 12 PLLs
 * PLL_BIAS_CURRENT = 0x04

gtbus_init
undocumented registers


 * GT_MST_READ_PROI_CFG_REG0 = 0xff0
 * GT_MST_CFG_REG(4 ~ 11) = 0x3fffffff

clear_ZI
Clear DRAM for image loading

bias_calibration
nothing for A80

UART console
standard stuff

Hardware I have

 * A10
 * Cubietech Cubieboard


 * A13
 * HSG H702 (I broke my UART rx pad/pin)


 * A20
 * Cubietech Cubieboard2
 * Cubietech Cubietruck


 * A23
 * Ippo q8h v5


 * A31
 * Merrii Hummingbird A31


 * A31s
 * Sinlinx SinA31s
 * MSI Primo81


 * A33
 * Sinlinx SinA33
 * Ippo q8h v1.5


 * A80
 * Merrii A80 Optimus Board
 * Cubietech Cubieboard4


 * A83T / H8
 * Allwinner A83TDevBoard
 * Cubietech Cubietruck Plus


 * H3
 * Orange Pi PC

A80 Optimus
The A80 Optimus Board currently refuses to boot from mmc0. Sometimes boot0 is stuck at initializing mmc0, and sometimes the BROM fails to detect the card in mmc0 altogether.

HELLO! BOOT0 is starting! boot0 version : 3.1.0 rtc 1 value 0x00010000 rtc 2 value 0x00020000 rtc 3 value 0x00030000 INFO: dram code V2.2 dram clk=672 dram_zq = 0x0x003f3fdd!! DDR3 used!! dram channle 2 0x0x00100001 0x0x00100001 pmu id=0x00000062 VTC Disabled!! Channel 0 OK! VTC Disabled!! Channel 1 OK! dram size=2048MBytes! dram size =2048 card boot number = 0 card no is 0 sdcard 0 line count 0 [mmc]: mmc driver ver 2014-06-05 14:18 [mmc]: ***Try SD card 0*** [mmc]: mmc 0 cmd 8 timeout, err 0x00000002 [mmc]: mmc 0 cmd 8 err 0x00000002 [mmc]: mmc 0 send if cond failed [mmc]: mmc 0 cmd 55 timeout, err 0x00000002 [mmc]: mmc 0 cmd 55 err 0x00000002 [mmc]: mmc 0 send app cmd failed [mmc]: ***Try MMC card 0*** [mmc]: mmc 0 cmd 1 timeout, err 0x00000002 [mmc]: mmc 0 cmd 1 err 0x00000002 [mmc]: mmc 0 send op cond failed [mmc]: mmc 0 Card did not respond to voltage select! [mmc]: ***SD/MMC 0 init error!!!*** [mmc]: mmc 0 register failed Fail in Init sdmmc. Ready to disable icache. Jump to Fel.

FEL mode
A80 FEL requires the bulk receive endpoint to be changed from 0x82 to 0x81. Patches for this have been merged into sunxi-tools. Please make sure you have the latest version.

To use FEL mode, make sure you have the patched FEL mode boot0 (fes1.fex) and u-boot (u-boot.fex) binaries. You can find them here

How to boot from fel using Allwinner's boot0 and u-boot: cat zImage sun9i-a80-optimus.dtb > zImage-dtb

mkimage -A arm -O linux -C none -T kernel -a 0x20008000 -e 0x20008000 -n Linux -d zImage-dtb uImage

FEL=../sunxi-tools/fel

${FEL} write 0x12000 fes1.fex ${FEL} exe 0x12000 ${FEL} write 0x2a000000 u-boot.fex ${FEL} write 0x24000000 uImage ${FEL} write 0x2c000000 rootfs.img ${FEL} exe 0x2a000500
 * 1) Load boot0
 * 1) Run boot0
 * 1) Load u-boot
 * 1) Load kernel
 * 1) Load ramdisk
 * 1) Run u-boot (Allwinner's u-boot has a header in the front)

u-boot commands setenv bootargs console=ttyS0,115200n8 earlycon=uart,mmio32,0x07000000 debug loglevel=8 root=/dev/mmcblk0p1 rootwait mem=2G bootm 0x24000000 0x2c000000

SD UHS-1 / DDR and eMMC high speed modes
Mainline sunxi-mmc does not know how to do bus speeds over 50 MHz SDR. This translates to 25 MB/s for 4-bit SD cards.

What is required is a combination of DDR mode (only this is needed if running HSDDR for eMMC) and signaling voltage change support.

A few things need to happen:


 * 1) Teach sunxi-mmc DDR mode
 * 2) Teach sunxi-mmc about vqmmc
 * 3) enabling/disabling it
 * 4) setting regulator voltage
 * 5) * This might need support for PIO/R_PIO pin bias voltage setting
 * 6) Implement start_voltage_change