Clock Control Module

= Clock Control Module =

Overview
Allwinner's A10 has 10 timing or clock sources. 7 Phase Locking Loop's (PLL's), a 24MHz main crystal oscillator, an RC based internal on chip based oscillator and a low-power 32kHz crystal oscillator.

The 24MHz crystal oscillator is mandatory and is responsible for supplying a clock source for the PLL. The 32kHz crystal oscillator is connected only to the RTC to ensure proper time is kept.

Clock generation
All PLL's are fed from the 24 MHz reference clock.

Timer Registers
Timer Base address: 0x01c20000

CCM_PLL1_CFG
Default value: 0x21005000

Offset: 0x0000

CCM_PLL1_TUN
Default value: unknown

Offset: 0x0004

CCM_PLL2_CFG
Default value: 0x81000010

Offset: 0x0008

CCM_PLL2_TUN
Default value: 0x00000000

Offset: 0x000c

CCM_PLL3_CFG
Default value: 0x0010d063

Offset: 0x0010

CCM_PLL4_CFG
Default value: 0x21081000

Offset: 0x0018

= ref = https://github.com/hno/uboot-allwinner/blob/lichee/lichee-dev-mmc/arch/arm/include/asm/arch-sunxi/clock.h https://github.com/amery/linux-allwinner/blob/allwinner-v3.0-android-v2/arch/arm/mach-sun4i/include/mach/ccmu_regs.h