LinkSprite pcDuino2

The pcDuino2 is an A10 based development board with Arduino compatible headers. Unlike many other A10 based boards, this one does not have a SATA connector.

= Identification =

On the back of the board, it helpfully says "pcDuino V2".

= Sunxi support =

Current status
Fully supported.

Manual build

 * For building u-boot, use the pcDuino target.
 * The .fex file can be found in sunxi-boards as linksprite_pcduino2.fex

Everything else is the same as the manual build howto.

Mainline U-Boot
For building mainline u-boot, use the Linksprite_pcDuino board name.

Mainline kernel
Use the sun4i-a10-pcduino.dts device-tree file for the mainline kernel.

= Tips, Tricks, Caveats =

FEL mode
The UPGRADE (SW2, near the HDMI connector) button triggers FEL mode.

LEDs
The board has 5 green LEDs. One of them is an always-on power indicator. Two LEDs labelled TX and RX are accessible via GPIO (using the PH15 and PH16 pins). One LED labelled CLK is connected to the PI11 pin, which can also have a dedicated use as SPI0_CLK. So this CLK LED serves either as an SPI activity indicator or just as an ordinary LED if no SPI hardware is connected. And there is also one more WIFI LED on the board, which is connected to the WIFI chip.

DRAM
This board uses four x8 DDR3 chips (two on the front side of the PCB and two on the back side). So far SKhynix and NANYA chips have been encountered. SKhynix has reliability problems at clock speeds higher than 360MHz. Preliminary tests show that NANYA appears to be reasonably good and at least works without problems at the default 408MHz settings from the vendor.

Below are the a10-tpr3-scan results with the default U-Boot settings, just after setting the DRAM clock frequency a little bit too high. The a10-tpr3-scan tool suggests to change the tpr3 value to 0x181111 for HYNIX and to 0x041111 for NANYA. Basically, the delay settings need to be changed in different directions for improving reliability. The HYNIX settings are bad for NANYA and the other way around. The default tpr3 value 0x000000 happens to be on the edge of the reliable/unreliable boundary in both cases.

a10-tpr3-scan results from pcDuino2 with HYNIX DDR3 @408MHz


  dcdc3_vol        = 1250 dram_clk          = 408 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b96900) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x06050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [solidbits=35, bitflip=20] Total number of successful memtester runs: 383  Best luminance at the height 0.5 is above 0x181111, score = 0.857 Best luminance at the height 1.0 is above 0x181111, score = 0.792 Best luminance at the height 2.0 is above 0x181111, score = 0.703 Best luminance at the height 4.0 is above 0x181111, score = 0.589  Read errors per lane: [0, 0, 11, 0]. Lane 1 is the most noisy/problematic. Write errors per lane: [0, 11, 33, 1]. Lane 1 is the most noisy/problematic. Errors from the lane 0 are not intersecting with the errors from the worst lane 1. Errors from the lane 2 are not intersecting with the errors from the worst lane 1.

a10-tpr3-scan results from pcDuino2 with NANYA DDR3 @432MHz


  dcdc3_vol        = 1250 dram_clk          = 432 mbus_clk          = 0 dram_type         = 3 dram_rank_num     = 1 dram_chip_density = 4096 dram_io_width     = 16 dram_bus_width    = 32 dram_cas          = 6 dram_zq           = 0x7b (0x6b91800) dram_odt_en       = 0 dram_tpr0         = 0x30926692 dram_tpr1         = 0x1090 dram_tpr2         = 0x1a0c8 dram_tpr3         = 0x0 dram_emr1         = 0x0 dram_emr2         = 0x0 dram_emr3         = 0x0 dqs_gating_delay  = 0x05050505 active_windowing  = 0 Lane phase adjustments: [0, 0, 0, 0] Error statistics from memtester: [bitflip=36, solidbits=9] Total number of successful memtester runs: 456  Best luminance at the height 0.5 is above 0x041111, score = 0.894 Best luminance at the height 1.0 is above 0x041111, score = 0.844 Best luminance at the height 2.0 is above 0x041111, score = 0.770 Best luminance at the height 4.0 is above 0x031111, score = 0.668  Read errors per lane: [0, 6, 0, 0]. Lane 2 is the most noisy/problematic. Write errors per lane: [1, 32, 6, 16]. Lane 2 is the most noisy/problematic. Errors from the lane 0 are 56.2% eclipsed by the worst lane 2. Errors from the lane 1 are 66.7% eclipsed by the worst lane 2. Errors from the lane 3 are 100.0% eclipsed by the worst lane 2.

Arduino shields compatibility


The advertised compatibility with Arduino shields is not always perfect.

= Adding a serial port =



There is 2.54mm pitch header next to the Wifi Module, labelled "UART". All you need to do is connect some jumper wires according to our UART howto.

= Pictures =

= Also known as =

This type of device has no rebadges.

= See also =
 * LinkSprite pcDuino
 * LinkSprite pcDuino3
 * User Guide.
 * Schematics (2013-09-17)