DRAM Controller

Two different families of DRAM controllers exist:

sun4i (Allwinner A10), sun5i (Allwinner A13) and sun7i (Allwinner A20) hardware
No accurate documentation for this particular DRAM controller exists in public access. But it is suspected that Allwinner uses one of the revisions of Synopsys DesignWare DDR2/3-Lite Memory Controller IP (MCTL) combined with DDR2/3-Lite PHY IP in A10/A13/A20. Also this DRAM controller apparently has siblings in Rockchip RK29XX, RK30XX and TI KeyStone2 hardware, which have some documentation and some bits of kernel and bootloader sources available in the Internet. Not to mention the original Allwinner boot0 bootloader sources and the suspend support code from the linux-sunxi kernel. This provides enough hints for finding out how the DRAM controller actually works by checking various bits of information via the trial and error method.

As a result, we have a reasonably usable reconstructed A10 DRAM Controller Register Guide.

sun6i (Allwinner A31) and sun8i (Allwinner A23) hardware
A31 DRAM Controller Register Guide