DE2 Register Guide

= DE2 register guide =

Overview
Although DE2 is listed as a single block in the datasheet, it in fact contains several sub-blocks.

Documentation
- 147 pages, 2.9MB, 18-01-2018

Sections
Most SoCs position DE2 at 0x01000000 (A64/H3/H5), but it may also be on a different address.

DE2_CCU_DIV
The real division value is the value in the register part + 1.

Mixer
Main mixer property is the number of supported video and UI channels. If the SoC has multiple mixers, they usually support different number of channels and first supports more channels than the second. Video channels support YUV planes and UI channels support RGB planes. Another important mixer property is maximum plane size. The exact number of supported channels of either kind and max. plane size can be found in BSP code in de_feat.[c|h] files. vi - number of video channels ui - number of UI channels

GLB_CTL_REG
Note: Only mixer enable and writeback port bits are used in BSP code.

GLB_STATUS_REG
Note: This register is not used in BSP code.

GLB_SIZE_REG
Sets mixer output size, should match width and height set in TCON and HDMI (if used).

Blender
First enabled channel correlates to first enabled pipe and so on. To simplify things, it can be always tought as 1:1 mapping, even if channels are not used in order. Most notably, video channel is often unused, so it is ok to enable first UI channel and second pipe (when SoC have only one video channel, which is very common).

BLD_PIPE_CTL
Note: Enabling pipe's fill color does nothing if pipe is not enabled.