DDR3

This page is an attempt to collect all the information about the various DDR3 chips in use on Sunxi hardware.

= DDR3 configuration in u-boot =

JEDEC speed bin
Sunxi devices typically use DRAM clock speeds not exceeding 533MHz, which means that the JEDEC DDR3-1066F speed bin is the most common set of timings that they are expected to be targeting for. The DDR3-1333 and DDR3-1600 chips, which are rated for higher clock speeds, may or may not support down binning to DDR3-1066F (this information has to be checked in the datasheets). That's because the DDR3-1066F compatible chips need to support 13.125 ns timings for tRP/tRCD, while the DDR3-1333H chips are only required to support 13.5 ns. So the DDR3-1066F speed bin has a bit tighter timings than DDR3-1333H. This difference between 13.125 ns and 13.5 ns is relatively important, because when the delays are converted from nanoseconds to cycles and rounded up, it is a matter of having 7 cycles delay instead of 8!

It is quite common to have DDR3-1333H or DDR3-1600K chips, which support DDR3-1066F timings too. This may look like an explicit note "backward compatible to 1066 CL-7" in the datasheets of such chips. Or the tRP/tRCD timing information may be sometimes specified as "13.5 (13.125) ns" in the table.

The u-boot *_defconfig file for an Allwinner A10/A13/A20 device may use the following configuration option to indicate that the DRAM chip is in fact compatible with DDR3-1066F timings (and with DDR3-1333H for the DRAM clock speeds >533MHz): +S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y

In the unlikely case if the DDR3-1066F speed bin is not supported by the DRAM chip, a slower DDR3-1066G speed bin has to be assumed.

= Manufacturers =

N2CB2G80GN-CG
DDR3-1333H (supports down binning to DDR3-1066F), x8, density: 2G, page size: 1K

Datasheet: http://www.elixir-memory.com/products/file/elixir-ddr3-2gb-g-die-r10.pdf

GT8UB256M16BP-BG
DDR3-1333H, x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: https://github.com/SoM-Boards/SoM-allwinnerA10/blob/master/docs/GT-DDR3-4Gbit-B-DIE-x8%20x16.pdf

GT8UB256M16BP-BH
DDR3-1600K (supports down binning to DDR3-1066F), x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: https://github.com/SoM-Boards/SoM-allwinnerA10/blob/master/docs/GT-DDR3-4Gbit-B-DIE-x8%20x16.pdf

GT8UB512M8EN-BG
DDR3-1333H, x8, density: 4G, page size: 1K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: https://github.com/SoM-Boards/SoM-allwinnerA10/blob/master/docs/GT-DDR3-4Gbit-B-DIE-x8%20x16.pdf

MEM4G16D3EABG-125
DDR3-1600K (supports down binning to DDR3-1066F), x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: http://www.memphis.ag/fileadmin/datasheets/MEM4G16D3EABG_10.pdf

MT41J256M16HA-125
DDR3-1600K (supports down binning to DDR3-1066F), x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: http://www.micron.com/~/media/documents/products/data-sheet/dram/ddr3/4gb_ddr3_sdram.pdf

NT5CB256M16BP-DI
DDR3-1600K (supports down binning to DDR3-1066F), x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: http://www.nanya.com/NanyaAdmin/GetFiles.ashx?ID=1109

NT5CB256M8DN-CG
DDR3-1333H (supports down binning to DDR3-1066F), x8, density: 2G, page size: 1K

Datasheet: http://www.nanya.com/NanyaAdmin/GetFiles.ashx?ID=923

H5TQ1G83TFR-H9C
DDR3-1333H (supports down binning to DDR3-1066F), x8, density: 1G, page size: 1K

Datasheet: http://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/DDR3_H5TQ1G(4_8)3TFR(Rev1.1).pdf

H5TQ2G63BFR-H9C
DDR3-1333H (supports down binning to DDR3-1066F), x16, density: 2G, page size: 2K

Datasheet: http://hands.com/~lkcl/H5TQ2G63BFR.pdf

H5TQ2G83CFR-H9C
DDR3-1333H (supports down binning to DDR3-1066F), x8, density: 2G, page size: 1K

Datasheet: https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3_H5TQ2G4(8)3CFR(Rev1.0).pdf

H5TQ4G63AFR-PBC
DDR3-1600K (supports down binning to DDR3-1066F), x16, density: 4G, page size: 2K, tRFC: 260ns (lower than JEDEC default 300ns)

Datasheet: https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Consumer_DDR3_H5TQ4G8(6)3AFR(Rev1.1)_130130.pdf

256X8DDR3 HL 1320
= Useful information =


 * 1) The "DDR3 Device Operation" document from SK Hynix contains a lot of copy/paste information from the DDR3 spec.
 * 2) "A DRAM Refresh Tutorial" blog post jointly authored by Rajeev Balasubramonian (University of Utah), Manju Shevgoor (University of Utah), and Jung-Sik Kim (Samsung).