MediaWiki API result

{
    "batchcomplete": "",
    "continue": {
        "gapcontinue": "Remote_Reboot_Jig",
        "continue": "gapcontinue||"
    },
    "warnings": {
        "main": {
            "*": "Subscribe to the mediawiki-api-announce mailing list at <https://lists.wikimedia.org/mailman/listinfo/mediawiki-api-announce> for notice of API deprecations and breaking changes."
        },
        "revisions": {
            "*": "Because \"rvslots\" was not specified, a legacy format has been used for the output. This format is deprecated, and in the future the new format will always be used."
        }
    },
    "query": {
        "pages": {
            "1093": {
                "pageid": 1093,
                "ns": 0,
                "title": "Reduced Serial Bus",
                "revisions": [
                    {
                        "contentformat": "text/x-wiki",
                        "contentmodel": "wikitext",
                        "*": "The RSB<sup>TM</sup> is a push-pull two wire bus developed by Allwinner Technology. Its primary (only?) use is to connect an (Allwinner) SoC to an\nAXP-series power management controller (PMIC) from X-Powers.\n\n= Features =\n* Related to the SMBus, which in turn is derived from I\u00b2C.\n* Connects to the SoC-internal AMBA Peripheral Bus (APB).\n* Supports speeds up to 20 MHz (in contrast to the 400 KHz of I\u00b2C).\n* Supports multiple devices, although most (all?) boards connect the pins to the only on-board PMIC.\n* Multiplexed with some I\u00b2C pins (allows driving slaves with I\u00b2C for compatibility).\n* Supports programmable output delay of CD signal.\n* Supports parity check for address and data transmission.\n* Included in [[A23]], [[A33]], [[A80]], [[A83T]], [[H3]](?) and [[A64]] SoCs.\n\n= Documentation =\nThe RSB is briefly mentioned (along with MMIO address and IRQ number) in the A23, A33 and A64 manuals, but explained in more detail (including a register description) in the A80 and A83 manuals.\n\n= Registers =\nThis list was originally gained from Allwinner code, but was later extended with the help of the manuals.\n\n== Register list ==\n{| class=\"wikitable\"\n|-\n! Offset !! Name   !! Description\n|-\n|   0x00 || CTRL   || Control\n|-\n|   0x04 || CCR    || Clock control\n|-\n|   0x08 || INTE   || Interrupt enable\n|-\n|   0x0C || STAT   || Interrupt status (write 1 to clear)\n|-\n|   0x10 || DADDR0 || Register address within the slave\n|-\n|   0x14 || DADDR1 ||\n|-\n|   0x18 || DLEN   || (Not sure if this exists)\n|-\n|   0x1C || DATA0  || Up to four data bytes\n|-\n|   0x20 || DATA1  ||\n|-\n|   0x24 || LCR    || Line control register\n|-\n|   0x28 || PMCR   || PMIC init register\n|-\n|   0x2C || CMD    || Command for next transaction\n|-\n|   0x30 || SADDR  || Slave address\n|}\n\nThe DLEN register seems to be hardwired to 0 in most recent implementations and is redundant with the CMD register. According to documentation it holds the transfer length (1, 2 or 4 Bytes) in the lower two bits and the read(=1)/write(=0) indicator in bit 4.\n\n== CTRL ==\n\n{| class=\"wikitable\"\n|-\n! Bit !! Name !! Description !! Value !! R/W !! Default\n|-\n| 31-9 || Reserved\n|-\n| 8 || USE_RSB || Use RSB interface ||  || RW || 0\n|-\n| 7 || START_TRANS || Start transfer || write 1 to start current transfer, resets to 0 when done || RW || 0\n|-\n| 6 || ABT_TRANS || Abort transfer || write 1 to abort current transfer, resets to 0 when done || RW || 0\n|-\n| 5-2 || Reserverd\n|-\n| 1 || GLB_INTEN || Enable interrupts || 1: enable || RW || 0\n|-\n| 0 || SOFT_RESET || Reset RSB controller, resets to 0 when done || write 1 to reset || RW || 0\n|}\n\n== CCR ==\nThis register controls the RSB bus clock (SCK) speed.\n\n{| class=\"wikitable\"\n|-\n! Bit !! Name !! Description !! Value !! R/W !! Default\n|-\n| 31-9 || Reserved\n|-\n| 8 || CD_ODLY || ?? || cd_odly = !(div >> 1) || RW ||\n|-\n| 7-0 || DIV || Clock divider || SCK = SRC / 2 / (DIV + 1) || RW ||\n|}\n\nThe reference clock is the 24 MHz oscillator, a common speed on most boards seems to be 3 MHz, so 0x103 is the value you most probably want to write into this register.\n\n== INTE ==\nThis register masks/unmasks interrupt events.\n\n{| class=\"wikitable\"\n|-\n! Bit !! Name !! Description !! R/W !! Default\n|-\n| 31-3 || Reserved\n|-\n| 2 || LBSY || Load busy (transfer in progress) || RW\n|-\n| 1 || TERR || Transfer error encountered || RW\n|-\n| 0 || TOVER || Transfer over (completed) || RW\n|}\n\n== STATUS ==\nThis register shows interrupt and transfer status.\nWrite 1 to the corresponding bit to clear each interrupt.\n\n{| class=\"wikitable\"\n|-\n! Bit !! Name !! Description !! R/W !! Default\n|-\n| 31-24 || Reserved\n|-\n| 23-16 || TRANS_ERR_ID || Transfer error ID for transfer 0 || RW\n|-\n| 15-8 || TRANS_ERR_ID || Transfer error ID for transfer 0 || RW\n|-\n| 2 || LBSY || Load busy (transfer in progress) || RW\n|-\n| 1 || TERR || Transfer error encountered || RW\n|-\n| 0 || TOVER || Transfer over (completed) || RW\n|}\n\n=== Transfer error codes ===\n{| class=\"wikitable\"\n|-\n! Bit !! Description\n|-\n| 15-9 || Reserved\n|-\n| 8 || No ACK when setting run-time slave address\n|-\n| 7-4 || Reserved\n|-\n| 3 || Error happened with the transmission of the 4th byte of data\n|-\n| 2 || Error happened with the transmission of the 3th byte of data\n|-\n| 1 || Error happened with the transmission of the 2th byte of data\n|-\n| 0 || Error happened with the transmission of the 1th byte of data\n|}\n\n== LCR ==\nThis register can seemingly be used to bit bang the bus.\n\n== PMCR ==\nEducated guess: This register can be used to switch a PMIC from its reset-state configured I2C interface to RSB mode. This avoids configuring the pins to I2C and sending the switch sequence via standard I2C.\n\n== CMD ==\nList of command codes\n\n{| class=\"wikitable\"\n|-\n! Name !! Value !! Description\n|-\n| WR8 || 0x4E || Write byte\n|-\n| WR16 || 0x59 || Write half word\n|-\n| WR32 || 0x63 || Write word\n|-\n| RD8 || 0x8B || Read byte\n|-\n| RD16 || 0x9C || Read half word\n|-\n| RD32 || 0xA6 || Read word\n|-\n| SRTA || 0xE8 || Set run-time address\n|}\n\n== SADDR ==\nThis register is used with the SRTA command to connect a hardware address to a runtime address.\n\n{| class=\"wikitable\"\n|-\n! Bit !! Description\n|-\n| 23-16 || Run-Time Slave Address\n|-\n| 15-0 || Hardware Slave Address\n|-\n|}\n\n= Hardware Addresses =\nRSB has hardware addresses and runtime addresses. Runtime addresses are configured at initialization time,\nand are used to talk to the slave devices. Hardware addresses are used to identify and configure runtime addresses.\nThe configured runtime addresses are not queryable.\n\nAllwinner sources use a static mapping of hardware and runtime addresses.\n\n{| class=\"wikitable\"\n|-\n! Hardware Address !! (Static) Runtime Address !! Known Devices\n|-\n| 0x3a3 || 0x2d || AXP223, AXP809, AXP81X\n|-\n| 0x745 || 0x3a || AXP806\n|-\n| 0x3a3 || 0x2d || [[AXP803]]\n|-\n| 0xe89 || 0x4e || AC100\n|}\n\nIn contrast to the AXP 803 manual, the hardware address for it seems to be 0x3a3 instead of the documented 0x1d1.\n\n= Example transactions =\nFor setting up the RSB controller in the first place, you have to:\n* Configure the associated pins to connect to the RSB controller (Port Controller CPUs)\n* Configure the pins to be Pull-up level 2 drive strength (same Port Controller CPUs)\n* Un-gate the RSB clock (bit 3 in the APB0_CLK_GATING_REG (offset 0x28) in the R_PRCM block)\n* De-assert the RSB reset line (bit 3 in the APB0_SOFT_RST_REG (offset 0xB0) in the R_PRCM block)\n* Program the clock (CCR register) in the RSB block (1 cycle delay, 3 MHz)\n* Soft reset the RSB block (bit 0 in CTRL register)\n\nAfter having setup the RSB block, a typical read transaction may look like:\n writel(rt_addr << 16, RSB_BASE + 0x30); /* set run-time address of slave */\n writel(0x8b, RSB_BASE + 0x2c);          /* \"Read-one-byte\" command into CMD register */\n writel(regnr, RSB_BASE + 0x10);         /* set register to be read */\n writel(0x80, RSB_BASE + 0x00);          /* start transaction */\n while (readl(RSB_BASE + 0x00) & 0x80)   /* poll for completion */\n         ;\n ret = readl(RSB_BASE + 0x0c);           /* read status register */\n if (ret == 0x01)                        /* transaction completed without errors */\n         return 0;\n return ret;\n\n[[Category:Hardware]]"
                    }
                ]
            },
            "953": {
                "pageid": 953,
                "ns": 0,
                "title": "Register-mediawiki-extension",
                "revisions": [
                    {
                        "contentformat": "text/x-wiki",
                        "contentmodel": "wikitext",
                        "*": "__NOTOC__\nWish page for a mediawiki extension to make easy editing and generate pretty register descriptions, together with the possibility of export in a machine friendly format.\n\n==== similar ====\nFrom previous discussions:\n* [https://github.com/kjmkznr/blockdiag-mediawiki-extension blockdiag-mediawiki-extension]\n* [http://blockdiag.com/en/nwdiag/packetdiag-examples.html packetdiag-examples]\n\nLaTeX packages:\n* [ftp://ctan.tug.org/pub/tex/macros/latex/contrib/register/register.pdf Register diagrams with field descriptions]\n* [http://texdoc.net/texmf-dist/doc/latex/bytefield/bytefield.pdf The bytefield package]\n\n==== disadvantages ====\nSomeone has to write it, be a maintainer.\n\n==== alternatives ====\n* Use mediawiki templates. <br/> Have two forms of arguments named/unnamed(indexed by number). Named arguments strip the start and end spaces. Unnamed, the '=' character transform in a named argument.\n* [http://www.mediawiki.org/wiki/Scribunto Scribunto - embed lua scripting] <br/> Page => Template => Module. Uses the same argument parsing rules as templates, with the same limitations.\n\n==== format ====\nShould be easy to edit, should be easy to write the extension's parser.\n <register>\n   ?\n </register>\n\n==== render ====\n== SRAM_CTL0_CFG ==\n{| style=\"table-layout:fixed; border-collapse:collapse; border-spacing:0; padding:0; text-align:center;\" width=100%\n|- style=\"vertical-align:bottom; font-size:7pt; height: 20px;\"\n|width=3.125%|    ||width=3.125%| 30 ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|\n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|  \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|\n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|   \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%| 0\n|- style=\"font-size:12pt;\"\n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan=31 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt>SRAM_C1_MAP</tt>\n|}\n{{REG|SRAM_CTL0_CFG|offset=0x0000|\n{{REG/FIELD|30:0|SRAM_C1_MAP|default=0x7fffffff\n|values=<pre>\n 0 = CPU/DMA\n 1 = VE\n</pre>\n|description=\nEach bit represents a page to be mapped to the CPU/DMA unit or to the VE. Each bit (combination) may represent a byte/page of sram C1\n}}\n}}\n\n== SRAM_CTL1_CFG ==\n{| style=\"table-layout:fixed; border-collapse:collapse; border-spacing:0; padding:0; text-align:center;\" width=100%\n|- style=\"vertical-align:bottom; font-size:7pt; height: 20px;\"\n|width=3.125%| 31 ||width=3.125%|    ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%|    \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%| \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|    ||width=3.125%| 12 \n|width=3.125%|    ||width=3.125%|    ||width=3.125%|  9 ||width=3.125%|  8\n|width=3.125%|    ||width=3.125%|    ||width=3.125%|  5 ||width=3.125%|  4 \n|width=3.125%|    ||width=3.125%|  2 ||width=3.125%|    ||width=3.125%|  0\n|- style=\"font-size:12pt;\"\n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n| colspan=18 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n| colspan= 2 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan= 2 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n| colspan= 2 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan= 2 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center; color:#aaa; background-color:#eee;\"| \n| colspan= 1 style=\"height: 70px; border: 2px solid #888;text-align:center;\"| <tt></tt>\n|}\n{{REG|SRAM_CTL1_CFG|offset=0x0004|\n{{REG/FIELD|31|SRAM_BIST_DMA_CTL|default=0b0\n|values=<pre>\n 0 = DMA\n 1 = BIST\n</pre>\n|description=Normal DMA or BIST control (build in self test)\n}}\n{{REG/FIELD|12|SRAM_C3_MAP|default=0b1\n|values=<pre>\n 0 = CPU/BIST\n 1 = ISP\n</pre>\n|description=Map SRAM C3 to either the CPU/BIST unit or to ISP\n}}\n{{REG/FIELD|9:8|SRAM_C2_MAP|default=0b11\n|values=<pre>\n 00 = CPU/BIST\n 01 = AE\n 10 = CE\n 11 = ACE\n</pre>\n|description=Map SRAM C2 to either the CPU/BIST unit or to the AE or to the CE or to the ACE\n}}\n{{REG/FIELD|5:4|SRAM_A3_A4_MAP|default=0b00\n|values=<pre>\n 00 = CPU/DMA\n 01 = EMAC\n 10 = no operation\n 11 = no operation\n</pre>\n|description=Map SRAM A3 and A4 to either the CPU/DMA unit or to EMAC\n}}\n{{REG/FIELD|2|SRAM_|default=0b0\n|values=<pre>\n 0 = ?\n 1 = ?\n</pre>\n|description=EMAC at the least changes this.A20 have this set by default\n}}\n{{REG/FIELD|0|SRAM_D_MAP|default=0b0\n|values=<pre>\n 0 = CPU/DMA\n 1 = USB0\n</pre>\n|description=Map SRAM D to either the CPU/DMA unit or to USB0\n}}\n}}"
                    }
                ]
            }
        }
    }
}