https://linux-sunxi.org/api.php?action=feedcontributions&user=Olecom&feedformat=atomlinux-sunxi.org - User contributions [en]2024-03-28T18:46:52ZUser contributionsMediaWiki 1.35.8https://linux-sunxi.org/index.php?title=Olimex_A20-OLinuXino-Lime2&diff=23147Olimex A20-OLinuXino-Lime22020-02-26T12:19:03Z<p>Olecom: delete dup</p>
<hr />
<div>{{Infobox Board<br />
| image = [[File:Lime2_top.jpg|250px]]<br />
| manufacturer = [https://www.olimex.com/ Olimex]<br />
| dimensions = 84''mm'' x 60''mm'' x 20''mm''<br />
| release_date = September 2014<br />
| website = [https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2 Device Product Page]<br />
| soc = [[A20]] @ 1Ghz<br />
| dram = 1GiB DDR3 @ 480MHz<br />
| nand = 4GB (optional)<br />
| emmc = 4GB (optional)<br />
| power = DC 5V ([https://www.olimex.com/wiki/PWRJACK 5.5/2.1 jack]), 3.7V LiPo (JST PHR-2 header)<br />
| video = HDMI (Type A, full)<br />
| network = 10/100/1000Mbps Ethernet ([[Ethernet#Realtek_RTL8211CL|Realtek RTL8211CL]])<br />
| storage = µSD, SATA<br />
| usb = 2x USB2.0 Host, 1x mini USB2.0 OTG<br />
| headers = UART, 5x GPIO headers<br />
}}<br />
<br />
The [https://www.olimex.com/wiki/A20-OLinuXino-LIME2 A20 Olinuxino LIME2] is an [[OSHW]] board produced by [[Olimex]].<br />
<br />
The A20-OLinuXino-LIME2 is an upgrade of the [[Olimex A20-OLinuXino-Lime]], but it comes with 1GiB RAM and gigabit ethernet. There are also two extra variants with onboard storage: [https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2-4GB A20-OLinuXIno-LIME2-4GB] with 4GB NAND and [https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC A20-OLinuXino-LIME2-eMMC] with 4GB eMMC.<br />
<br />
= Identification =<br />
<br />
The board is marked as ''A20-OLinuXino-Lime'' on both the top and bottom of the PCB.<br />
<br />
Note that it is not marked as Lime2. The Lime2 variant can be distinguished by the presence of two dram chips on the top of the board between the SoC and the USB connectors, also the ethernet phy is on the bottom of the board instead of the top.<br />
<br />
= Sunxi support =<br />
<br />
== Current status ==<br />
<br />
Supported.<br />
* Mainline kernel patches posted to linux-arm-kernel mailing list 2014-09-28<br />
* Mainline u-boot patches posted to u-boot mailing list 2014-09-28<br />
<br />
== Manual build ==<br />
<br />
You can build things for yourself by following our [[Manual_build_howto | Manual build howto]] and by choosing from the configurations available below.<br />
<br />
=== U-Boot ===<br />
<br />
==== Sunxi/Legacy U-Boot ====<br />
<br />
Use the ''A20-OLinuXino_Lime2'' build target. ''_FEL'' version is also available for USB booting.<br />
<br />
==== Mainline U-Boot ====<br />
<br />
Use the ''A20-OLinuXino-Lime2_defconfig'' build target or ''A20-OLinuXino-Lime2-eMMC_defconfig'' if you have the eMMC version.<br />
<br />
''WARNING'' Revisions H and newer need [[an extra u-boot config]].<br />
<br />
=== Linux Kernel ===<br />
<br />
==== Sunxi/Legacy Kernel ====<br />
<br />
Use the [https://github.com/linux-sunxi/sunxi-boards/blob/master/sys_config/a20/a20-olinuxino_lime2.fex ''a20-olinuxino_lime2.fex''] file. (Please note that this fex file adopted DRAM clock setting from the Lime2's predecessor - only ''dram_tpr4'' differs for unknown reasons. Using this fex file the DRAM is clocked with just 384&nbsp;MHz, which costs some few percent performance depending on the application used.)<br />
<br />
==== Mainline kernel ====<br />
<br />
Use the ''sun7i-a20-olinuxino-lime2.dtb'' device-tree binary.<br />
<br />
[[File:Lime2_fel.jpg|thumb|240px|Recovery button]]<br />
= Tips, Tricks, Caveats =<br />
<br />
== FEL mode ==<br />
<br />
The Recovery button (under sata connector, nearest hdmi connector) triggers [[FEL | FEL mode]].<br />
<br />
[[File:Lime2_uext.jpg|thumb|240px|Lime2 UEXT connector]]<br />
<br />
== GMAC u-boot config ==<br />
<br />
From Revision H onward, the Lime2 comes with a Microchip KSZ9031 gigabit ethernet [[Ethernet#Phyceivers|phyceiver]]. These need the following line added to the u-boot config (in configs/A20-OLinuXino-Lime2_defconfig):<br />
<pre>CONFIG_GMAC_TX_DELAY=3</pre> Do not set this to another value but 3.<br />
<br />
This Microchip PHY chip is also getting significantly hotter than the old [[Ethernet#Realtek_RTL8201CP|Realtek RTL8201CP PHY]].<br />
<br />
== Expansion ports ==<br />
<br />
The internal GPIO headers appear to be mirrored compared to the original Lime boards [https://olimex.wordpress.com/2014/10/27/a20-olinuxino-lime2-review-and-updates/]. Due to this there are specific A20-OLinuXino-Lime2-UEXT adapters, however as of 2014-09-28 these do not appear to be available directly from the Olimex shop.<br />
<br />
== Booting from SPI Flash ==<br />
<br />
See the main [[Bootable_SPI_flash]] article for generic guides on how to boot from SPI flash. Included here are two pictures of a SPI NOR Flash setup with a LIME2. This requires soldering wires to 3 pads on the empty NAND socket in order to get access to the PC0,PC1,PC2 pins, which makes it more or less just a proof of concept solution. But it would be great if Olimex considers adding an on-board SPI flash to the future revisions of the A20-OLinuXino-Lime2 board just like they have recently [https://olimex.wordpress.com/2016/05/04/lime2-get-better-now-with-emmc-flash-a20-olinuxino-lime2-emmc/ done this with eMMC]. Because this can allow having SATA or network boot without any need to use an SD card for storing the U-Boot bootloader.<br />
<br />
<gallery><br />
File:A20_LIME2_with_SPI0_soldered.jpg<br />
File:A20_LIME2_with_SPI0_soldered-part-2.jpg<br />
</gallery><br />
<br />
== SATA power connector ==<br />
<br />
Unlike other sunxi boards the Olimex boards don't use the JST XH 0.1"/2.5mm header for SATA power but the smaller JST PHR-2 header normally used for connecting LiPo batteries.<br />
<br />
== Hardware reliability ==<br />
There are known cases where Lime2 boards are failing in the wild. The main suspects are DRAM clock speed and CPU core voltage. For more information see [Hardware Reliability Tests].<br />
<br />
=== DRAM clock speed limit ===<br />
DRAM is clocked at '''480 MHz''' by the hardware vendor (in fact even [https://olimex.wordpress.com/2014/10/27/a20-olinuxino-lime2-review-and-updates/ 532Mhz is mentioned in the blog]). The board uses somewhat non-standard resistors for ZQ calibration (ZQ = '''330 Ohm''', SZQ = '''330 Ohm'''), but at least they seem to be the same in Lime2 revisions from Rev.B to Rev.E according to the board schematics. Still it's best to always mention the board revision in the results table in order to avoid any surprises.<br />
<br />
=== DRAM test results ===<br />
Having done runs on a larger set of boards, initial test results looked appalling. Machines that where known to have caused trouble in the past, failed within the hour. Others kept going for a few hours actually. We did notice temperature variation influences. On a Monday, the heating in the building was broken and the ambient temperature was only 20 degrees Celsius and 3 boards ran overnight without a problem. On Wednesday the heating was fixed and the ambient temperature rose to 23 degrees Celsius and all three boards had crashed. All of the initial 6 test subjects crashed and failed at their stock 480 DRAM frequency setting!<br />
<br />
Expanding this test to influence ambient temperature, even more interesting results where found. For example, 456 Mhz seemed stable at 22 degrees Celsius, but with an ambient temperature of 50 degrees Celsius a few boards still crashed. Lowering the frequency even more, to 432 MHz stabilized that and thus the ambient temperature was increased to 70 degrees Celsius. Here the sunxi_tp_temp, which is very unreliable, reported core temperatures of about 77 degrees Celsius. The board however remained running stable at least one hour.<br />
<br />
The full tests results can be seen in this [http://dl.linux-sunxi.org/users/oliver/Lime2_memory_stability.ods sheet], and can eventually be modified into table below.<br />
<br />
{| class="wikitable"<br />
! Hardware<br />
! Diagnostic software<br />
! lima-memtester passes<br />
! lima-memtester fails<br />
! Notes<br />
|-<br />
| [[User:JohnDoe]]'s A20-OLinuXino-Lime2 Rev.? || fel-boot-lima-memtester-on-a20-lime2-v1.tar.gz || ? MHz || ? MHz || ? MHz fails after running for ? minutes<br />
|}<br />
<br />
= Adding a serial port =<br />
<br />
[[File:Lime2-uart.jpg|thumb|240px|UART connector]]<br />
<br />
There is a clearly marked UART0 connector on the edge of the board beside the ethernet connector. All you have to do is attach some leads according to our [[UART|UART howto]].<br />
<br />
= Pictures =<br />
<br />
<gallery><br />
File:Lime2_top.jpg<br />
File:Lime2_bot.jpg<br />
File:Lime2_fel.jpg<br />
File:Lime2_uext.jpg<br />
</gallery><br />
<br />
= See also =<br />
<br />
* [[Olimex A10-OLinuXino-Lime]]<br />
* [https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A20-OLinuXino-LIME2 Lime2 schematics & CAD files]<br />
== Manufacturer images ==<br />
<br />
[https://www.olimex.com/wiki/A20-OLinuXino-LIME2#Linux Olimex images for Lime2]<br />
<br />
[[Category:Devices]]<br />
[[Category:Mainline_U-Boot]]<br />
[[Category:Mainline_Kernel]]<br />
[[Category:A20 Boards]]<br />
[[Category:OSHW]]<br />
[[Category:Community_Devices]]<br />
[[Category:Olimex]]<br />
[[Category:Devices with Ethernet port]]<br />
[[Category:Devices with HDMI port]]<br />
[[Category:Devices with SATA port]]</div>Olecomhttps://linux-sunxi.org/index.php?title=A20&diff=23146A202020-02-26T12:10:56Z<p>Olecom: fix 404s</p>
<hr />
<div>{{Infobox SoC<br />
| image = [[File:Allwinner_A20.png|250px]]<br />
| manufacturer = Allwinner<br />
| process = 40nm<br />
| cpu = Dual-Core ARM Cortex-A7<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR3/DDR3/LPDDR2<br />
| gpu = [[Mali400]] MP2<br />
| vpu = <br />
| apu = <br />
| video = HDMI 1.4, CVBS, YPbPr, VGA, CPU/RGB/LVDS LCD<br />
| audio = I2S, PCM, AC97<br />
| network = <br />
| storage = MMC, NAND, SATA<br />
| usb = OTG, 2x Host<br />
| other = <br />
| release_date = December 2012<br />
| website = [http://www.allwinnertech.com/index.php?c=product&a=index&id=45 Product Page]<br />
}}<br />
<br />
Allwinner [[A20]] (sun7i) SoC features a Dual-Core Cortex-A7 ARM CPU, and a [[Mali400]] MP2 GPU from ARM.<br />
<br />
Allwinner A20 is a low-end (budget) version of the [[A31]]. It shares its Cortex-A7 ARM CPU architecture, but at the same time it is also pin-to-pin compatible with [[A10]].<br />
<br />
A20 is fully supported by the community from linux-sunxi 3.4 kernel and later.<br />
<br />
=Overview=<br />
A20 CPU consists of dual ARM Cortex-A7 cores, and integrates the Mali400 MP2 GPU. Together with [[Cedar Engine]] multimedia processing unit that is capable of up to 2160p (3840x1080@30fps 4k resolution or 1080p 3D decoding) video decoding, with integrated HDMI 1.4 output support, and H.264 HP (High Profile) in 1080p at 30fps video encoding.<br />
<br />
==Main components of the A20 ==<br />
* CPU: Dual-Core ARM [http://en.wikipedia.org/wiki/ARM_Cortex-A7 Cortex-A7 1GHz Processor (r0p4, revidr=0x0)] which have both VFP4 and NEON SIMD co-processors that share 32 floating point double-precision registers together<ref>[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/BABDAHCE.html Cortex-A7 MPCore Technical Reference Manual — 1.3. Features]</ref>: <br />
** FPU: standard ARM VFPv4-D32 FPU Floating Point Unit<br />
** SIMD: NEON (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400|Mali400 MP2]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
* HDMI-transmitter: HDMI CEC (Consumer Electronics Control)<br />
<br />
==Cortex-A7==<br />
Cortex-A7 is 100% ISA compatible with the Cortex-A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration.<ref>http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices</ref><ref>http://en.wikipedia.org/wiki/ARM_Cortex-A7_MPCore</ref><ref>http://www.arm.com/products/processors/cortex-a/cortex-a7.php</ref><br />
<br />
=== Virtualization ===<br />
Cortex A7 and A15 includes hardware virtualization support.<br />
<br />
* It is managed by Xen ([http://www-archive.xenproject.org/files/xensummit_seoul11/nov2/2_XSAsia11_JGoodacre_HW_accelerated_virtualization_in_the_ARM_Cortex_processors.pdf Presentation of Cortex A7 and A15 capabilities for virtualisation], [http://www-archive.xenproject.org/products/xen_arm.html Xen ARM] on xenproject.org, [http://blog.xen.org/index.php/2012/09/21/xensummit-sessions-new-pvh-virtualisation-mode-for-arm-cortex-a15arm-servers-and-x86/ PVH mode] on blog.xen.org, [http://wiki.xen.org/wiki/Xen_ARMv7_with_Virtualization_Extensions Xen ARMv7 with Virtualization Extensions] on xenproject.org wiki)<br />
<br />
* [http://wiki.xen.org/wiki/Xen_ARM_with_Virtualization_Extensions/Allwinner there is a guide about running xen on a20]<br />
<br />
* [http://www.virtualopensystems.com/ Some guides to deploy virtualization on Cortex-A15 and source for virtualization with KVM on Cortex-A15 on github]<br />
<br />
* [http://www.ok-labs.com/releases/release/open-kernel-labs-delivers-okl4-mobile-virtualization-for-arm-Cortex-A7 Open Kernel Labs Delivers OKL4 Mobile Virtualization for ARM Cortex-A7 Processors]<br />
<br />
On the kvm branch of kernel.org, there is description of Cortex-A15 Virtualization extensions VGIC registers :<br />
<br />
* [https://git.kernel.org/cgit/virt/kvm/kvm.git/tree/Documentation/devicetree/bindings/arm/gic.txt GIC of ARM on kvm branch of the kernel]<br />
<br />
After the ARM Cortex-A7 documentation:<br />
<br />
* GIC memory MAP on Cortex-A7<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.1. GIC memory-map</ref>:<br />
0x4000-0x4FFF Virtual interface control, common base address<br />
0x5000-0x5FFF Virtual interface control, processor-specific base address<br />
0x6000-0x7FFF Virtual CPU interface<br />
* Virtual Maintenance Interrupt (PPI6)<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.2. Interrupt sources</ref> <br />
* 2 virtual interrupt signals, nVIRQ and nVFIQ<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.4. GIC configuration</ref><br />
* With MMU-400, Intermediate Physical Address (IPA) ca be used by guest OS<ref>CoreLink MMU-400 System Memory Management Unit Technical Reference Manual - 1.1. About the MMU-400</ref><br />
<br />
==A20 SoC Features==<br />
[[File:Allwinner A20.jpg|thumb|A20 SoC on a [[Cubieboard2]]]]<br />
* CPU<br />
** ARM Cortex-A7 Dual-Core ([http://infocenter.arm.com/help/topic/com.arm.doc.epm016887/index.html revision r0p4])<br />
** 256KiB L2-Cache (shared between two cores)<br />
** 32KiB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
** Large Physical Address Extensions (LPAE) 1TB<br />
* GPU<br />
** ARM Mali400 MP2<br />
** Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).<br />
** Complies with OpenGL ES 2.0<br />
* Memory<br />
** LPDDR2/DDR3/DDR3L controller<br />
** NAND Flash controller and 64-bit ECC<br />
* Video<br />
** HD H.264 2160P video decoding<br />
** Full HD video decoding<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@30fps encoding<br />
** 3840×1080@30fps 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** Support multi-channel HD display<br />
** Integrated HDMI 1.4<br />
** CPU/RGB/LVDS LCD interface 1920×1080 resolution<br />
** CVBS/YPbPr/VGA support<br />
** Integrated TV decoder<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV sensor<br />
** Integrated 24-bit parallel YUV 444 I/F<br />
** 5M/8M CMOS sensor support<br />
** Dual-sensor support<br />
* Audio<br />
** Integrated HI-FI 100dB Audio Codec<br />
** Dual MIC noise cancellation<br />
* package: BGA441 19 mm × 19 mm (0.80 mm Pitch)<br />
<br />
= Documentation =<br />
<br />
* [https://github.com/allwinner-zh/documents/raw/master/A20/A20_User_Manual_v1.4_20150510.pdf Allwinner A20 Manual v1.40] <small>(PDF, 857 pages, 2015-04-20)</small><br />
* [https://github.com/allwinner-zh/documents/raw/master/A20/A20_Datasheet_v1.5_20150510.pdf Allwinner A20 Datasheet v1.50] <small>(PDF, 36 pages, 2015-04-06)</small><br />
* [http://dl.linux-sunxi.org/A20/A20%20Brief%202013-04-07.pdf A20 Product Brief] (Outdated)<br />
* [http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf A20 User Manual] (Outdated v1.0)<br />
<br />
= DVFS =<br />
<br />
The A20 SoC supports dynamic voltage & frequency scaling. Below are the DVFS operating points, as documented in the A20 SDK (lichee-v2.0.tar.gz):<br />
<pre><br />
; dvfs voltage-frequency table configuration<br />
;<br />
; max_freq: cpu maximum frequency, based on Hz, can not be more than 1008MHz<br />
; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz<br />
;<br />
; LV_count: count of LV_freq/LV_volt, must be < 16<br />
;<br />
; LV1: core vdd is 1.45v if cpu frequency is (912Mhz, 1008Mhz]<br />
; LV2: core vdd is 1.40v if cpu frequency is (864Mhz, 912Mhz]<br />
; LV3: core vdd is 1.30v if cpu frequency is (792Mhz, 864Mhz]<br />
; LV4: core vdd is 1.25v if cpu frequency is (720Mhz, 792Mhz]<br />
; LV5: core vdd is 1.20v if cpu frequency is (624Mhz, 720Mhz]<br />
; LV6: core vdd is 1.15v if cpu frequency is (528Mhz, 624Mhz]<br />
; LV7: core vdd is 1.10v if cpu frequency is (312Mhz, 528Mhz]<br />
; LV8: core vdd is 1.05v if cpu frequency is ( 60Mhz, 312Mhz]<br />
</pre><br />
<br />
= Software =<br />
== Original SDKs ==<br />
We have made some SDKs available on our server:<br />
* A20-SDK-2.0 ([http://dl.linux-sunxi.org/SDK/A20-SDK-2.0/aw.tar.bz2 Full])<br />
* A20_SDK_20130319 ([http://dl.linux-sunxi.org/SDK/A20/A20_SDK_20130319.tar.gz Reduced], [http://dl.linux-sunxi.org/SDK/A20/A20_SDK_20130319/ Unpacked])<br />
<br />
== GPL Violations ==<br />
<br />
See [[GPL_Violations#CedarX|CedarX violations.]]<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A20 Devices</categorytree><br />
= See also =<br />
* [[Mali400]]<br />
* [[A10]]<br />
* [[A10s]]<br />
* [[A13]]<br />
* [[A31]]<br />
<br />
=References=<br />
<references /><br />
<br />
= External links =<br />
* [http://www.allwinnertech.com/index.php?c=product&a=index&id=45 Product Page]<br />
* [https://github.com/amery/linux-allwinner/tree/import/lichee-3.3/a20-dev kernel source code for Allwinner A20]<br />
* [https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A20-PDFs/A20_PAD_STD_V1_1.rar?raw=true Allwinner A20 EVB Schematics]<br />
* [http://www.allwinnertech.com/uploads/pdf/20190404102543df.pdf Allwinner A20 product brief]<br />
* [http://en.wikipedia.org/wiki/Allwinner_A20 Allwinner A20 article on wikipedia.org]<br />
<br />
[[Category:System on Chip]]</div>Olecom