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2024-03-28T22:27:50Z
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https://linux-sunxi.org/index.php?title=CedarX/Reverse_Engineering&diff=18728
CedarX/Reverse Engineering
2016-11-22T21:36:52Z
<p>Nove: don't forget h265</p>
<hr />
<div>= Current status = <br />
{{MBOX NOTE|'''FIRST NOTE: Allwinner's [[Cedar Engine|video de-/encoding engine]] is successfully reverse engineered in the most common parts (HEVC, H264, MPEG1/2, MPEG4).'''<br />
<br />
The results of this reverse engineering are bundled in a [[Cedrus/libvdpau-sunxi|vdpau driver backend]] since January 2014.<br />
<br />
To do hardware accelerated video decoding on sunxi devices nowadays, you don't need any software provided by Allwinner, which is either (partly) closed sourced and/ or violating the GPL. Instead you should use the result of the community's reverse engineering work, called [[Cedrus]].<br />
<br />
As this is only proof of concept code, the goal is a [[VE_Planning|mainlined video engine driver]] in the end. To take full advantage of such a driver, the other bits (display, hdmi, sound ...) also have to be rewritten in ongoing [[Linux mainlining effort|mainline process]].<br />
}}<br />
<br />
= Hardware registers =<br />
The closed source blob uses direct access to hardware registers using mmap to userspace. Currently known register usage is documented: <br />
<br />
* [[VE Register guide]]<br />
* [[ACE Register guide]]<br />
<br />
There's ongoing register documentation effort using [https://github.com/plaes/envytools envytools].<br />
<br />
= Progress history =<br />
<br />
; 15 June 2012<br />
: Iain Bullard [http://article.gmane.org/gmane.comp.hardware.netbook.arm/3351 started reverse engineering the proprietary libraries].<br />
:* [https://github.com/iainb/open_cdxalloc open_cdxalloc] as an free reimplementation of [[Allwinner]]'s <tt>libcederxalloc.a</tt>.<br />
:* [https://github.com/iainb/CedarXWrapper CedarXWrapper] as a <tt>LD_PRELOAD</tt>ed wrapper to help understanding the proprietary libraries.<br />
:* [https://github.com/iainb/CedarXPlayerTest CedarXPlayerTest] as a basic player to use when testing.<br />
<br />
; 3 May 2013<br />
: wingrime and oliver started work on register guide, JPEG, MPEG decoding manuals and [[CedarX_binary_analysis|binary analysis]].<br />
<br />
; 20 May 2013<br />
: nove introduced new MMIO tracer based on Valgrind<br />
:* [https://gitorious.org/recedro ReCedro] has similar tools as those from IanB above, but with a different angle, works really well.<br />
<br />
; 22 June 2013<br />
: JPEG decoding proof-of-concept was introduced by Jemk [https://github.com/jemk/cedrus JPEG/MPEG-12 Decoding PoC]<br />
<br />
; 30 August 2013<br />
: Workable proof-of-concept VDPAU decoder was introduced by Jemk support MPEG-1/2 and MPEG-4 AVC/h.264 decoding [https://github.com/linux-sunxi/libvdpau-sunxi libvdpau-sunxi]<br />
<br />
; 24 August ~ 12 September 2013<br />
: Paullo612 worked in documenting vp8 decoding.<br />
<br />
; 12 January 2014<br />
: First MPEG-4 AVC/h.264 encoder proof-of-concept from Jemk<br />
<br />
; 15 January 2014<br />
: Jpeg encoding proof-of-concept by nove [https://gitorious.org/recedro/jepoc jepoc]<br />
<br />
; 31 January 2014<br />
: Jemk added to libvdpau-sunxi the first support for decoding (some) mpeg4 videos<br />
<br />
; 28 November 2015<br />
: Jemk added [https://github.com/linux-sunxi/libvdpau-sunxi/commit/0947363eaf083ba08d85f0c06b2b2d62ae2841a0 initial H.265 support] to libvdpau-sunxi<br />
<br />
; 12 July 2016<br />
: ubobrov modified Jemk's proof-of-concept h264 encoder sources making them workable on [https://github.com/uboborov/h264_encoder_H3 H3 platform]<br />
<br />
A first proof at the end ...<br /><br />
{{#ev:youtube|z__RxeVmYCQ|640}}<br />
<br />
[[Category:CedarX]]</div>
Nove
https://linux-sunxi.org/index.php?title=CedarX/Reverse_Engineering&diff=18722
CedarX/Reverse Engineering
2016-11-22T21:15:20Z
<p>Nove: no cedarx here</p>
<hr />
<div>= Current status = <br />
{{MBOX NOTE|'''FIRST NOTE: Allwinner's [[Cedar Engine|video de-/encoding engine]] is successfully reverse engineered in the most common parts (HEVC, H264, MPEG1/2, MPEG4).'''<br />
<br />
The results of this reverse engineering are bundled in a [[Cedrus/libvdpau-sunxi|vdpau driver backend]] since January 2014.<br />
<br />
To do hardware accelerated video decoding on sunxi devices nowadays, you don't need any software provided by Allwinner, which is either (partly) closed sourced and/ or violating the GPL. Instead you should use the result of the community's reverse engineering work, called [[Cedrus]].<br />
<br />
As this is only proof of concept code, the goal is a [[VE_Planning|mainlined video engine driver]] in the end. To take full advantage of such a driver, the other bits (display, hdmi, sound ...) also have to be rewritten in ongoing [[Linux mainlining effort|mainline process]].<br />
}}<br />
<br />
= Hardware registers =<br />
The closed source blob uses direct access to hardware registers using mmap to userspace. Currently known register usage is documented: <br />
<br />
* [[VE Register guide]]<br />
* [[ACE Register guide]]<br />
<br />
There's ongoing register documentation effort using [https://github.com/plaes/envytools envytools].<br />
<br />
= Progress history =<br />
<br />
; 15 June 2012<br />
: Iain Bullard [http://article.gmane.org/gmane.comp.hardware.netbook.arm/3351 started reverse engineering the proprietary libraries].<br />
:* [https://github.com/iainb/open_cdxalloc open_cdxalloc] as an free reimplementation of [[Allwinner]]'s <tt>libcederxalloc.a</tt>.<br />
:* [https://github.com/iainb/CedarXWrapper CedarXWrapper] as a <tt>LD_PRELOAD</tt>ed wrapper to help understanding the proprietary libraries.<br />
:* [https://github.com/iainb/CedarXPlayerTest CedarXPlayerTest] as a basic player to use when testing.<br />
<br />
; 3 May 2013<br />
: wingrime and oliver started work on register guide, JPEG, MPEG decoding manuals and [[CedarX_binary_analysis|binary analysis]].<br />
<br />
; 20 May 2013<br />
: nove introduced new MMIO tracer based on Valgrind<br />
:* [https://gitorious.org/recedro ReCedro] has similar tools as those from IanB above, but with a different angle, works really well.<br />
<br />
; 22 June 2013<br />
: JPEG decoding proof-of-concept was introduced by Jemk [https://github.com/jemk/cedrus JPEG/MPEG-12 Decoding PoC]<br />
<br />
; 30 August 2013<br />
: Workable proof-of-concept VDPAU decoder was introduced by Jemk support MPEG-1/2 and MPEG-4 AVC/h.264 decoding [https://github.com/linux-sunxi/libvdpau-sunxi libvdpau-sunxi]<br />
<br />
; 24 August ~ 12 September 2013<br />
: Paullo612 worked in documenting vp8 decoding.<br />
<br />
; 12 January 2014<br />
: First MPEG-4 AVC/h.264 encoder proof-of-concept from Jemk<br />
<br />
; 15 January 2014<br />
: Jpeg encoding proof-of-concept by nove [https://gitorious.org/recedro/jepoc jepoc]<br />
<br />
; 31 January 2014<br />
: Jemk added to libvdpau-sunxi the first support for decoding (some) mpeg4 videos<br />
<br />
; 12 July 2016<br />
: ubobrov modified Jemk's proof-of-concept h264 encoder sources making them workable on [https://github.com/uboborov/h264_encoder_H3 H3 platform]<br />
<br />
A first proof at the end ...<br /><br />
{{#ev:youtube|z__RxeVmYCQ|640}}<br />
<br />
[[Category:CedarX]]</div>
Nove
https://linux-sunxi.org/index.php?title=VE_Register_guide&diff=18389
VE Register guide
2016-10-26T20:35:50Z
<p>Nove: /* MACC_ISP_SRAM_DATA */</p>
<hr />
<div>__NOTOC__<br />
= Video Engine Registers =<br />
<br />
Base address: <br />
* <tt>0x01c0e000</tt> - A10/A13/A20 sun8iw1p1/sun8iw3p1/sun8iw5p1<br />
* <tt>0x03a40000</tt> - sun9iw1p1<br />
* <tt>0x01c0e000</tt> - sun8iw6p1<br />
<br />
<br />
[[#General Registers|General Registers]]<br/><br />
[[#MPEG Engine Registers|MPEG Engine Registers]]<br/><br />
[[#H264 Engine Registers|H264 Engine Registers]]<br/><br />
[[#VC1 Engine Registers|VC1 Engine Registers]]<br/><br />
[[#RMVB Engine Registers|RMVB Engine Registers]]<br/><br />
[[#HEVC Engine Registers|HEVC Engine Registers]]<br/><br />
[[#ISP Engine Registers|ISP Engine Registers]]<br/><br />
[[#AVC Encoder Engine Registers|AVC Encoder Engine Registers]]<br/><br />
<br />
== General Registers ==<br />
<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>[[#MACC_VE_CTRL|MACC_VE_CTRL]]</tt><br />
| <tt>0x0000</tt><br />
| <tt>4B</tt><br />
| <tt>Sub-Engine Select and RAM type select</tt><br />
|-<br />
| <tt>[[#MACC_VE_RESET|MACC_VE_RESET]]</tt><br />
| <tt>0x0004</tt><br />
| <tt>4B</tt><br />
| <tt>Sub-Engines Reset</tt><br />
|-<br />
| <tt>[[#MACC_VE_CYCLES_COUNTER|MACC_VE_CYCLES_COUNTER]]</tt><br />
| <tt>0x0008</tt><br />
| <tt>4B</tt><br />
| <tt>Clock Cycles counter</tt><br />
|-<br />
| <tt>[[#MACC_VE_TIMEOUT|MACC_VE_TIMEOUT]]</tt><br />
| <tt>0x000c</tt><br />
| <tt>4B</tt><br />
| <tt>VE Timeout value</tt><br />
|-<br />
| <tt>[[#MACC_VE_MMCREQ_WNUM|MACC_VE_MMCREQ_WNUM]]</tt><br />
| <tt>0x0010</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_VE_CACHEREG_WNUM|MACC_VE_CACHEREG_WNUM]]</tt><br />
| <tt>0x0014</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_VE_STATUS|MACC_VE_STATUS]]</tt><br />
| <tt>0x001c</tt><br />
| <tt>4B</tt><br />
| <tt>Busy status</tt><br />
|-<br />
| <tt>[[#MACC_VE_RDDATA_COUNTER|MACC_VE_RDDATA_COUNTER]]</tt><br />
| <tt>0x0020</tt><br />
| <tt>4B</tt><br />
| <tt>DRAM Read counter</tt><br />
|-<br />
| <tt>[[#MACC_VE_WRDATA_COUNTER|MACC_VE_WRDATA_COUNTER]]</tt><br />
| <tt>0x0024</tt><br />
| <tt>4B</tt><br />
| <tt>DRAM Write counter</tt><br />
|-<br />
| <tt>[[#MACC_VE_ANAGLYPH_CTRL|MACC_VE_ANAGLYPH_CTRL]]</tt><br />
| <tt>0x0028</tt><br />
| <tt>4B</tt><br />
| <tt>Anaglyph mode control</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAF_CTRL|MACC_VE_MAF_CTRL]]</tt><br />
| <tt>0x0030</tt><br />
| <tt>4B</tt><br />
| <tt>Motion adaptive filter config</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAF_CLIP_TH|MACC_VE_MAF_CLIP_TH]]</tt><br />
| <tt>0x0034</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_VE_MAFREF1_LUMA_BUF|MACC_VE_MAFREF1_LUMA_BUF]]</tt><br />
| <tt>0x0038</tt><br />
| <tt>4B</tt><br />
| <tt>Reference luma buffer {unsure}</tt><br />
|- <br />
| <tt>[[#MACC_VE_MAFREF1_CHROMA_BUF|MACC_VE_MAFREF1_CHROMA_BUF]]</tt><br />
| <tt>0x003c</tt><br />
| <tt>4B</tt><br />
| <tt>Reference chroma buffer {unsure}</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAFCUR_ADDR|MACC_VE_MAFCUR_ADDR]]</tt><br />
| <tt>0x0040</tt><br />
| <tt>4B</tt><br />
| <tt>current maf output address {unsure}</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAFREF1_ADDR|MACC_VE_MAFREF1_ADDR]]</tt><br />
| <tt>0x0044</tt><br />
| <tt>4B</tt><br />
| <tt>reference maf input address {unsure}</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAFREF2_ADDR|MACC_VE_MAFREF2_ADDR]]</tt><br />
| <tt>0x0048</tt><br />
| <tt>4B</tt><br />
| <tt>second reference maf input address {unsure}</tt><br />
|-<br />
| <tt>[[#MACC_VE_MAFDIFF_GROUP_MAX|MACC_VE_MAFDIFF_GROUP_MAX]]</tt><br />
| <tt>0x004c</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_VE_IPD_DBLK_BUF_CTRL|MACC_VE_IPD_DBLK_BUF_CTRL]]</tt><br />
| <tt>0x0050</tt><br />
| <tt>4B</tt><br />
| <tt>deblocking and intra prediction dram buffer config register (required for A13+ SoC for H264 decoding or on A10 for video with width >= 2048)</tt><br />
|-<br />
| <tt>[[#MACC_VE_IPD_BUF|MACC_VE_IPD_BUF]]</tt><br />
| <tt>0x0054</tt><br />
| <tt>4B</tt><br />
| <tt>Intra prediction buffer (needed on A13+ or (width >= 2048))</tt><br />
|-<br />
| <tt>[[#MACC_VE_DBLK_BUF|MACC_VE_DBLK_BUF]]</tt><br />
| <tt>0x0058</tt><br />
| <tt>4B</tt><br />
| <tt>Deblocking buffer (needed on A13+ or (width >= 2048))</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_CMD_QUEUE_START|MACC_VE_ARGB_QUEUE_START]]</tt><br />
| <tt>0x005c</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB command queue</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_SRC1_ADDR|MACC_VE_ARGB_BLK_SRC1_ADDR]]</tt><br />
| <tt>0x0060</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB source 1 address</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_SRC2_ADDR|MACC_VE_ARGB_BLK_SRC2_ADDR]]</tt><br />
| <tt>0x0064</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB source 2 addres</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_DST_ADDR|MACC_VE_ARGB_BLK_DST_ADDR]]</tt><br />
| <tt>0x0068</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB destination address</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_SRC_STRIDE|MACC_VE_ARGB_SRC_STRIDE]]</tt><br />
| <tt>0x006c</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB source strides for src1 and src2</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_DST_STRIDE|MACC_VE_ARGB_DST_STRIDE]]</tt><br />
| <tt>0x0070</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB destination stride</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_SIZE|MACC_VE_ARGB_BLK_SIZE]]</tt><br />
| <tt>0x0074</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB size</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_FILL_VALUE|MACC_VE_ARGB_BLK_FILL_VALUE]]</tt><br />
| <tt>0x0078</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB fill value</tt><br />
|-<br />
| <tt>[[#MACC_VE_ARGB_BLK_CTRL|MACC_VE_ARGB_BLK_CTRL]]</tt><br />
| <tt>0x007c</tt><br />
| <tt>4B</tt><br />
| <tt>ARGB control</tt><br />
|-<br />
| <tt>[[#MACC_VE_LUMA_HIST_THRi|MACC_VE_LUMA_HIST_THR[0-3]]]</tt><br />
| <tt>0x0080 - 0x008c</tt><br />
| <tt>4B</tt><br />
| <tt>Luma histogram thresholds</tt><br />
|-<br />
| <tt>[[#MACC_VE_LUMA_HIST_VALi|MACC_VE_LUMA_HIST_VAL[0-15]]]</tt><br />
| <tt>0x0090 - 0x00cc</tt><br />
| <tt>4B</tt><br />
| <tt>Luma histogram output values</tt><br />
|-<br />
| <tt>[[#MACC_VE_ANGL_R_BUF|MACC_VE_ANGL_R_BUF]]</tt><br />
| <tt>0x00d0</tt><br />
| <tt>4B</tt><br />
| <tt>Anaglyph red output buffer</tt><br />
|-<br />
| <tt>[[#MACC_VE_ANGL_G_BUF|MACC_VE_ANGL_G_BUF]]</tt><br />
| <tt>0x00d4</tt><br />
| <tt>4B</tt><br />
| <tt>Anaglyph green output buffer</tt><br />
|-<br />
| <tt>[[#MACC_VE_ANGL_B_BUF|MACC_VE_ANGL_B_BUF]]</tt><br />
| <tt>0x00d8</tt><br />
| <tt>4B</tt><br />
| <tt>Anaglyph blue output buffer</tt><br />
|-<br />
| <tt>[[#MACC_VE_EXTRA_OUT_FMT_OFFSET|MACC_VE_EXTRA_OUT_FMT_OFFSET]]</tt><br />
| <tt>0x00e8</tt><br />
| <tt>4B</tt><br />
| <tt>Extra output format and chroma offset ''(not available on A10/A13/A20)''</tt><br />
|-<br />
| <tt>[[#MACC_VE_VERSION|MACC_VE_VERSION]]</tt><br />
| <tt>0x00f0</tt><br />
| <tt>4B</tt><br />
| <tt>IP Version register</tt><br />
|-<br />
| <tt>[[#MACC_VE_DBG_CTRL|MACC_VE_DBG_CTRL]]</tt><br />
| <tt>0x00f8</tt><br />
| <tt>4B</tt><br />
| <tt>Debug control</tt><br />
|-<br />
| <tt>[[#MACC_VE_DBG_OUTPUT|MACC_VE_DBG_OUTPUT]]</tt><br />
| <tt>0x00fc</tt><br />
| <tt>4B</tt><br />
| <tt>Debug output</tt><br />
|}<br />
<br />
== MPEG Engine Registers ==<br />
Base address: 0x01c0e100<br /><br />
Used by engine 0x0 (MPEG)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|- <br />
| <tt>[[#MACC_MPEG_PHDR|MACC_MPEG_PHDR]]</tt><br />
| <tt>0x0100</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG12 Picture Header register</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VOPHDR|MACC_MPEG_VOPHDR]]</tt><br />
| <tt>0x0104</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Video Object Plane Header register (MPEG4 Header)</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SIZE|MACC_MPEG_SIZE]]</tt><br />
| <tt>0x0108</tt><br />
| <tt>4B</tt><br />
| <tt>Frame size in MPEG macroblocks (16x16)</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_FRAME_SIZE|MACC_MPEG_FRAME_SIZE]]</tt><br />
| <tt>0x010c</tt><br />
| <tt>4B</tt><br />
| <tt>Frame size in pixels </tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MBA|MACC_MPEG_MBA]]</tt><br />
| <tt>0x0110</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Address register</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_CTRL|MACC_MPEG_CTRL]]</tt><br />
| <tt>0x0114</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Control Register</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_TRIG|MACC_MPEG_TRIG]]</tt><br />
| <tt>0x0118</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Decoding Trigger</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_STATUS|MACC_MPEG_STATUS]]</tt><br />
| <tt>0x011c</tt><br />
| <tt>4B</tt><br />
| <tt>MACC MPEG Status register</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_FRAME_DIST|MACC_MPEG_FRAME_DIST]]</tt><br />
| <tt>0x0120</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG P and B Frame distance</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_TRBTRDFLD|MACC_MPEG_TRBTRDFLD]]</tt><br />
| <tt>0x0124</tt><br />
| <tt>4B</tt><br />
| <tt>Temporal References(TRB(B-VOP) and TRD)</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VLD_ADDR|MACC_MPEG_VLD_ADDR]]</tt><br />
| <tt>0x0128</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Variable Length Decoding Address</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VLD_OFFSET|MACC_MPEG_VLD_OFFSET]]</tt><br />
| <tt>0x012c</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Variable Length Decoding Offset</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VLD_LEN|MACC_MPEG_VLD_LEN]]</tt><br />
| <tt>0x0130</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Variable Length Decoding Length</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VBV_END|MACC_MPEG_VBV_END]]</tt><br />
| <tt>0x0134</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG VBV end - video source buffer end</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MBH_ADDR|MACC_MPEG_MBH_ADDR]]</tt><br />
| <tt>0x0138</tt><br />
| <tt>4B</tt><br />
| <tt>MBH buffer address</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_DCAC_ADDR|MACC_MPEG_DCAC_ADDR]]</tt><br />
| <tt>0x013c</tt><br />
| <tt>4B</tt><br />
| <tt>DCAC Buffer address</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_BLK_OFFSET|MACC_MPEG_BLK_OFFSET]]</tt><br />
| <tt>0x0140</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Block address???</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_NCF_ADDR|MACC_MPEG_NCF_ADDR]]</tt><br />
| <tt>0x0144</tt><br />
| <tt>4B</tt><br />
| <tt>NFC buffer address</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_REC_LUMA|MACC_MPEG_REC_LUMA]]</tt><br />
| <tt>0x0148</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Luma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_REC_CHROMA|MACC_MPEG_REC_CHROMA]]</tt><br />
| <tt>0x014c</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Chroma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_FWD_LUMA|MACC_MPEG_FWD_LUMA]]</tt><br />
| <tt>0x0150</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Luma forward buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_FWD_CHROMA|MACC_MPEG_FWD_CHROMA]]</tt><br />
| <tt>0x0154</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG forward buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_BACK_LUMA|MACC_MPEG_BACK_LUMA]]</tt><br />
| <tt>0x0158</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Luma Back buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_BACK_CHROMA|MACC_MPEG_BACK_CHROMA]]</tt><br />
| <tt>0x015c</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Chroma Back buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SOCX|MACC_MPEG_SOCX]]</tt><br />
| <tt>0x0160</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SOCY|MACC_MPEG_SOCY]]</tt><br />
| <tt>0x0164</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SOL|MACC_MPEG_SOL]]</tt><br />
| <tt>0x0168</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SDLX|MACC_MPEG_SDLX]]</tt><br />
| <tt>0x016c</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SDLY|MACC_MPEG_SDLY]]</tt><br />
| <tt>0x0170</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SPRITESHFT|MACC_MPEG_SPRITESHFT]]</tt><br />
| <tt>0x0174</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SDCX|MACC_MPEG_SDCX]]</tt><br />
| <tt>0x0178</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SDCY|MACC_MPEG_SDCY]]</tt><br />
| <tt>0x017c</tt><br />
| <tt>4B</tt><br />
| <tt>MS-MPEG related</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_IQ_MIN_INPUT|MACC_MPEG_IQ_MIN_INPUT]]</tt><br />
| <tt>0x0180</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Inverse Quantization minimum input level</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_IQ_INPUT|MACC_MPEG_IQ_INPUT]]</tt><br />
| <tt>0x0184</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Inverse Quantization input level</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MSMPEG4_HDR|MACC_MPEG_MSMPEG4_HDR]]</tt><br />
| <tt>0x0188</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG MS-Mpeg-4 header</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_VP6_HDR|MACC_MPEG_VP6_HDR]]</tt><br />
| <tt>0x018c</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG VP6 Header</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_IQ_IDCT_INPUT|MACC_MPEG_IQ_IDCT_INPUT]]</tt><br />
| <tt>0x0190</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Inverse Quantization and Inverse Discrete Cosine Transform input</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_HEIGHT|MACC_MPEG_MB_HEIGHT]]</tt><br />
| <tt>0x0194</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Height</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V1|MACC_MPEG_MB_V1]]</tt><br />
| <tt>0x0198</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 1</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V2|MACC_MPEG_MB_V2]]</tt><br />
| <tt>0x019c</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 2</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V3|MACC_MPEG_MB_V3]]</tt><br />
| <tt>0x01a0</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 3</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V4|MACC_MPEG_MB_V4]]</tt><br />
| <tt>0x01a4</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 4</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V5|MACC_MPEG_MB_V5]]</tt><br />
| <tt>0x01a8</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 5</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V6|MACC_MPEG_MB_V6]]</tt><br />
| <tt>0x01ac</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 6</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V7|MACC_MPEG_MB_V7]]</tt><br />
| <tt>0x01b0</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 7</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_MB_V8|MACC_MPEG_MB_V8]]</tt><br />
| <tt>0x01b4</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Macro Block Vector 8</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_JPEG_SIZE|MACC_MPEG_JPEG_SIZE]]</tt><br />
| <tt>0x01b8</tt><br />
| <tt>4B</tt><br />
| <tt>JPEG Size</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_JPEG_MCU|MACC_MPEG_JPEG_MCU]]</tt><br />
| <tt>0x01bc</tt><br />
| <tt>4B</tt><br />
| <tt>JPEG Minimum Coded Unit</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_JPEG_RES_INT|MACC_MPEG_JPEG_RES_INT]]</tt><br />
| <tt>0x01c0</tt><br />
| <tt>4B</tt><br />
| <tt>JPEG Restart Interval</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_ERROR|MACC_MPEG_ERROR]]</tt><br />
| <tt>0x01c4</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Error flags</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_CTR_MB|MACC_MPEG_CTR_MB]]</tt><br />
| <tt>0x01c8</tt><br />
| <tt>4B</tt><br />
| <tt>(Macroblock Control??)</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_ROT_LUMA|MACC_MPEG_ROT_LUMA]]</tt><br />
| <tt>0x01cc</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Rotate-Scale Luma buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_ROT_CHROMA|MACC_MPEG_ROT_CHROMA]]</tt><br />
| <tt>0x01d0</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG Rotate-Scale Chroma buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_ROTSCALE_CTRL|MACC_MPEG_ROTSCALE_CTRL]]</tt><br />
| <tt>0x01d4</tt><br />
| <tt>4B</tt><br />
| <tt>Control Rotate/Scale Buffer</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_JPEG_MCU_START|MACC_MPEG_JPEG_MCU_START]]</tt><br />
| <tt>0x01d8</tt><br />
| <tt>4B</tt><br />
| <tt>JPEG Macro Cell Unit Start</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_JPEG_MCU_END|MACC_MPEG_JPEG_MCU_END]]</tt><br />
| <tt>0x01dc</tt><br />
| <tt>4B</tt><br />
| <tt>JPEG Macro Cell Unit End</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SRAM_RW_OFFSET|MACC_MPEG_SRAM_RW_OFFSET]]</tt><br />
| <tt>0x01e0</tt><br />
| <tt>4B</tt><br />
| <tt>Auto incremental pointer for read/write VE SRAM</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_SRAM_RW_DATA|MACC_MPEG_SRAM_RW_DATA]]</tt><br />
| <tt>0x01e4</tt><br />
| <tt>4B</tt><br />
| <tt>FIFO Like Data register for write/read VE SRAM</tt><br />
|-<br />
| <tt>[[#MACC_MPEG_START_CODE_BITOFFSET|MACC_MPEG_START_CODE_BITOFFSET]]</tt><br />
| <tt>0x01f0</tt><br />
| <tt>4B</tt><br />
| <tt>MPEG start code search result</tt><br />
|}<br />
<br />
== H264 Engine Registers ==<br />
Base address: 0x01c0e200<br /><br />
Used by engine 0x1 (H264)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|- <br />
| <tt>[[#MACC_H264_SEQ_HDR|MACC_H264_SEQ_HDR]]</tt><br />
| <tt>0x0200</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Sequence header</tt><br />
|-<br />
| <tt>[[#MACC_H264_PIC_HDR|MACC_H264_PIC_HDR]]</tt><br />
| <tt>0x0204</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Picture header</tt><br />
|-<br />
| <tt>[[#MACC_H264_SLICE_HDR|MACC_H264_SLICE_HDR]]</tt><br />
| <tt>0x0208</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Slice header</tt><br />
|-<br />
| <tt>[[#MACC_H264_SLICE_HDR2|MACC_H264_SLICE_HDR2]]</tt><br />
| <tt>0x020c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Slice header</tt><br />
|-<br />
| <tt>[[#MACC_H264_PRED_WEIGHT|MACC_H264_PRED_WEIGHT]]</tt><br />
| <tt>0x0210</tt><br />
| <tt>4B</tt><br />
| <tt>H264 weighted prediction parameters</tt><br />
|-<br />
| <tt>[[#MACC_H264_VP8_HDR|MACC_H264_VP8_HDR]]</tt><br />
| <tt>0x0214</tt><br />
| <tt>4B</tt><br />
| <tt>H264 VP8 Picture header</tt><br />
|-<br />
| <tt>[[#MACC_H264_QINDEX|MACC_H264_QINDEX]]</tt><br />
| <tt>0x0218</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Quantizer settings (VP8)</tt><br />
|-<br />
| <tt>[[#MACC_H264_VP8_PART_OFFSET|MACC_H264_VP8_PART_OFFSET]]<br />
[[#MACC_H264_QP|MACC_H264_QP]]</tt><br />
| <tt>0x021c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 QP parameters (VP8 partition offset)</tt><br />
|-<br />
| <tt>[[#MACC_H264_CTRL|MACC_H264_CTRL]]</tt><br />
| <tt>0x0220</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Control Register</tt><br />
|-<br />
| <tt>[[#MACC_H264_TRIG|MACC_H264_TRIG]]</tt><br />
| <tt>0x0224</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Trigger Register</tt><br />
|-<br />
| <tt>[[#MACC_H264_STATUS|MACC_H264_STATUS]]</tt><br />
| <tt>0x0228</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Status Register</tt><br />
|-<br />
| <tt>[[#MACC_H264_CUR_MBNUM|MACC_H264_CUR_MBNUM]]</tt><br />
| <tt>0x022c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 current Macroblock</tt><br />
|-<br />
| <tt>[[#MACC_H264_VLD_ADDR|MACC_H264_VLD_ADDR]]</tt><br />
| <tt>0x0230</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Variable Length Decoder Address</tt><br />
|-<br />
| <tt>[[#MACC_H264_VLD_OFFSET|MACC_H264_VLD_OFFSET]]</tt><br />
| <tt>0x0234</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Variable Length Decoder Bit Offset</tt><br />
|-<br />
| <tt>[[#MACC_H264_VLD_LEN|MACC_H264_VLD_LEN]]</tt><br />
| <tt>0x0238</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Variable Length Decoder Bit Length</tt><br />
|-<br />
| <tt>[[#MACC_H264_VLD_END|MACC_H264_VLD_END]]</tt><br />
| <tt>0x023c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Variable Length Decoder End Address</tt><br />
|-<br />
| <tt>[[#MACC_H264_SDROT_CTRL|MACC_H264_SDROT_CTRL]]</tt><br />
| <tt>0x0240</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Scale Rotate buffer control</tt><br />
|-<br />
| <tt>[[#MACC_H264_SDROT_LUMA|MACC_H264_SDROT_LUMA]]</tt><br />
| <tt>0x0244</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Scale Rotate buffer Luma color component</tt><br />
|-<br />
| <tt>[[#MACC_H264_SDROT_CHROMA|MACC_H264_SDROT_CHROMA]]</tt><br />
| <tt>0x0248</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Scale Rotate buffer Chroma color component</tt><br />
|-<br />
| <tt>[[#MACC_H264_OUTPUT_FRAME_INDEX|MACC_H264_OUTPUT_FRAME_INDEX]]</tt><br />
| <tt>0x024c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 output frame index in dpb</tt><br />
|-<br />
| <tt>[[#MACC_H264_FIELD_INTRA_INFO_BUF|MACC_H264_FIELD_INTRA_INFO_BUF]]<br />
[[#MACC_H264_VP8_ENTROPY_PROBS|MACC_H264_VP8_ENTROPY_PROBS]]</tt><br />
| <tt>0x0250</tt><br />
| <tt>4B</tt><br />
| <tt>H264 field intra info buffer address (VP8 entropy brobabilities table address)</tt><br />
|-<br />
| <tt>[[#MACC_H264_NEIGHBOR_INFO_BUF|MACC_H264_NEIGHBOR_INFO_BUF]]<br />
[[#MACC_H264_VP8_FSTDATA_PARTLEN|MACC_H264_VP8_FSTDATA_PARTLEN]]</tt><br />
| <tt>0x0254</tt><br />
| <tt>4B</tt><br />
| <tt>H264 neighbor info buffer address (VP8 First partition length)</tt><br />
|-<br />
| <tt>[[#MACC_H264_PIC_MBSIZE|MACC_H264_PIC_MBSIZE]]</tt><br />
| <tt>0x0258</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Picture size in macroblocks</tt><br />
|-<br />
| <tt>[[#MACC_H264_PIC_BOUNDARYSIZE|MACC_H264_PIC_BOUNDARYSIZE]]</tt><br />
| <tt>0x025c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Picture size in pixels</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_ADDR|MACC_H264_MB_ADDR]]</tt><br />
| <tt>0x0260</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Current macroblock position</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB1|MACC_H264_MB_NB1]]</tt><br />
| <tt>0x0264</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ??? MbNeightbour1</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB2|MACC_H264_MB_NB2]]</tt><br />
| <tt>0x0268</tt><br />
| <tt>4B</tt><br />
| <tt>H264 MbNeightbour2</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB3|MACC_H264_MB_NB3]]</tt><br />
| <tt>0x026c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB4|MACC_H264_MB_NB4]]</tt><br />
| <tt>0x0270</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB5|MACC_H264_MB_NB5]]</tt><br />
| <tt>0x0274</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB6|MACC_H264_MB_NB6]]</tt><br />
| <tt>0x0278</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB7|MACC_H264_MB_NB7]]</tt><br />
| <tt>0x027c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_NB8|MACC_H264_MB_NB8]]</tt><br />
| <tt>0x0280</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x0284</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x0288</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x028c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_MB_QP|MACC_H264_MB_QP]]</tt><br />
| <tt>0x0290</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x0294</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x0298</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x029c</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02a0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02a4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02a8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_REC_LUMA|MACC_H264_REC_LUMA]]</tt><br />
| <tt>0x02ac</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Luma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_FWD_LUMA|MACC_H264_FWD_LUMA]]</tt><br />
| <tt>0x02b0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Luma forward buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_BACK_LUMA|MACC_H264_BACK_LUMA]]</tt><br />
| <tt>0x02b4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Luma back buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_ERROR|MACC_H264_ERROR]]</tt><br />
| <tt>0x02b8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Error</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02bc</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02c0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02c4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02c8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>MACC_H264_???</tt><br />
| <tt>0x02cc</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ???</tt><br />
|-<br />
| <tt>[[#MACC_H264_REC_CHROMA|MACC_H264_REC_CHROMA]]</tt><br />
| <tt>0x02d0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Chroma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_FWD_CHROMA|MACC_H264_FWD_CHROMA]]</tt><br />
| <tt>0x02d4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Chroma forward buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_BACK_CHROMA|MACC_H264_BACK_CHROMA]]</tt><br />
| <tt>0x02d8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Chroma back buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_BASIC_BITS_DATA|MACC_H264_BASIC_BITS_DATA]]</tt><br />
| <tt>0x02dc</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Basic bits data</tt><br />
|-<br />
| <tt>[[#MACC_H264_RAM_WRITE_PTR|MACC_H264_RAM_WRITE_PTR]]</tt><br />
| <tt>0x02e0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ram write pointer</tt><br />
|-<br />
| <tt>[[#MACC_H264_RAM_WRITE_DATA|MACC_H264_RAM_WRITE_DATA]]</tt><br />
| <tt>0x02e4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ram write data</tt><br />
|-<br />
| <tt>[[#MACC_H264_ALT_LUMA|MACC_H264_ALT_LUMA]]</tt><br />
| <tt>0x02e8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Alternate Luma buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_ALT_CHROMA|MACC_H264_ALT_CHROMA]]</tt><br />
| <tt>0x02ec</tt><br />
| <tt>4B</tt><br />
| <tt>H264 Alternate Chroma buffer</tt><br />
|-<br />
| <tt>[[#MACC_H264_SEG_MB_LV0|MACC_H264_SEG_MB_LV0]]</tt><br />
| <tt>0x02f0</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ??? Segment Mb Level 0</tt><br />
|-<br />
| <tt>[[#MACC_H264_SEG_MB_LV1|MACC_H264_SEG_MB_LV1]]</tt><br />
| <tt>0x02f4</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ??? Segment Mb Level 1</tt><br />
|-<br />
| <tt>[[#MACC_H264_REF_LF_DELTA|MACC_H264_REF_LF_DELTA]]</tt><br />
| <tt>0x02f8</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ??? (VP8 ref lf deltas)</tt><br />
|-<br />
| <tt>[[#MACC_H264_MODE_LF_DELTA|MACC_H264_MODE_LF_DELTA]]</tt><br />
| <tt>0x02fc</tt><br />
| <tt>4B</tt><br />
| <tt>H264 ??? (VP8 mode lf deltas)</tt><br />
|}<br />
<br />
== VC1 Engine Registers ==<br />
Base address: 0x01c0e300<br /><br />
Used by engine 0x2 (VC1)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>MACC_VC1_EPHS</tt><br />
| <tt>0x0300</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_CTRL</tt><br />
| <tt>0x0304</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_QP</tt><br />
| <tt>0x0308</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_MV</tt><br />
| <tt>0x030c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_INTEN_COMP</tt><br />
| <tt>0x0310</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_INTERLANCE</tt><br />
| <tt>0x0314</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_HDR_LEN</tt><br />
| <tt>0x0318</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_FSIZE</tt><br />
| <tt>0x031c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_PIC_SIZE</tt><br />
| <tt>0x0320</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_CTRL</tt><br />
| <tt>0x0324</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Decoder Control</tt><br />
|-<br />
| <tt>MACC_VC1_START_TYPE</tt><br />
| <tt>0x0328</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_STATUS</tt><br />
| <tt>0x032c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Status</tt><br />
|-<br />
| <tt>MACC_VC1_VBV_BASE_ADDR</tt><br />
| <tt>0x0330</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Source buffer address</tt><br />
|-<br />
| <tt>MACC_VC1_VLD_OFFSET</tt><br />
| <tt>0x0334</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Variable Length Decoder Offset</tt><br />
|-<br />
| <tt>MACC_VC1_VBV_LEN</tt><br />
| <tt>0x0338</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 length of source video buffer</tt><br />
|-<br />
| <tt>MACC_VC1_VBV_END_ADDR</tt><br />
| <tt>0x033c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 last address of source video buffer</tt><br />
|-<br />
| <tt>MACC_VC1_REC_FRAME_CHROMA</tt><br />
| <tt>0x0340</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Chroma Reconstruct frame</tt><br />
|-<br />
| <tt>MACC_VC1_REC_FRAME_LUMA</tt><br />
| <tt>0x0344</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Luma Reconstruct frame</tt><br />
|-<br />
| <tt>MACC_VC1_FWD_FRAME_CHROMA</tt><br />
| <tt>0x0348</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Chroma Forward Frame</tt><br />
|-<br />
| <tt>MACC_VC1_FWD_FRAME_LUMA</tt><br />
| <tt>0x034c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Luma Forward Frame</tt><br />
|-<br />
| <tt>MACC_VC1_BACK_CHROMA</tt><br />
| <tt>0x0350</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Chroma back buffer</tt><br />
|-<br />
| <tt>MACC_VC1_BACK_LUMA</tt><br />
| <tt>0x0354</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Luma back buffer</tt><br />
|-<br />
| <tt>MACC_VC1_MBHADDR</tt><br />
| <tt>0x0358</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_DCAPRED_ADDR</tt><br />
| <tt>0x035c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_BITPLANE_ADDR</tt><br />
| <tt>0x0360</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBINFO_ADDR</tt><br />
| <tt>0x0364</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???(or COLMVINFOADDR)</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x0368</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x036c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBA</tt><br />
| <tt>0x0370</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBHDR</tt><br />
| <tt>0x0374</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_LUMA_TRANSFORM</tt><br />
| <tt>0x0378</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBCBF</tt><br />
| <tt>0x037c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V1</tt><br />
| <tt>0x0380</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V2</tt><br />
| <tt>0x0384</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V3</tt><br />
| <tt>0x0388</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V4</tt><br />
| <tt>0x038c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V5</tt><br />
| <tt>0x0390</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V6</tt><br />
| <tt>0x0394</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V7</tt><br />
| <tt>0x0398</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_MBM_V8</tt><br />
| <tt>0x039c</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03a0</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03a4</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03a8</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03ac</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03b0</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03b4</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_ERROR</tt><br />
| <tt>0x03b8</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 Error result code</tt><br />
|-<br />
| <tt>MACC_VC1_CRT_MB_NUM</tt><br />
| <tt>0x03bc</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_EXTRA_CTRL</tt><br />
| <tt>0x03c0</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_EXTRA_CBUF_ADDR</tt><br />
| <tt>0x03c4</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 EXTRA Chroma DRAM address</tt><br />
|-<br />
| <tt>MACC_VC1_EXTRA_YBUF_ADDR</tt><br />
| <tt>0x03c8</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 EXTRA Luma DRAM address</tt><br />
|-<br />
| <tt>MACC_VC1_OVERLAP_UP_ADDR</tt><br />
| <tt>0x03d0</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_DBLK_ABOVE_ADDR</tt><br />
| <tt>0x03d4</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|-<br />
| <tt>MACC_VC1_???</tt><br />
| <tt>0x03d8</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
<br />
|-<br />
| <tt>MACC_VC1_BITS_RETDATA</tt><br />
| <tt>0x03dc</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
<br />
|-<br />
| <tt>MACC_VC1_DEBUG_BUF_ADDR</tt><br />
| <tt>0x03fc</tt><br />
| <tt>4B</tt><br />
| <tt>VC1 ???</tt><br />
|}<br />
<br />
== RMVB Engine Registers ==<br />
Base address: 0x01c0e400<br /><br />
Used by engine 0x3 (RMVB)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>MACC_RMVB_SLC_HDR</tt><br />
| <tt>0x0400</tt><br />
| <tt>4B</tt><br />
| <tt>Header</tt><br />
|-<br />
| <tt>MACC_RMVB_FRM_SIZE</tt><br />
| <tt>0x0404</tt><br />
| <tt>4B</tt><br />
| <tt>Framesize (in macroblocks ?) </tt><br />
|-<br />
| <tt>MACC_RMVB_DIR_MODE_RATIO</tt><br />
| <tt>0x0408</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_DIR_MB_ADDR</tt><br />
| <tt>0x040c</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_QC_INPUT</tt><br />
| <tt>0x0410</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_CTRL</tt><br />
| <tt>0x0414</tt><br />
| <tt>4B</tt><br />
| <tt>RMVB IRQ Control </tt><br />
|-<br />
| <tt>MACC_RMVB_TRIG</tt><br />
| <tt>0x0418</tt><br />
| <tt>4B</tt><br />
| <tt>Trigger register</tt><br />
|-<br />
| <tt>MACC_RMVB_STATUS</tt><br />
| <tt>0x041c</tt><br />
| <tt>4B</tt><br />
| <tt>RMVB Status </tt><br />
|-<br />
| <tt>MACC_RMVB_VBV_BASE</tt><br />
| <tt>0x0428</tt><br />
| <tt>4B</tt><br />
| <tt>Video source buffer base</tt><br />
|-<br />
| <tt>MACC_RMVB_VLD_OFFSET</tt><br />
| <tt>0x042c</tt><br />
| <tt>4B</tt><br />
| <tt>Video source buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_VLD_LEN</tt><br />
| <tt>0x0430</tt><br />
| <tt>4B</tt><br />
| <tt>Video source buffer length in bytes</tt><br />
|-<br />
| <tt>MACC_RMVB_VBV_END</tt><br />
| <tt>0x0434</tt><br />
| <tt>4B</tt><br />
| <tt>Video source buffer last DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_HUFF_TABLE_ADDR</tt><br />
| <tt>0x043c</tt><br />
| <tt>4B</tt><br />
| <tt>Huffman table DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_CUR_Y_ADDR</tt><br />
| <tt>0x0440</tt><br />
| <tt>4B</tt><br />
| <tt>Luma Current buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_CUR_C_ADDR</tt><br />
| <tt>0x0444</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma Current buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_FOR_Y_ADDR</tt><br />
| <tt>0x0448</tt><br />
| <tt>4B</tt><br />
| <tt>Luma Forward buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_FOR_C_ADDR</tt><br />
| <tt>0x044c</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma Forward buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_BAC_Y_ADDR</tt><br />
| <tt>0x0450</tt><br />
| <tt>4B</tt><br />
| <tt>Luma Back buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_BAC_C_ADDR</tt><br />
| <tt>0x0454</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma Back buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_ROT_Y_ADDR</tt><br />
| <tt>0x0458</tt><br />
| <tt>4B</tt><br />
| <tt>Luma Rot buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_ROT_C_ADDR</tt><br />
| <tt>0x045c</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma Rot Buffer DRAM address</tt><br />
|-<br />
| <tt>MACC_RMVB_MBH_ADDR</tt><br />
| <tt>0x0460</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_MV_ADDR</tt><br />
| <tt>0x0464</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_MBH_INFO</tt><br />
| <tt>0x0470</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_MV0</tt><br />
| <tt>0x0474</tt><br />
| <tt>4B</tt><br />
| <tt>Mountion vector 0</tt><br />
|-<br />
| <tt>MACC_RMVB_MV1</tt><br />
| <tt>0x0478</tt><br />
| <tt>4B</tt><br />
| <tt>Mountion vector 1</tt><br />
|-<br />
| <tt>MACC_RMVB_MV2</tt><br />
| <tt>0x047c</tt><br />
| <tt>4B</tt><br />
| <tt>Mountion vector 2</tt><br />
|-<br />
| <tt>MACC_RMVB_MV3</tt><br />
| <tt>0x0480</tt><br />
| <tt>4B</tt><br />
| <tt>Mountion vector 3</tt><br />
|-<br />
| <tt>MACC_RMVB_DBLK_COEF</tt><br />
| <tt>0x0490</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_ERROR</tt><br />
| <tt>0x04b0</tt><br />
| <tt>4B</tt><br />
| <tt>Decode error result code</tt><br />
|-<br />
| <tt>MACC_RMVB_BITS_DATA</tt><br />
| <tt>0x04b8</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_SLC_QUEUE_ADDR</tt><br />
| <tt>0x04c0</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_SLC_QUEUE_LEN</tt><br />
| <tt>0x04c4</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
<br />
|-<br />
| <tt>MACC_RMVB_SLC_QUEUE_TRIG</tt><br />
| <tt>0x04c8</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_SLC_QUEUE_STATUS</tt><br />
| <tt>0x04cc</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_SCALE_ROT_CTRL</tt><br />
| <tt>0x04d0</tt><br />
| <tt>4B</tt><br />
| <tt></tt><br />
|-<br />
| <tt>MACC_RMVB_SRAM_RW_OFFSET</tt><br />
| <tt>0x04e0</tt><br />
| <tt>4B</tt><br />
| <tt>SRAM Fifo like index register</tt><br />
|-<br />
| <tt>MACC_RMVB_SRAM_RW_DATA</tt><br />
| <tt>0x04e4</tt><br />
| <tt>4B</tt><br />
| <tt>SRAM Fifo like data register</tt><br />
|}<br />
<br />
== HEVC Engine Registers ==<br />
Base address: 0x01c0e500<br /><br />
Only on H3, used by engine 0x4 (HEVC)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>[[#MACC_HEVC_NAL_HDR|MACC_HEVC_NAL_HDR]]</tt><br />
| <tt>0x0500</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC NAL header</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SPS|MACC_HEVC_SPS]]</tt><br />
| <tt>0x0504</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC sequence parameter set</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_PIC_SIZE|MACC_HEVC_PIC_SIZE]]</tt><br />
| <tt>0x0508</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC picture size</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_PCM_HDR|MACC_HEVC_PCM_HDR]]</tt><br />
| <tt>0x050c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC PCM header</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_PPS0|MACC_HEVC_PPS0]]</tt><br />
| <tt>0x0510</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC picture parameter set</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_PPS1|MACC_HEVC_PPS1]]</tt><br />
| <tt>0x0514</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC picture parameter set</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SCALING_LIST_CTRL|MACC_HEVC_SCALING_LIST_CTRL]]</tt><br />
| <tt>0x0518</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC scaling list control register</tt><br />
|-<br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SLICE_HDR0|MACC_HEVC_SLICE_HDR0]]</tt><br />
| <tt>0x0520</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC slice header</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SLICE_HDR1|MACC_HEVC_SLICE_HDR1]]</tt><br />
| <tt>0x0524</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC slice header</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SLICE_HDR2|MACC_HEVC_SLICE_HDR2]]</tt><br />
| <tt>0x0528</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC slice header</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_CTB_ADDR|MACC_HEVC_CTB_ADDR]]</tt><br />
| <tt>0x052c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC CTB address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_CTRL|MACC_HEVC_CTRL]]</tt><br />
| <tt>0x0530</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC control register</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_TRIG|MACC_HEVC_TRIG]]</tt><br />
| <tt>0x0534</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC trigger register</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_STATUS|MACC_HEVC_STATUS]]</tt><br />
| <tt>0x0538</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC status register</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_CTU_NUM|MACC_HEVC_CTU_NUM]]</tt><br />
| <tt>0x053c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC current CTU number</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_BITS_ADDR|MACC_HEVC_BITS_ADDR]]</tt><br />
| <tt>0x0540</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC bitstream address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_BITS_OFFSET|MACC_HEVC_BITS_OFFSET]]</tt><br />
| <tt>0x0544</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC bitstream offset</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_BITS_LEN|MACC_HEVC_BITS_LEN]]</tt><br />
| <tt>0x0548</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC bitstream length</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_BITS_END_ADDR|MACC_HEVC_BITS_END_ADDR]]</tt><br />
| <tt>0x054c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC bitstream end address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_EXTRA_OUT_CTRL|MACC_HEVC_EXTRA_OUT_CTRL]]</tt><br />
| <tt>0x0550</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC extra output control register</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_EXTRA_OUT_LUMA_ADDR|MACC_HEVC_EXTRA_OUT_LUMA_ADDR]]</tt><br />
| <tt>0x0554</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC extra output luma address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_EXTRA_OUT_CHROMA_ADDR|MACC_HEVC_EXTRA_OUT_CHROMA_ADDR]]</tt><br />
| <tt>0x0558</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC extra output chroma address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_REC_BUF_IDX|MACC_HEVC_REC_BUF_IDX]]</tt><br />
| <tt>0x055c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC reconstruct buffer index</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_NEIGHBOR_INFO_ADDR|MACC_HEVC_NEIGHBOR_INFO_ADDR]]</tt><br />
| <tt>0x0560</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC neighbor info buffer address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_TILE_LIST_ADDR|MACC_HEVC_TILE_LIST_ADDR]]</tt><br />
| <tt>0x0564</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC tile entry point list address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_TILE_START_CTB|MACC_HEVC_TILE_START_CTB]]</tt><br />
| <tt>0x0568</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC tile start CTB</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_TILE_END_CTB|MACC_HEVC_TILE_END_CTB]]</tt><br />
| <tt>0x056c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC tile end CTB</tt><br />
|-<br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SCALING_LIST_DC_COEF0|MACC_HEVC_SCALING_LIST_DC_COEF0]]</tt><br />
| <tt>0x0578</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC scaling list DC coefficients</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SCALING_LIST_DC_COEF1|MACC_HEVC_SCALING_LIST_DC_COEF1]]</tt><br />
| <tt>0x057c</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC scaling list DC coefficients</tt><br />
|-<br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|-<br />
| <tt>[[#MACC_HEVC_BITS_DATA|MACC_HEVC_BITS_DATA]]</tt><br />
| <tt>0x05dc</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC bitstream data</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SRAM_ADDR|MACC_HEVC_SRAM_ADDR]]</tt><br />
| <tt>0x05e0</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC SRAM address</tt><br />
|-<br />
| <tt>[[#MACC_HEVC_SRAM_DATA|MACC_HEVC_SRAM_DATA]]</tt><br />
| <tt>0x05e4</tt><br />
| <tt>4B</tt><br />
| <tt>HEVC SRAM data</tt><br />
|-<br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
| <tt></tt><br />
|}<br />
<br />
== ISP Engine Registers ==<br />
Base address: 0x01c0ea00<br /><br />
Used by engine 0x8 (MPEG enc), 0xa (ISP) and 0xb (AVC enc)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>[[#MACC_ISP_PIC_SIZE|MACC_ISP_PIC_SIZE]]</tt><br />
| <tt>0x0a00</tt><br />
| <tt>4B</tt><br />
| <tt>ISP source picture size in macroblocks (16x16)</tt><br />
|-<br />
| <tt>[[#MACC_ISP_PIC_STRIDE|MACC_ISP_PIC_STRIDE]]</tt><br />
| <tt>0x0a04</tt><br />
| <tt>4B</tt><br />
| <tt>ISP source picture stride</tt><br />
|-<br />
| <tt>[[#MACC_ISP_CTRL|MACC_ISP_CTRL]]</tt><br />
| <tt>0x0a08</tt><br />
| <tt>4B</tt><br />
| <tt>ISP IRQ Control </tt><br />
|-<br />
| <tt>[[#MACC_ISP_TRIG|MACC_ISP_TRIG]]</tt><br />
| <tt>0x0a0c</tt><br />
| <tt>4B</tt><br />
| <tt>ISP Trigger </tt><br />
|-<br />
| <tt>[[#MACC_ISP_SCALER_SIZE|MACC_ISP_SCALER_SIZE]]</tt><br />
| <tt>0x0a2c</tt><br />
| <tt>4B</tt><br />
| <tt>ISP scaler frame size/16</tt><br />
|-<br />
| <tt>[[#MACC_ISP_SCALER_OFFSET_Y|MACC_ISP_SCALER_OFFSET_Y]]</tt><br />
| <tt>0x0a30</tt><br />
| <tt>4B</tt><br />
| <tt>ISP scaler picture offset for luma</tt><br />
|-<br />
| <tt>[[#MACC_ISP_SCALER_OFFSET_C|MACC_ISP_SCALER_OFFSET_C]]</tt><br />
| <tt>0x0a34</tt><br />
| <tt>4B</tt><br />
| <tt>ISP scaler picture offset for chroma</tt><br />
|-<br />
| <tt>[[#MACC_ISP_SCALER_FACTOR|MACC_ISP_SCALER_FACTOR]]</tt><br />
| <tt>0x0a38</tt><br />
| <tt>4B</tt><br />
| <tt>ISP scaler picture scale factor</tt><br />
|-<br />
| <tt>MACC_ISP_BUF???</tt><br />
| <tt>0x0a44</tt><br />
| <tt>4B</tt><br />
| <tt>ISP PHY Buffer offset</tt><br />
|-<br />
| <tt>MACC_ISP_BUF???</tt><br />
| <tt>0x0a48</tt><br />
| <tt>4B</tt><br />
| <tt>ISP PHY Buffer offset</tt><br />
<br />
|-<br />
| <tt>MACC_ISP_BUF???</tt><br />
| <tt>0x0a4C</tt><br />
| <tt>4B</tt><br />
| <tt>ISP PHY Buffer offset</tt><br />
|-<br />
| <tt>MACC_ISP_??</tt><br />
| <tt>0x0a74</tt><br />
| <tt>4B</tt><br />
| <tt>ISP ??</tt><br />
<br />
|-<br />
| <tt>[[#MACC_ISP_OUTPUT_LUMA|MACC_ISP_OUTPUT_LUMA]]</tt><br />
| <tt>0x0a70</tt><br />
| <tt>4B</tt><br />
| <tt>ISP Output LUMA Address </tt><br />
|-<br />
| <tt>[[#MACC_ISP_OUTPUT_CHROMA|MACC_ISP_OUTPUT_CHROMA]]</tt><br />
| <tt>0x0a74</tt><br />
| <tt>4B</tt><br />
| <tt>ISP Output CHROMA Address </tt><br />
<br />
|-<br />
| <tt>[[#MACC_ISP_WB_THUMB_LUMA|MACC_ISP_WB_THUMB_LUMA]]</tt><br />
| <tt>0x0a78</tt><br />
| <tt>4B</tt><br />
| <tt>ISP THUMB WriteBack PHY LUMA Address </tt><br />
|-<br />
| <tt>[[#MACC_ISP_WB_THUMB_CHROMA|MACC_ISP_WB_THUMB_CHROMA]]</tt><br />
| <tt>0x0a7c</tt><br />
| <tt>4B</tt><br />
| <tt>ISP THUMB WriteBack PHY CHROMA Adress</tt><br />
|-<br />
| <tt>[[#MACC_ISP_SRAM_INDEX|MACC_ISP_SRAM_INDEX]]</tt><br />
| <tt>0x0ae0</tt><br />
| <tt>4B</tt><br />
| <tt>ISP VE SRAM Index</tt><br />
|-<br />
| <tt>[[#MACC_ISP_SRAM_DATA|MACC_ISP_SRAM_DATA]]</tt><br />
| <tt>0x0ae4</tt><br />
| <tt>4B</tt><br />
| <tt>ISP VE SRAM Data</tt><br />
|}<br />
<br />
== AVC Encoder Engine Registers ==<br />
Base address: 0x01c0eb00<br /><br />
Used by engine 0xb (AVC enc)<br />
{| class="wikitable" |<br />
! Register Name<br />
! Offset<br />
! Size<br />
! Description<br />
|-<br />
| <tt>MACC_AVC_??</tt><br />
| <tt>0x0b00</tt><br />
| <tt>4B</tt><br />
| <tt>unk(not used in blob) </tt><br />
|-<br />
| <tt>[[#MACC_AVC_JPEG_CTRL|MACC_AVC_JPEG_CTRL]]<br />
[[#MACC_AVC_H264_CTRL|MACC_AVC_H264_CTRL]]</tt><br />
| <tt>0x0b04</tt><br />
| <tt>4B</tt><br />
| <tt>jpeg / h264 different settings</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_QP|MACC_AVC_H264_QP]]</tt><br />
| <tt>0x0b08</tt><br />
| <tt>4B</tt><br />
| <tt>H264 quantization parameters</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_MOTION_EST|MACC_AVC_H264_MOTION_EST]]</tt><br />
| <tt>0x0b10</tt><br />
| <tt>4B</tt><br />
| <tt>Motion estimation parameters</tt><br />
|-<br />
| <tt>[[#MACC_AVC_CTRL|MACC_AVC_CTRL]]</tt><br />
| <tt>0x0b14</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Encoder IRQ Control </tt><br />
|-<br />
| <tt>[[#MACC_AVC_TRIG|MACC_AVC_TRIG]]</tt><br />
| <tt>0x0b18</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Encoder trigger </tt><br />
|-<br />
| <tt>[[#MACC_AVC_STATUS|MACC_AVC_STATUS]]</tt><br />
| <tt>0x0b1c</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Encoder Busy Status </tt><br />
|-<br />
| <tt>[[#MACC_AVC_BITS_DATA|MACC_AVC_BITS_DATA]]</tt><br />
| <tt>0x0b20</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Encoder Bits Data </tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_MAD|MACC_AVC_H264_MAD]]</tt><br />
| <tt>0x0b50</tt><br />
| <tt>4B</tt><br />
| <tt>AVC H264 Encoder Mean Absolute Difference</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_RESIDUAL_BITS|MACC_AVC_H264_RESIDUAL_BITS]]</tt><br />
| <tt>0x0b54</tt><br />
| <tt>4B</tt><br />
| <tt>AVC H264 Encoder Residual Bits</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_HEADER_BITS|MACC_AVC_H264_HEADER_BITS]]</tt><br />
| <tt>0x0b58</tt><br />
| <tt>4B</tt><br />
| <tt>AVC H264 Encoder Header Bits</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_??|MACC_AVC_H264_??]]</tt><br />
| <tt>0x0b5c</tt><br />
| <tt>4B</tt><br />
| <tt>AVC H264 Encoder ''unknown statistical data, maybe motion vectors''</tt><br />
|-<br />
| <tt>[[#MACC_AVC_H264_??|MACC_AVC_H264_??]]</tt><br />
| <tt>0x0b60</tt><br />
| <tt>4B</tt><br />
| <tt>AVC H264 Encoder ''unknown buffer''</tt><br />
|-<br />
| <tt>[[#MACC_AVC_VLE_ADDR|MACC_AVC_VLE_ADDR]]</tt><br />
| <tt>0x0b80</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Variable Length Encoder Start Address</tt><br />
|-<br />
| <tt>[[#MACC_AVC_VLE_END|MACC_AVC_VLE_END]]</tt><br />
| <tt>0x0b84</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Variable Length Encoder End Address</tt><br />
|-<br />
| <tt>[[#MACC_AVC_VLE_OFFSET|MACC_AVC_VLE_OFFSET]]</tt><br />
| <tt>0x0b88</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Variable Length Encoder Bit Offset</tt><br />
|-<br />
| <tt>[[#MACC_AVC_VLE_MAX|MACC_AVC_VLE_MAX]]</tt><br />
| <tt>0x0b8c</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Variable Length Encoder Maximum Bits</tt><br />
|-<br />
| <tt>[[#MACC_AVC_VLE_LENGTH|MACC_AVC_VLE_LENGTH]]</tt><br />
| <tt>0x0b90</tt><br />
| <tt>4B</tt><br />
| <tt>AVC Variable Length Encoder Bit Length</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REF_LUMA|MACC_AVC_REF_LUMA]]</tt><br />
| <tt>0x0ba0</tt><br />
| <tt>4B</tt><br />
| <tt>Luma reference buffer</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REF_CHROMA|MACC_AVC_REF_CHROMA]]</tt><br />
| <tt>0x0ba4</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma reference buffer</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REC_LUMA|MACC_AVC_REC_LUMA]]</tt><br />
| <tt>0x0bb0</tt><br />
| <tt>4B</tt><br />
| <tt>Luma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REC_CHROMA|MACC_AVC_REC_CHROMA]]</tt><br />
| <tt>0x0bb4</tt><br />
| <tt>4B</tt><br />
| <tt>Chroma reconstruct buffer</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REF_SLUMA|MACC_AVC_REF_SLUMA]]</tt><br />
| <tt>0x0bb8</tt><br />
| <tt>4B</tt><br />
| <tt>Smaller luma reference buffer ?</tt><br />
|-<br />
| <tt>[[#MACC_AVC_REC_SLUMA|MACC_AVC_REC_SLUMA]]</tt><br />
| <tt>0x0bbc</tt><br />
| <tt>4B</tt><br />
| <tt>Smaller luma reconstruct buffer ?</tt><br />
|-<br />
| <tt>[[#MACC_AVC_MB_INFO|MACC_AVC_MB_INFO]]</tt><br />
| <tt>0x0bc0</tt><br />
| <tt>4B</tt><br />
| <tt>Temporary buffer with macroblock information</tt><br />
|-<br />
| <tt>[[#MACC_AVC_SRAM_INDEX|MACC_AVC_SRAM_INDEX]]</tt><br />
| <tt>0x0be0</tt><br />
| <tt>4B</tt><br />
| <tt>AVC VE SRAM Index</tt><br />
|-<br />
| <tt>[[#MACC_AVC_SRAM_DATA|MACC_AVC_SRAM_DATA]]</tt><br />
| <tt>0x0be4</tt><br />
| <tt>4B</tt><br />
| <tt>AVC VE SRAM Data</tt><br />
|}<br />
<br />
= VE General Registers =<br />
<br />
== MACC_VE_CTRL ==<br />
Default value: 0x00000007<br /><br />
Offset: 0x0000<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_CTRL_ENGINE</tt><br />
| <tt>0:3</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x7</tt><br />
| <tt><br />
0x0 = MPEG<br />
0x1 = H264<br />
0x2 = VC1<br />
0x3 = RMVB<br />
0x4 = HEVC (H3 only)<br />
0x5-0x6 = reserved<br />
0x7 = place in #reset<br />
0x8 = MPEG Encoder {may be present only in sun3i}<br />
0x9 = reserved<br />
0xa = ISP<br />
0xb = AVC (H264 Encoder)<br />
0xc-0xf = reserved<br />
</tt><br />
| Select VE Engine:<br />
Each bit set represents Sub Engine that implemets personal codes sets,<br />
and enables required regiter set.<br />
H264 and MPEG Encoders using same register set, and seems 0x8 still<br />
here for historic reasons<br />
'''Note:''' selecting 0x7 mean 'place in reset state'<br />
|-<br />
| <tt></tt><br />
| <tt>4</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>5</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| Enable JPEG decoder (sun8iw8p1 (H3?) only)<br />
|-<br />
| <tt></tt><br />
| <tt>6</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| Enable ISP (1633 and newer only?)<br />
|-<br />
| <tt></tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| Enable AVC encoder (1633 and newer only?)<br />
|-<br />
| <tt>MACC_VE_CTRL_???</tt><br />
| <tt>8:9</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| ?<br />
|-<br />
| <tt></tt><br />
| <tt>10:15</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_CTRL_MEM_TYPE</tt><br />
| <tt>16:17</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0x0 = DDR1 16-BITS<br />
0x1 = DDR1 32-BITS / DDR2 16-Bits<br />
0x2 = DDR2 32-BITS / DDR3 16-Bits<br />
0x3 = DDR3 32-BITS<br />
</tt><br />
| Memory type (on current a10/a13 used only 0x3)<br />
|-<br />
| <tt></tt><br />
| <tt>18:19</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_CTRL_???</tt><br />
| <tt>20</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| more one mem type??<br />
|-<br />
| <tt>MACC_VE_CTRL_???</tt><br />
| <tt>21</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| needs to be set to decode pictures with more than 2048px width<br />
|-<br />
| <tt></tt><br />
| <tt>22:23</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_CTRL_???</tt><br />
| <tt>24:25</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| more one mem type??<br />
|-<br />
| <tt></tt><br />
| <tt>26:27</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_CTRL_???</tt><br />
| <tt>28</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
|<br />
| ?<br />
|-<br />
| <tt></tt><br />
| <tt>29:31</tt><br />
| <tt>Read only</tt><br />
| <tt>0x0</tt><br />
|<br />
| ''reserved''<br />
|}<br />
<br />
== MACC_VE_RESET ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0004<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| Reset sub-engines<br />
|-<br />
| <tt></tt><br />
| <tt>1:3</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| unused?<br />
|-<br />
| <tt></tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| unknown? <br />
|-<br />
| <tt></tt><br />
| <tt>5:31</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| unused?<br />
|-<br />
|}<br />
<br />
== MACC_VE_CYCLES_COUNTER ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0008<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_CYCLES_COUNTER_EN</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable cycle counter<br />
|-<br />
| <tt>MACC_VE_CYCLES_COUNTER_VAL</tt><br />
| <tt>30:0</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| Clock cycles since start of counter<br />
|}<br />
<br />
== MACC_VE_TIMEOUT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x000C<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>0:7</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ?<br />
|-<br />
| <tt></tt><br />
| <tt>8:30</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| overtime value<br />
|-<br />
| <tt></tt><br />
| <tt>31</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ? <br />
|}<br />
<br />
== MACC_VE_STATUS ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x001c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>0:8</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| reserved<br />
|-<br />
| <tt>MACC_VE_STATUS</tt><br />
| <tt>9:14</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x00</tt><br />
| <tt><br />
0x0 = Ready<br />
0x3 = Busy<br />
</tt><br />
| CedarX status<br />
|-<br />
| <tt></tt><br />
| <tt>15:31</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| reserved<br />
|}<br />
<br />
== MACC_VE_RDDATA_COUNTER ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0020<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_RDDATA_COUNTER_EN</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable read counter<br />
|-<br />
| <tt>MACC_VE_RDDATA_COUNTER_VAL</tt><br />
| <tt>30:0</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| Data read from DRAM in 64 bit words<br />
|}<br />
<br />
== MACC_VE_WRDATA_COUNTER ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0024<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_WRDATA_COUNTER_EN</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable write counter<br />
|-<br />
| <tt>MACC_VE_WRDATA_COUNTER_VAL</tt><br />
| <tt>30:0</tt><br />
| <tt>Read Only</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| Data written to DRAM in 64 bit words<br />
|}<br />
<br />
== MACC_VE_ANAGLYPH_CTRL ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0028<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_ANAGLYPH_OUT_EN</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable anaglyph output<br />
|-<br />
| <tt></tt><br />
| <tt>30:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_ANAGLYPH_COLORSPACE</tt><br />
| <tt>9:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = YCC<br />
0x1 = BT601<br />
0x2 = BT709<br />
0x3 = ''reserved''</tt><br />
| YUV to RGB conversion color space<br />
|-<br />
| <tt></tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_ANAGLYPH_MODE</tt><br />
| <tt>6:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = red/blue<br />
0x1 = red/green<br />
0x2 = red/cyan<br />
0x3 = color<br />
0x4 = half color<br />
0x5 = optimized<br />
0x6 = yellow/blue<br />
0x7 = ''reserved''</tt><br />
| Anaglyph color channels<br />
|-<br />
| <tt>MACC_VE_ANAGLYPH_SIDE</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = left<br />
0x1 = right</tt><br />
| Current decoded picture for "seperate frames" source mode<br />
|-<br />
| <tt></tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_ANAGLYPH_SRC_MODE</tt><br />
| <tt>1:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = side by side<br />
0x1 = top/down<br />
0x2 = line by line<br />
0x3 = separate frames</tt><br />
| Source mode<br />
|}<br />
<br />
== MACC_VE_IPD_DBLK_BUF_CTRL ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0050<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_IPD_BUF_CTRL</tt><br />
| <tt>3:2</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = only SRAM<br />
0x1 = left 1280 pixels SRAM, rest DRAM<br />
0x2 = only DRAM</tt><br />
| Intraprediction buffer control<br />
|-<br />
| <tt>MACC_VE_DBLK_BUF_CTRL</tt><br />
| <tt>1:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0</tt><br />
| <tt><br />
0x0 = only SRAM<br />
0x1 = left 1280 pixels SRAM, rest DRAM<br />
0x2 = only DRAM</tt><br />
| Deblocking buffer control<br />
|}<br />
<br />
== MACC_VE_LUMA_HIST_THRi ==<br />
Default value: see table<br /><br />
Offset: 0x0080 + (i * 4)<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_LUMA_HIST_THR_i_3</tt><br />
| <tt>31:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt>(i * 0x40) + 0x40</tt><br />
| <tt></tt><br />
| Threshold for histogram channel (i * 4) + 3<br />
|-<br />
| <tt>MACC_VE_LUMA_HIST_THR_i_2</tt><br />
| <tt>23:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt>(i * 0x40) + 0x30</tt><br />
| <tt></tt><br />
| Threshold for histogram channel (i * 4) + 2<br />
|-<br />
| <tt>MACC_VE_LUMA_HIST_THR_i_1</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt>(i * 0x40) + 0x20</tt><br />
| <tt></tt><br />
| Threshold for histogram channel (i * 4) + 1<br />
|-<br />
| <tt>MACC_VE_LUMA_HIST_THR_i_0</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>(i * 0x40) + 0x10</tt><br />
| <tt></tt><br />
| Threshold for histogram channel (i * 4) + 0<br />
|}<br />
<br />
== MACC_VE_LUMA_HIST_VALi ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0090 + (i * 4)<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:20</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_VE_LUMA_HIST_VAL</tt><br />
| <tt>19:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt></tt><br />
| Output value for histogram channel i<br />
|}<br />
<br />
== MACC_VE_EXTRA_OUT_FMT_OFFSET ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x00e8<br /><br />
VE Version 1633 and newer<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_EXTRA_OUT_FMT</tt><br />
| <tt>30:31</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0x0 = 32x32 tile format<br />
0x1 = reserved<br />
0x2 = YUV planar<br />
0x3 = YVU planar<br />
</tt><br />
| Extra output format<br />
|-<br />
| <tt>MACC_VE_EXTRA_OUT_ALIGN</tt><br />
| <tt>29:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
</tt><br />
| Extra output alignment'', yet to figure out the exact values''<br />
|-<br />
| <tt>MACC_VE_EXTRA_OUT_SEC_OFF</tt><br />
| <tt>27:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt></tt><br />
| Offset for the second chroma plane<br />
|}<br />
<br />
== MACC_VE_VERSION ==<br />
Offset: 0x00f0<br />
<br />
Known values:<br />
* 0x16230055 (A10/A20)<br />
* 0x16250055 (A13)<br />
* 0x16330040 (A31s)<br />
* 0x16390028 (A80)<br />
* 0x16670040 (A33)<br />
* 0x16800040 (H3)<br />
* 0x16890040 (A64)<br />
<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_VE_VERSION_SOC</tt><br />
| <tt>16:31</tt><br />
| <tt>Read Only</tt><br />
| <tt>0x1625(a13)</tt><br />
| <tt><br />
Video Core IP Version<br />
0x1625 - A13<br />
0x1623 - A10/A20<br />
...<br />
</tt><br />
| VE IP version<br />
'''WARNING:''' In case of A10 and A13 match SoC Version, <br />
but seems AW stuff was too lazy to fix blob code for A20 production,<br />
thats means, A10/A20 use absolutly same VE Engine(A20 Also workable <br />
with A10 blob except cortex a8/a7 cache behavior difference).<br />
|-<br />
| <tt>MACC_VE_VERSION_<s>REV</s></tt><br />
| <tt>15:0</tt><br />
| <tt>Read Only</tt><br />
| <tt>0x0055(A13)</tt><br />
| <tt><br />
<br />
</tt><br />
| <s>IP revision(guess)</s><br />
|}<br />
<br />
= MPEG Engine Registers =<br />
<br />
== MACC_MPEG_PHDR ==<br />
Mostly from Picture_Coding_Extension<br />
<br />
<br />
Default value: 0x00000000<br /><br />
Offset: 0x0100<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_PHDR_TYPE</tt><br />
| <tt>31:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
<br />
MPEG picture_coding_type: <ref> ISO/IEC 13818-2 Page 53 Table 6-12 </ref><br />
0x0 = forbidden<br />
0x1 = I-Frame<br />
0x2 = P-Frame<br />
0x3 = B-Frame<br />
0x4 = D-Frame<br />
... = reserved<br />
<br />
</tt><br />
| Frame Type<br />
|-<br />
| <tt>MACC_MPEG_PHDR_FCODE_00</tt><br />
| <tt>27:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2 f_code[0][0] <br />
MPEG1: forward_f_code<br />
</tt><br />
| (4+ n)^2 - Mountion vector forward range<br />
|-<br />
| <tt>MACC_MPEG_PHDR_FCODE_01</tt><br />
| <tt>23:20</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: f_code[0][1] <br />
MPEG1: forward_f_code<br />
</tt><br />
| (4+ n)^2 - Mountion vector forward range<br />
|-<br />
| <tt>MACC_MPEG_PHDR_FCODE_10</tt><br />
| <tt>19:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: f_code[1][0] <br />
MPEG1: backward_f_code<br />
</tt><br />
| (4+ n)^2 - Mountion vector backward range<br />
|-<br />
| <tt>MACC_MPEG_PHDR_FCODE_11</tt><br />
| <tt>15:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: f_code[1][1] <br />
MPEG1: backward_f_code<br />
</tt><br />
| (4+ n)^2 - Mountion vector backward range<br />
|-<br />
| <tt>MACC_MPEG_PHDR_INTRA_DC_PREC</tt><br />
| <tt>11:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: intra_dc_precision<ref> ISO/IEC 13818-2 Page 54 Table 6-13 </ref>:<br />
00 - Precision (bits) 8<br />
01 - Precision (bits) 9<br />
10 - Precision (bits) 10<br />
11 - Precision (bits) 11<br />
<br />
MPEG1: 0x0<br />
</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_PIC_STRUCT</tt><br />
| <tt>9:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: picture_structure <ref> ISO/IEC 13818-2 Page 54 Table 6-14 </ref>:<br />
00 - reserved<br />
01 - top field<br />
00 - bottom field<br />
11 - frame picture<br />
<br />
MPEG1: always 0x3 (Frame picture)<br />
</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_TOP_FIRST</tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: top_field_first<ref> ISO/IEC 13818-2 Page 55</ref> <br />
MPEG1: always 0x1<br />
</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_FRAME_PRED</tt><br />
| <tt>6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
<br />
MPEG2: frame_pred_frame_dct<ref> ISO/IEC 13818-2 Page 55</ref> <br />
0 - not used <br />
1 - used<br />
MPEG1: always 1<br />
</tt><br />
| Is frame-DCT and frame prediction used<br />
|-<br />
| <tt>MACC_MPEG_PHDR_CON_MOTION</tt><br />
| <tt>5</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: concealment_motion_vectors<ref> ISO/IEC 13818-2 Page 55</ref><br />
0 - not coded<br />
1 - coded<br />
MPEG1: always 0<br />
</tt><br />
| Is montion vectors are coded for intral MB<br />
|-<br />
| <tt>MACC_MPEG_PHDR_Q_SCALE</tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt> <br />
MPEG2: q_scale_type <br />
MPEG1: always 0x0<br />
</tt><br />
|<br />
|-<br />
| <tt>MACC_MPEG_PHDR_INTRA_VLC</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: intra_vlc_format <br />
MPEG1: always 0x0</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_ALT_SCAN</tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG2: alternate_scan <br />
MPEG1: always 0x0</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_FULL_PEL_FWD</tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG1: full_pel_forward_vector <br />
MPEG2: always 0x0 by specification</tt><br />
| <br />
|-<br />
| <tt>MACC_MPEG_PHDR_FULL_PEL_BACK</tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG1: full_pel_backward_vector <br />
MPEG2: always 0x0 by specification</tt><br />
| <br />
|}<br />
<br />
== MACC_MPEG_VOPHDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0104<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| MPEG4 VOP Header<br />
|}<br />
<br />
== MACC_MPEG_SIZE ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0108<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_MPEG_SIZE_WIDTH</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture width in macroblocks (rounded up to multiple of 16 and divided by 16)<br />
|-<br />
| <tt>MACC_MPEG_SIZE_HEIGHT</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture height in macroblocks (rounded up to multiple of 16 and divided by 16)<br />
|}<br />
<br />
== MACC_MPEG_FRAME_SIZE ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x010c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_FRAME_SIZE_WIDTH</tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture width rounded up to multiple of 16<br />
|-<br />
| <tt>MACC_MPEG_FRAME_SIZE_HEIGHT</tt><br />
| <tt>15:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture height rounded up to multiple of 16<br />
|}<br />
<br />
== MACC_MPEG_MBA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0110<br />
<br />
MPEG4:<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unused<br />
|-<br />
| <tt></tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| MPEG4: Macroblock number in horizontal row (mb_x) of current picture slice<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| MPEG4: Macroblock number in vertical row (mb_y) of current picture slice<br />
|}<br />
<br />
MPEG2:<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Macroblock address location relative to previously coded MB in GOB, MBA = 1+(skipped MBs in GOB)<br />
|}<br />
<br />
== MACC_MPEG_CTRL ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0114<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:17</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_MPEG_CTRL_HISTOGRAM_EN</tt><br />
| <tt>16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable luma histogram output (see [[#MACC_VE_LUMA_HIST_VALi|MACC_VE_LUMA_HIST_VAL[0-15]]])<br />
|-<br />
| <tt></tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_MPEG_CTRL_IRQ_EN</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x0 - IRQ Disabled<br />
0x1 - IRQ Enabled<br />
</tt><br />
| IRQ enable flag(driver and blob use mask 0x7c for enable disable) <br />
|}<br />
<br />
== MACC_MPEG_TRIG ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0118<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_TRIG_ERROR_DISABLE</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x1 - disable <br />
0x0 - enable <br />
</tt><br />
| MPEG bitstream error handling<br />
|-<br />
|-<br />
| <tt></tt><br />
| <tt>30</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknow<br />
|-<br />
| <tt>MACC_MPEG_CTRL_COLOR_FMT</tt><br />
| <tt>29:27</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0x0 = YUV 4:2:0<br />
0x1 = YUV 4:1:1<br />
0x2 = YUV 4:2:2 horizontal<br />
0x3 = YUV 4:4:4<br />
0x4 = YUV 4:2:2 vertical<br />
0x5 = ???<br />
0x6 = ???<br />
0x7 = ???<br />
</tt><br />
| Input color format<br />
|-<br />
| <tt>MACC_MPEG_CTRL_FORMAT</tt><br />
| <tt>26:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
0x0 = reserved<br />
0x1 = MPEG1<br />
0x2 = MPEG2<br />
0x3 = JPEG<br />
0x4 = MPEG4<br />
0x5 = VP6<br />
0x6 = ???<br />
0x7 = ???<br />
</tt><br />
| Input data format<br />
|-<br />
| <tt>MACC_MPEG_CTRL_MB_NUM</tt><br />
| <tt>23:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Number of macroblock<br />
|-<br />
| <tt></tt><br />
| <tt>7:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown counter/offset(seen mpeg4)<br />
|-<br />
| <tt></tt><br />
| <tt>3:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEGs: 0xe<br />
JPEG: 0xd<br />
MS-MPEG: 0x7 or 0x5<br />
VP6: 0xf<br />
Mpeg bit-offset search 0x8<br />
</tt><br />
| Trigger bits, exact function unknown<br />
|}<br />
<br />
== MACC_MPEG_STATUS ==<br />
Default value: 0x0000c000<br /><br />
Offset: 0x011c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_STATUS_FINISH</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Mpeg finish flag<br />
|-<br />
|-<br />
| <tt></tt><br />
| <tt>30:14</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_MPEG_STATUS_MC_FREE</tt><br />
| <tt>13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mc free status<br />
|-<br />
| <tt>MACC_MPEG_STATUS_BUSY</tt><br />
| <tt>12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Mpeg engine busyness status<br />
|-<br />
| <tt>MACC_MPEG_STATUS_IDCT_IN_EMPTY</tt><br />
| <tt>11</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Inverse discrete cosine transform input empty<br />
|-<br />
| <tt>MACC_MPEG_STATUS_IDQT_IN_EMPTY</tt><br />
| <tt>10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Inverse quantization and inverse scan input empty<br />
|-<br />
| <tt></tt><br />
| <tt>9:5</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknow<br />
<br />
|-<br />
| <tt>MACC_MPEG_STATUS_BITSFUNC_FREE</tt><br />
| <tt>6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Unknown (VP6 related)<br />
|-<br />
<br />
| <tt></tt><br />
| <tt>5:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_FRAME_DIST ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0120<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt> <br />
MPEG1: always 0(initialy)<br />
</tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_TRBTRDFLD ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0124<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG1: always 0x3(initialy)<br />
</tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_VLD_ADDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0128<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
MPEG - 0x5<br />
JPEG - 0x7<br />
</tt><br />
| the 0x7 flag is used for both MPEG and JPEG decoding<br />
|-<br />
| <tt></tt><br />
| <tt>27:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
27:4 VLD Address bits<br />
</tt><br />
| VLD Address LOW bits (for first bits dropped from address)<br />
|-<br />
| <tt></tt><br />
| <tt>3:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
31:28 VLD Address bits (for addesses beyond 256 MB)<br />
</tt><br />
| VLD Address HI bits<br />
|}<br />
<br />
== MACC_MPEG_VLD_OFFSET ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x012c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_VLD_OFFSET</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VLD Offset in bits - current frame offset from VLD start address<br />
|}<br />
<br />
== MACC_MPEG_VLD_LEN ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0130<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_VLD_LEN</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VLD Length in bits - source video size<br />
|}<br />
<br />
== MACC_MPEG_VBV_END ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0134<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Source video buffer last address <br />
|}<br />
<br />
== MACC_MPEG_MBH_ADDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0138<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| macro block hdr info<br />
|}<br />
<br />
== MACC_MPEG_DCAC_ADDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x013c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_BLK_OFFSET ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0140<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_NCF_ADDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0144<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_REC_LUMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0148<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_REC_LUMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Luma Reconstruct Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_REC_CHROMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x014c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_REC_CHROMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Chroma Reconstruct Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_FWD_LUMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0150<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_FWD_LUMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Luma Forward Prediction Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_FWD_CHROMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0154<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_FWD_CHROMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Chroma Forward Prediction Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_BACK_LUMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0158<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_BACK_LUMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Luma Backward Prediction Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_BACK_CHROMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x015c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_BACK_CHROMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Chroma Backward Prediction Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_SOCX ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0160<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SOCY ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0164<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SOL ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0168<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SDLX ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x016c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SDLY ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0170<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SPRITESHFT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0174<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SDCX ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0178<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SDCY ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x017c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_IQ_MIN_INPUT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0180<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Used for load IQ table for MPEG2/JPEG decoding, after write value automaticly moves to some v-sram<br />
|}<br />
<br />
== MACC_MPEG_IQ_INPUT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0184<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MSMPEG4_HDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0188<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_VP6_HDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x018c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_IQ_IDCT_INPUT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0190<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_HEIGHT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0194<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V1 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0198<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V2 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x019c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V3 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01a0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V4 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01a4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V5 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01a8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V6 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01ac<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V7 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01b0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_MB_V8 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01b4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_JPEG_SIZE ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01b8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_JPEG_SIZE_HEIGHT</tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0000</tt><br />
| <tt><br />
0 = 1 MCU<br />
1 = 2 MCU<br />
...<br />
</tt><br />
| Height in MCUs<br />
|-<br />
| <tt>MACC_MPEG_JPEG_SIZE_WIDTH</tt><br />
| <tt>15:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0000</tt><br />
| <tt><br />
0 = 1 MCU<br />
1 = 2 MCU<br />
...<br />
</tt><br />
| Width in MCUs<br />
|}<br />
<br />
== MACC_MPEG_JPEG_MCU ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01bc<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_JPEG_RES_INT ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01c0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_JPEG_RES_INT</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt>0x0</tt><br />
| <tt><br />
DRI marker<br />
</tt><br />
| JPEG Restart Interval<br />
|}<br />
<br />
== MACC_MPEG_ERROR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01c4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| (guess)Must return error code in some error cases <br />
|}<br />
<br />
== MACC_MPEG_CTR_MB ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01c8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_ROT_LUMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01cc<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_ROT_LUMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Luma Rotate/Scale Output Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_ROT_CHROMA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01d0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_ROT_CHROMA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Chroma Rotate/Scale Output Buffer Address (must be 1KB aligned)<br />
|}<br />
<br />
== MACC_MPEG_ROTSCALE_CTRL ==<br />
<br />
<br />
Used for control Rotate/Scale buffer<br />
<br />
<br />
Default value: 0x00000000<br /><br />
Offset: 0x01d4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_MPEG_EXTRA_FUNC_SCALE_Y</tt><br />
| <tt>11:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x0 = /1 (full size)<br />
0x1 = /2<br />
0x2 = /4<br />
0x3 = /8<br />
</tt><br />
| Downscale y<br />
|-<br />
| <tt>MACC_MPEG_EXTRA_FUNC_SCALE_X</tt><br />
| <tt>9:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x0 = /1 (full size)<br />
0x1 = /2<br />
0x2 = /4<br />
0x3 = /8<br />
</tt><br />
| Downscale x<br />
|-<br />
| <tt></tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_JPEG_MCU_START ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01d8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_JPEG_MCU_END ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01dc<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_MPEG_SRAM_RW_OFFSET ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01e0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Used for reload huffman table(JPEG decoding)<br />
|}<br />
<br />
== MACC_MPEG_SRAM_RW_DATA ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x01e4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Used for Huffman table load procedure in JPEG-decoding process<br />
|}<br />
<br />
Map for Jpeg decoding process:<br />
<br />
Cedar Huffman Tables are 2KiB of data written through this register.<br />
First half contains description of Huffman-tree, second half contains the data.<br />
<br />
+----------+----------+----------+----------+---- - - - ---------- - - - ---------- - - - -----+<br />
| LumaDC | LumaAC | ChromaDC | ChromaAC | Filled with zero (maybe more trees are possible) |<br />
| 64 bytes | 64 bytes | 64 bytes | 64 bytes | 768 bytes |<br />
+----------+----------+----------+----------+---- - - - -----+---- - - - -----+---- - - - -----+<br />
| Luma DC Data | Luma AC Data | Chroma DC Data | Chroma AC Data |<br />
| 256 bytes | 256 bytes | 256 bytes | 256 bytes |<br />
+-------------------------------------------+---- - - - -----+---- - - - -----+---- - - - -----+<br />
<br />
Each of the 64 byte tree-description has the following format:<br />
First 16 halfwords: first bitstream used for datacodes in corresponding depth (or 0xffff if no more data)<br />
Next 16 bytes: offset in data section for corresponding depth<br />
Rest (16 bytes): Filled with zero<br />
<br />
The 256 byte data sections contain the codes in same format as in JPEG.<br />
<br />
== MACC_MPEG_START_CODE_BITOFFSET ==<br />
Default value: UNDEF <br /><br />
Offset: 0x01f0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_MPEG_START_CODE_BITOFFSET </tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Used as result register for mpeg2 entry offset search procedure<br />
|}<br />
<br />
= H264 Engine Registers =<br />
<br />
== MACC_H264_SEQ_HDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0200<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:22</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_CHROMA_FORMAT</tt><br />
| <tt>21:19</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
chroma_format_idc</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_FRAME_MBS_ONLY</tt><br />
| <tt>18</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
frame_mbs_only_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_MB_ADAPTIVE</tt><br />
| <tt>17</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
mb_adaptive_frame_field_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_DIRECT_8X8</tt><br />
| <tt>16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
direct_8x8_inference_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_PIC_WIDTH</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
pic_width_in_mbs_minus1</tt><br />
| Width in macroblocks - 1<br />
|-<br />
| <tt>MACC_H264_SEQ_HEADER_PIC_HEIGHT</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
pic_height_in_map_units_minus1</tt><br />
| Height in map units - 1<br />
|}<br />
<br />
== MACC_H264_PIC_HDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0204<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_PIC_HDR_ENTROPY_CODING</tt><br />
| <tt>15</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
entropy_coding_mode_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_NUM_REF_IDX_L0</tt><br />
| <tt>14:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
num_ref_idx_l0_default_active_minus1</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_NUM_REF_IDX_L1</tt><br />
| <tt>9:5</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
num_ref_idx_l1_default_active_minus1</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_WEIGHTED_PRED</tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
weighted_pred_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_WEIGHTED_BIPRED</tt><br />
| <tt>3:2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
weighted_bipred_idc</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_CONST_INTRA_PRED</tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
constrained_intra_pred_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_PIC_HDR_TRANSFORM_8X8</tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
transform_8x8_mode_flag</tt><br />
| <br />
|}<br />
<br />
== MACC_H264_SLICE_HDR ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x0208<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_FIRST_MB_X</tt><br />
| <tt>31:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
first_mb_in_slice % pic_width_in_mbs</tt><br />
| First Macroblock in slice (x-coordinate)<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_FIRST_MB_Y</tt><br />
| <tt>23:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
first_mb_in_slice / pic_width_in_mbs<br />
( * 2 if mbaff)</tt><br />
| First Macroblock in slice (y-coordinate)<br />
|-<br />
| <tt></tt><br />
| <tt>15:13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_IS_REFERENCE</tt><br />
| <tt>12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = no reference<br />
1 = reference</tt><br />
| This frame will be used as reference<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_TYPE</tt><br />
| <tt>11:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x0 = P<br />
0x1 = B<br />
0x2 = I</tt><br />
| Slice type<br />
|-<br />
| <tt></tt><br />
| <tt>7:6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_FIRST_IN_PICTURE</tt><br />
| <tt>5</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = further<br />
1 = first</tt><br />
| First slice in Picture<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_FIELD_PIC</tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
field_pic_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_BOTTOM_FIELD</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
bottom_field_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_DIRECT_SPAT_MV_PRED</tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
direct_spatial_mv_pred_flag</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_CABAC_INIT</tt><br />
| <tt>1:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
cabac_init_idc</tt><br />
| <br />
|}<br />
<br />
== MACC_H264_SLICE_HDR2 ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x020c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:29</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_NUM_REF_IDX_L0</tt><br />
| <tt>28:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
num_ref_idx_l0_active_minus1</tt><br />
| only used if override flag is set<br />
|-<br />
| <tt></tt><br />
| <tt>23:21</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_NUM_REF_IDX_L1</tt><br />
| <tt>20:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
num_ref_idx_l1_active_minus1</tt><br />
| only used if override flag is set<br />
|-<br />
| <tt></tt><br />
| <tt>15:13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_NUM_REF_IDX_OVERRIDE</tt><br />
| <tt>12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
num_ref_idx_active_override_flag</tt><br />
| <br />
|-<br />
| <tt></tt><br />
| <tt>11:10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_DEBLOCKING</tt><br />
| <tt>9:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
disable_deblocking_filter_idc</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_ALPHA_OFFSET</tt><br />
| <tt>7:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
slice_alpha_c0_offset_div2</tt><br />
| <br />
|-<br />
| <tt>MACC_H264_SLICE_HDR_BETA_OFFSET</tt><br />
| <tt>3:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
slice_beta_offset_div2</tt><br />
| <br />
|}<br />
<br />
== MACC_H264_PRED_WEIGHT ==<br />
Default value: <br /><br />
Offset: 0x0210<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_PRED_WEIGHT_CHROMA_DENOM</tt><br />
| <tt>6:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
chroma_log2_weight_denom</tt><br />
| <br />
|-<br />
| <tt></tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_PRED_WEIGHT_LUMA_DENOM</tt><br />
| <tt>2:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
luma_log2_weight_denom</tt><br />
| <br />
|}<br />
<br />
== MACC_H264_VP8_HDR ==<br />
Default value: <br /><br />
Offset: 0x0214<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_FRAME_TYPE</tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = KEY_FRAME<br />
1 = INTER_FRAME<br />
</tt><br />
| current frame_type<br />
|-<br />
| <tt>MACC_H264_LAST_FRAME_SHARPNESS_LEVEL</tt><br />
| <tt>30:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| last frame sharpness_level<br />
|-<br />
| <tt>MACC_H264_LAST_FRAME_TYPE</tt><br />
| <tt>27</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = KEY_FRAME<br />
1 = INTER_FRAME<br />
</tt><br />
| last frame frame_type<br />
|-<br />
| <tt>MACC_H264_REF_FRAME_SIGN_BIAS_ALTREF_FRAME</tt><br />
| <tt>26</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_frame_sign_bias for ALTREF_FRAME<br />
|-<br />
| <tt>MACC_H264_REF_FRAME_SIGN_BIAS_GOLDEN_FRAME</tt><br />
| <tt>25</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_frame_sign_bias for GOLDEN_FRAME<br />
|-<br />
| <tt></tt><br />
| <tt>24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reload_entropy_probs, allways set to 1<br />
|-<br />
| <tt>MACC_H264_REFRESH_ENTROPY_PROBS</tt><br />
| <tt>23</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| refresh_entropy_probs<br />
|-<br />
| <tt>MACC_H264_MB_NO_COEFF_SKIP</tt><br />
| <tt>22</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mb_no_coeff_skip<br />
|-<br />
| <tt>MACC_H264_TOKEN_PARTITION_NUMBER</tt><br />
| <tt>21:20</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = ONE_PARTITION<br />
1 = TWO_PARTITION<br />
2 = FOUR_PARTITION<br />
3 = EIGHT_PARTITION<br />
</tt><br />
| number of token partitions<br />
|-<br />
| <tt>MACC_H264_MODE_REF_LF_DELTA_UPDATE</tt><br />
| <tt>19</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_ref_lf_delta_update<br />
|-<br />
| <tt>MACC_H264_MODE_REF_LF_DELTA_ENABLED</tt><br />
| <tt>18</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_ref_lf_delta_enabled <br />
|-<br />
| <tt>MACC_H264_FILTER_LEVEL</tt><br />
| <tt>17:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| current frame filter_level<br />
|-<br />
| <tt>MACC_H264_FILTER_TYPE</tt><br />
| <tt>11</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = NORMAL_LOOPFILTER<br />
1 = SIMPLE_LOOPFILTER<br />
</tt><br />
| current frame filter_type <br />
|-<br />
| <tt>MACC_H264_SHARPNESS_LEVEL</tt><br />
| <tt>10:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| sharpness_level<br />
|-<br />
| <tt>MACC_H264_LAST_FRAME_FILTER_TYPE</tt><br />
| <tt>7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = NORMAL_LOOPFILTER<br />
1 = SIMPLE_LOOPFILTER<br />
</tt><br />
| last frame filter_type<br />
|-<br />
| <tt>MACC_H264_SEGMENTATION_ENABLED</tt><br />
| <tt>6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segmentation_enabled<br />
|-<br />
| <tt>MACC_H264_MB_SEGMENT_ABS_DELTA</tt><br />
| <tt>5</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mb_segement_abs_delta<br />
|-<br />
| <tt>MACC_H264_UPDATE_MB_SEGMENTATION_MAP</tt><br />
| <tt>4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| update_mb_segmentation_map<br />
|-<br />
| <tt>MACC_H264_FULL_PIXEL</tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| full_pixel (VP8 version)<br />
|-<br />
| <tt>MACC_H264_USE_BILLENAR_MC_FILTER</tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| use_billenar_mc_filter (VP8 version)<br />
|-<br />
| <tt>MACC_H264_FILTER_TYPE</tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = NORMAL_LOOPFILTER<br />
1 = SIMPLE_LOOPFILTER<br />
</tt><br />
| filter_type (VP8 version)<br />
|-<br />
| <tt>MACC_H264_NO_LPF</tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| no_lpf (VP8 version)<br />
|}<br />
<br />
==MACC_H264_QINDEX==<br />
Default value: <br /><br />
Offset: 0x0218<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_UVAC_DELTA_Q</tt><br />
| <tt>31:27</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| uvac_delta_q<br />
|-<br />
| <tt>MACC_H264_UVDC_DELTA_Q</tt><br />
| <tt>26:22</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| uvdc_delta_q<br />
|-<br />
| <tt>MACC_H264_Y2AC_DELTA_Q</tt><br />
| <tt>21:17</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| y2ac_delta_q<br />
|-<br />
| <tt>MACC_H264_Y2DC_DELTA_Q</tt><br />
| <tt>16:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| y2dc_delta_q<br />
|-<br />
| <tt>MACC_H264_Y1DC_DELTA_Q</tt><br />
| <tt>11:7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| y1dc_delta_q<br />
|-<br />
| <tt>MACC_H264_BASE_QINDEX</tt><br />
| <tt>6:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| base_qindex<br />
|}<br />
<br />
== MACC_H264_QP ==<br />
Default value: 0x00000000<br /><br />
Offset: 0x021c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:25</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MACC_H264_QP_DEFAULT_SCALING_MATRIX</tt><br />
| <tt>24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = custom<br />
1 = default</tt><br />
| scaling matrix to use<br />
|-<br />
| <tt></tt><br />
| <tt>23:22</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_QP_SECOND_CHROMA_QP_OFFSET</tt><br />
| <tt>21:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
second_chroma_qp_index_offset</tt><br />
| <br />
|-<br />
| <tt></tt><br />
| <tt>15:14</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_QP_CHROMA_QP_OFFSET</tt><br />
| <tt>13:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
chroma_qp_index_offset</tt><br />
| <br />
|-<br />
| <tt></tt><br />
| <tt>7:6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt>MACC_H264_QP_PARAM</tt><br />
| <tt>5:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
pic_init_qp + slice_qp_delta</tt><br />
| <br />
|}<br />
<br />
== MACC_H264_CTRL ==<br />
Default value: <br /><br />
Offset: 0x0220<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:30</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved5<br />
|-<br />
| <tt></tt><br />
| <tt>29</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| isVP8Dec<br />
|-<br />
| <tt></tt><br />
| <tt>28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| isAVS<br />
|-<br />
| <tt></tt><br />
| <tt>27</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved4<br />
|-<br />
| <tt></tt><br />
| <tt>26</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| AVS_Demulate_Enable<br />
|-<br />
| <tt>MACC_H264_CTRL_STARTCODE_DETECT_EN</tt><br />
| <tt>25</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable start code detection<br />
|-<br />
| <tt></tt><br />
| <tt>24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| eptb_detection_bypass<br />
|-<br />
| <tt></tt><br />
| <tt>14:23</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved0<br />
|-<br />
| <tt>MACC_H264_CTRL_HISTOGRAM_EN</tt><br />
| <tt>13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0 = disabled<br />
1 = enabled</tt><br />
| Enable luma histogram output (see [[#MACC_VE_LUMA_HIST_VALi|MACC_VE_LUMA_HIST_VAL[0-15]]])<br />
|-<br />
| <tt></tt><br />
| <tt>11:12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved1<br />
|-<br />
| <tt></tt><br />
| <tt>10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mcri_cache_enable<br />
|-<br />
| <tt></tt><br />
| <tt>9</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| write_rotated_pic_flag<br />
|-<br />
| <tt></tt><br />
| <tt>8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| not_write_recons_pic_flag<br />
|-<br />
| <tt></tt><br />
| <tt>3:7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved0<br />
|-<br />
| <tt></tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| vld_data_req_int_en IRQ <br />
|-<br />
| <tt></tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| dec_error_int_en IRQ<br />
|-<br />
| <tt></tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| slice_dec_finish_int_en IRQ<br />
<br />
|}<br />
<br />
== MACC_H264_TRIG ==<br />
Default value: <br /><br />
Offset: 0x0224<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Parameter , n_bits<br />
|-<br />
| <tt></tt><br />
| <tt>7:6</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| reserved<br />
|-<br />
| <tt></tt><br />
| <tt>5:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| stcd_type<br />
|-<br />
| <tt>MACC_H264_TRIG_FUNCTION</tt><br />
| <tt>3:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x0 = ?<br />
0x1 = ?<br />
0x2 = read basic bits<br />
0x3 = ?<br />
0x4 = read exp-golomb coded signed integer<br />
0x5 = read exp-golomb coded unsigned integer<br />
0x6 = ?<br />
0x7 = ? (maybe reset or init)<br />
0x8 = start decoding one H.264 slice<br />
0x9 = ?<br />
0xa = start decoding VP8 frame<br />
... = ?<br />
0xe = start reading coef_probs to entropy <br />
probabilities table using VP8 bool decoder<br />
0xf = read bits to MACC_H264_BASIC_BITS_DATA<br />
using VP8 bool decoder, where <br />
31:24 - probability<br />
18:16 - (bits_count - 1)</tt><br />
| Function<br />
|}<br />
<br />
== MACC_H264_STATUS ==<br />
Default value: <br /><br />
Offset: 0x0228<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| startcode detected<br />
|-<br />
| <tt></tt><br />
| <tt>30:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| start code type<br />
|-<br />
| <tt></tt><br />
| <tt>27</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| stcd_busy<br />
|-<br />
| <tt></tt><br />
| <tt>26</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>25</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| avs_idct_busy<br />
|-<br />
| <tt></tt><br />
| <tt>24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| avs_busy<br />
|-<br />
| <tt></tt><br />
| <tt>23</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| wb_busy<br />
|-<br />
| <tt></tt><br />
| <tt>22</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| bs_dma_busy<br />
|-<br />
| <tt></tt><br />
| <tt>21</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| it_busy<br />
|-<br />
| <tt></tt><br />
| <tt>20</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| intram_busy<br />
|-<br />
| <tt></tt><br />
| <tt>19</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>18</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| vp8_busy<br />
|-<br />
| <tt></tt><br />
| <tt>17</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| vp8_upprob_busy <br />
|-<br />
| <tt></tt><br />
| <tt>16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| more_data_flag<br />
|-<br />
| <tt></tt><br />
| <tt>15</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| dblk_busy<br />
|-<br />
| <tt></tt><br />
| <tt>14</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
|irec_busy<br />
|-<br />
| <tt></tt><br />
| <tt>13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
|intra_pred_busy<br />
|-<br />
| <tt></tt><br />
| <tt>12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
|mcri_busy<br />
|-<br />
| <tt></tt><br />
| <tt>11</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
|iq_it_bust <br />
|-<br />
| <tt></tt><br />
| <tt>10</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
|mvp_busy<br />
|-<br />
| <tt></tt><br />
| <tt>9</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| is_busy<br />
|-<br />
| <tt></tt><br />
| <tt>8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| vld_busy<br />
|-<br />
| <tt></tt><br />
| <tt>7:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| over_time_interrupt<br />
|-<br />
| <tt></tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| vld_data_req_interrupt<br />
|-<br />
| <tt></tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| decode_error_interrupt<br />
|-<br />
| <tt></tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| slice_decode_finish_interrupt <br />
|}<br />
<br />
== MACC_H264_CUR_MBNUM ==<br />
Default value: <br /><br />
Offset: 0x022c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_CUR_MBNUM</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| current decoded macroblock nr.<br />
|}<br />
<br />
== MACC_H264_VLD_ADDR ==<br />
Default value: <br /><br />
Offset: 0x0230<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>30</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x1 for h.264 and VP8</tt><br />
| first_slice_data<br />
|-<br />
| <tt></tt><br />
| <tt>29</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x1 for h.264 and VP8</tt><br />
| last_slice_data<br />
|-<br />
| <tt></tt><br />
| <tt>28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
0x1 for h.264 and VP8</tt><br />
| slice_data_valid<br />
|-<br />
| <tt></tt><br />
| <tt>27:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
27:4 VLD Address bits</tt><br />
| VLD Address LOW bits (four first bits dropped from address)<br />
|-<br />
| <tt></tt><br />
| <tt>3:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt><br />
31:28 VLD Address bits (for addesses beyond 256 MB)</tt><br />
| VLD Address HI bits<br />
|}<br />
<br />
== MACC_H264_VLD_OFFSET ==<br />
Default value: <br /><br />
Offset: 0x0234<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_VLD_OFFSET</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VLD Offset in bits<br />
|}<br />
<br />
== MACC_H264_VLD_LEN ==<br />
Default value: <br /><br />
Offset: 0x0238<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_VLD_LEN</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VLD Length in bits<br />
|}<br />
<br />
== MACC_H264_VLD_END ==<br />
Default value: <br /><br />
Offset: 0x023c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MAC_H264_VLD_END</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VLD End Address <br />
|}<br />
== MACC_H264_SDROT_CTRL ==<br />
Default value: <br /><br />
Offset: 0x0240<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>14:31</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| r0<br />
|-<br />
| <tt></tt><br />
| <tt>13</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| bottom_field_sel <br />
|-<br />
| <tt></tt><br />
| <tt>12</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| field_scale_mode<br />
|-<br />
| <tt></tt><br />
| <tt>8:11</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| scale_precision <br />
|-<br />
| <tt></tt><br />
| <tt>3:7</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| r1<br />
|-<br />
| <tt></tt><br />
| <tt>0:2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| rot_angle<br />
|}<br />
<br />
== MACC_H264_OUTPUT_FRAME_INDEX ==<br />
Default value: <br /><br />
Offset: 0x024c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MAC_H264_OUTPUT_FRAME_INDEX</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Output frame index in dpb<br />
|}<br />
<br />
== MACC_H264_VP8_ENTROPY_PROBS ==<br />
Default value: <br /><br />
Offset: 0x024c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MAC_H264_ENTROPY_PROBS_TABLE_ADDRESS</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Entropy probabilities table address<br />
|}<br />
<br />
Size of entropy probabilities table is defined as 0x2400, but only first 0x11b0 bytes are used.</br><br />
The table contents buffer is null'ed after allocation and reused for every decoded frame.</br><br />
Memory layout of entropy probabilities table:<br />
0x000 - 0x7ff : coef_probs (BLOCK_TYPES are 512 bytes aligned,<br />
COEF_BANDS are 64 bytes aligned,<br />
PREV_COEF_CONTEXTS are 16 bytes aligned)<br />
0x800 - 0xfff : vp8_coef_update_probs (BLOCK_TYPES are 512 bytes aligned,<br />
COEF_BANDS are 64 bytes aligned,<br />
PREV_COEF_CONTEXTS are 16 bytes aligned)<br />
0x1000 - 0x1003: vp8_kf_ymode_prob<br />
0x1008 - 0x100b: ymode_prob<br />
0x1010 - 0x1012: uv_mode_prob or vp8_kf_uv_mode_prob depending on frame type<br />
0x1018 - 0x101a: mb_segment_tree_probs<br />
0x101c : prob_skip_false<br />
0x101d : prob_intra<br />
0x101e : prob_last<br />
0x101f : prob_gf<br />
0x1020 - 0x1032: mvc[0].prob<br />
0x1040 - 0x1052: mvc[1].prob<br />
0x1060 - 0x1062: vp8_mbsplit_probs<br />
0x1068 - 0x1070: vp8_bmode_prob<br />
0x1088 - 0x109b: vp8_sub_mv_ref_prob2 (4 bytes aligned)<br />
0x10a8 - 0x10bf: vp8_mode_contexts (4 bytes aligned)<br />
0x1100 - 0x1107: vp8_kf_ymode_tree<br />
0x1108 - 0x110f: vp8_ymode_tree<br />
0x1110 - 0x1115: vp8_uv_mode_tree<br />
0x1122 - 0x112f: vp8_small_mvtree<br />
0x1142 - 0x114f: vp8_small_mvtree (again)<br />
0x1160 - 0x1165: vp8_mbsplit_tree<br />
0x1168 - 0x1179: vp8_bmode_tree<br />
0x1188 - 0x118d: vp8_sub_mv_ref_tree<br />
0x11a8 - 0x11af: vp8_mv_ref_tree<br />
<br />
All trees should be in signed magnitude representation, e.g. <br />
table[0x1168] = (vp8_bmode_tree[0] <= 0)?(128-vp8_bmode_tree[0]):vp8_bmode_tree[0];<br />
<br />
== MACC_H264_VP8_FSTDATA_PARTLEN ==<br />
Default value: <br /><br />
Offset: 0x0254<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:28</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>27:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| First partition length in bits<br />
|}<br />
<br />
== MACC_H264_PIC_MBSIZE ==<br />
Default value: <br /><br />
Offset: 0x0258<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MAC_H264_HORIZONTAL_MACROBLOCK_COUNT</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VP8: number of horizontal macroblocks (Y dimensions)<br />
|-<br />
| <tt>MAC_H264_VERTICAL_MACROBLOCK_COUNT</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| VP8: number of vertical macroblocks (Y dimensions)<br />
|}<br />
<br />
For VP8:<br />
MAC_H264_HORIZONTAL_MACROBLOCK_COUNT = (frame_width + 15)/16<br />
MAC_H264_VERTICAL_MACROBLOCK_COUNT = (frame_height + 15)/16<br />
<br />
== MACC_H264_PIC_BOUNDARYSIZE ==<br />
Default value: <br /><br />
Offset: 0x025c<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MAC_H264_PICTURE_WIDTH</tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture width in pixels<br />
|-<br />
| <tt>MAC_H264_PICTURE_HEIGHT</tt><br />
| <tt>15:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Picture height in pixels<br />
|}<br />
<br />
== MACC_H264_MB_ADDR ==<br />
Default value: <br /><br />
Offset: 0x0260<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|-<br />
| <tt>MAC_H264_HORIZONTAL_MACROBLOCK_POSITION</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| current decoded macroblock horizontal position<br />
|-<br />
| <tt>MAC_H264_VERTICAL_MACROBLOCK_POSITION</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| current decoded macroblock vertical position<br />
|}<br />
<br />
== MACC_H264_REC_LUMA ==<br />
Default value: <br /><br />
Offset: 0x02ac<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Reconstruct Buffer luma color component<br />
|}<br />
<br />
== MACC_H264_FWD_LUMA ==<br />
Default value: <br /><br />
Offset: 0x02b0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Forward prediction buffer (last frame buffer for VP8) luma color component<br />
|}<br />
<br />
== MACC_H264_BACK_LUMA ==<br />
Default value: <br /><br />
Offset: 0x02b4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Back buffer (golden frame buffer for VP8) luma color component<br />
|}<br />
<br />
== MACC_H264_ERROR ==<br />
Default value: <br /><br />
Offset: 0x02b8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:4</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ''reserved''<br />
|-<br />
| <tt></tt><br />
| <tt>3</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| block_error<br />
|-<br />
| <tt></tt><br />
| <tt>2</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_idx_error<br />
|-<br />
| <tt></tt><br />
| <tt>1</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mbh_error<br />
|-<br />
| <tt></tt><br />
| <tt>0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| no_more_data_error<br />
|}<br />
<br />
== MACC_H264_REC_CHROMA ==<br />
Default value: <br /><br />
Offset: 0x02d0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Reconstruct buffer chroma color component<br />
|}<br />
<br />
== MACC_H264_FWD_CHROMA ==<br />
Default value: <br /><br />
Offset: 0x02d4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Forward prediction buffer (last frame buffer for VP8) chroma color component<br />
|}<br />
<br />
== MACC_H264_BACK_CHROMA ==<br />
Default value: <br /><br />
Offset: 0x02d8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Back buffer (golden frame buffer for VP8) chroma color component<br />
|}<br />
<br />
== MACC_H264_BASIC_BITS_DATA ==<br />
Default value: <br /><br />
Offset: 0x02dc<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| unknown<br />
|}<br />
<br />
== MACC_H264_RAM_WRITE_PTR ==<br />
Default value: <br /><br />
Offset: 0x02e0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_RAM_WRITE_PTR</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| relative (to?) address to write to (auto incrementing)<br />
|}<br />
<br />
== MACC_H264_RAM_WRITE_DATA ==<br />
Default value: <br /><br />
Offset: 0x2e4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_RAM_WRITE_DATA</tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Data to write to VE-SRAM at address pointed to by MACC_H264_RAM_WRITE_PTR<br />
|}<br />
<br />
Memory layout for h.264 decoding:<br />
0x000 - 0x2ff: Prediction weight table<br />
0x400 - 0x63f: Framebuffer list<br />
0x640 - ? : Reference Picture list 0<br />
0x664 - ? : Reference Picture list 1<br />
0x800 - 0x8df: Scaling lists<br />
<br />
Prediction weight table:<br />
uint32_t luma_l0[32];<br />
uint32_t chroma_l0[32][2];<br />
uint32_t luma_l1[32];<br />
uint32_t chroma_l1[32][2];<br />
<br />
each has bit 24:16 = signed offset<br />
bit 8:0 = signed weight<br />
<br />
Framebuffer list:<br />
struct {<br />
uint32_t top_pic_order_cnt;<br />
uint32_t bottom_pic_order_cnt;<br />
uint32_t flags; // bit 0-1: top ref type: 0x0 = short, 0x1 = long, 0x2 = no ref<br />
// bit 4-5: bottom ref type: 0x0 = short, 0x1 = long, 0x2 = no ref<br />
// bit 8-9: picture type: 0x0 = frame, 0x1 = field, 0x2 = mbaff<br />
uint32_t luma_addr;<br />
uint32_t chroma_addr;<br />
uint32_t extra_buffer_top_addr; // prediction buffers?<br />
uint32_t extra_buffer_bottom_addr; // size = pic_width_in_mbs * pic_height_in_mbs * 32<br />
uint32_t unknown; // = 0x0<br />
} framebuffer_list[18];<br />
<br />
Reference Picture lists:<br />
uint8_t ref_picture[?]; // (index to framebuffer list) * 2 + (bottom_field ? 1 : 0)<br />
<br />
Scaling lists:<br />
uint8_t ScalingList8x8[2][64];<br />
uint8_t ScalingList4x4[6][16];<br />
<br />
== MACC_H264_ALT_LUMA ==<br />
Default value: <br /><br />
Offset: 0x02e8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Alternative buffer (altref frame buffer for VP8) luma color component<br />
|}<br />
<br />
== MACC_H264_ALT_CHROMA ==<br />
Default value: <br /><br />
Offset: 0x02ec<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt></tt><br />
| <tt>31:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| Alternative buffer (altref frame buffer for VP8) chroma color component<br />
|}<br />
<br />
== MACC_H264_SEG_MB_LV0 ==<br />
Default value: <br /><br />
Offset: 0x02f0<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV0_4</tt><br />
| <tt>31:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[0][3]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV0_3</tt><br />
| <tt>23:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[0][2]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV0_2</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[0][1]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV0_1</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[0][0]<br />
|}<br />
<br />
== MACC_H264_SEG_MB_LV1 ==<br />
Default value: <br /><br />
Offset: 0x02f4<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV1_4</tt><br />
| <tt>31:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[1][3]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV1_3</tt><br />
| <tt>23:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[1][2]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV1_2</tt><br />
| <tt>15:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[1][1]<br />
|-<br />
| <tt>MACC_H264_SEGMENT_MB_LV1_1</tt><br />
| <tt>7:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| segment_feature_data[1][0]<br />
|}<br />
<br />
== MACC_H264_REF_LF_DELTA ==<br />
Default value: <br /><br />
Offset: 0x02f8<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_REF_LF_DELTA_4</tt><br />
| <tt>30:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_lf_deltas[3]<br />
|-<br />
| <tt>MACC_H264_REF_LF_DELTA_3</tt><br />
| <tt>22:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_lf_deltas[2]<br />
|-<br />
| <tt>MACC_H264_REF_LF_DELTA_2</tt><br />
| <tt>14:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_lf_deltas[1]<br />
|-<br />
| <tt>MACC_H264_REF_LF_DELTA_1</tt><br />
| <tt>6:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| ref_lf_deltas[0]<br />
|}<br />
<br />
== MACC_H264_MODE_LF_DELTA ==<br />
Default value: <br /><br />
Offset: 0x02fc<br />
{| class="wikitable" |<br />
! Name<br />
! Bit<br />
! Read/Write<br />
! Default (Hex)<br />
! Values<br />
! Description<br />
|-<br />
| <tt>MACC_H264_MODE_LF_DELTA_4</tt><br />
| <tt>30:24</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_lf_deltas[3]<br />
|-<br />
| <tt>MACC_H264_MODE_LF_DELTA_3</tt><br />
| <tt>22:16</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_lf_deltas[2]<br />
|-<br />
| <tt>MACC_H264_MODE_LF_DELTA_2</tt><br />
| <tt>14:8</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_lf_deltas[1]<br />
|-<br />
| <tt>MACC_H264_MODE_LF_DELTA_1</tt><br />
| <tt>6:0</tt><br />
| <tt>Read/Write</tt><br />
| <tt></tt><br />
| <tt></tt><br />
| mode_lf_deltas[0]<br />
|}<br />
<br />
= HEVC Engine Register =<br />
<br />
== MACC_HEVC_NAL_HDR ==<br />
{{REG|MACC_HEVC_NAL_HDR|offset=0x500|<br />
{{REG/FIELD|31:9||description=''reserved''}}<br />
{{REG/FIELD|?:0|MACC_HEVC_NAL_HDR_TYPE|values=<pre>nal_unit_type</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_SPS ==<br />
{{REG|MACC_HEVC_SPS|offset=0x504|<br />
{{REG/FIELD|31:27||description=''reserved''}}<br />
{{REG/FIELD|26||values=<pre>strong_intra_smoothing_enabled_flag</pre>}}<br />
{{REG/FIELD|25||values=<pre>sps_temporal_mvp_enabled_flag</pre>}}<br />
{{REG/FIELD|24||values=<pre>sample_adaptive_offset_enabled_flag</pre>}}<br />
{{REG/FIELD|23||values=<pre>amp_enabled_flag</pre>}}<br />
{{REG/FIELD|22:20||values=<pre>max_transform_hierarchy_depth_intra</pre>}}<br />
{{REG/FIELD|19:17||values=<pre>max_transform_hierarchy_depth_inter</pre>}}<br />
{{REG/FIELD|16:15||values=<pre>log2_diff_max_min_transform_block_size</pre>}}<br />
{{REG/FIELD|14:13||values=<pre>log2_min_transform_block_size_minus2</pre>}}<br />
{{REG/FIELD|12:11||values=<pre>log2_diff_max_min_luma_coding_block_size</pre>}}<br />
{{REG/FIELD|10:9||values=<pre>log2_min_luma_coding_block_size_minus3</pre>}}<br />
{{REG/FIELD|8:2||description=''unknown''}}<br />
<br />
{{REG/FIELD|1:0||values=<pre>chroma_format_idc</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_PIC_SIZE ==<br />
{{REG|MACC_HEVC_PIC_SIZE|offset=0x508|<br />
{{REG/FIELD|31:30||description=''reserved''}}<br />
{{REG/FIELD|29:16|MACC_HEVC_PIC_SIZE_HEIGHT|values=<pre>pic_height_in_luma_samples</pre>}}<br />
{{REG/FIELD|15:14||description=''reserved''}}<br />
{{REG/FIELD|13:0|MACC_HEVC_PIC_SIZE_WIDTH|values=<pre>pic_width_in_luma_samples</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_PCM_HDR ==<br />
{{REG|MACC_HEVC_PCM_HDR|offset=0x50c|<br />
{{REG/FIELD|31:16||description=''reserved''}}<br />
{{REG/FIELD|15||values=<pre>pcm_enabled_flag</pre>}}<br />
{{REG/FIELD|14||description=''unknown''}}<br />
{{REG/FIELD|13:12||description=''reserved''}}<br />
{{REG/FIELD|11:10||values=<pre>log2_diff_max_min_pcm_luma_coding_block_size</pre>}}<br />
{{REG/FIELD|9:8||values=<pre>log2_min_pcm_luma_coding_block_size_minus3</pre>}}<br />
{{REG/FIELD|7:4||values=<pre>pcm_sample_bit_depth_chroma_minus1</pre>}}<br />
{{REG/FIELD|3:0||values=<pre>pcm_sample_bit_depth_luma_minus1</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_PPS0 ==<br />
{{REG|MACC_HEVC_PPS0|offset=0x510|<br />
{{REG/FIELD|31:29||description=''reserved''}}<br />
{{REG/FIELD|28:24||values=<pre>pps_cr_qp_offset</pre>}}<br />
{{REG/FIELD|23:21||description=''reserved''}}<br />
{{REG/FIELD|20:16||values=<pre>pps_cb_qp_offset</pre>}}<br />
{{REG/FIELD|15:14||description=''reserved''}}<br />
{{REG/FIELD|13:8||values=<pre>init_qp_minus26</pre>}}<br />
{{REG/FIELD|7:6||description=''reserved''}}<br />
{{REG/FIELD|5:4||values=<pre>diff_cu_qp_delta_depth</pre>}}<br />
{{REG/FIELD|3||values=<pre>cu_qp_delta_enabled_flag</pre>}}<br />
{{REG/FIELD|2||values=<pre>transform_skip_enabled_flag</pre>}}<br />
{{REG/FIELD|1||values=<pre>constrained_intra_pred_flag</pre>}}<br />
{{REG/FIELD|0||values=<pre>sign_data_hiding_enabled_flag</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_PPS1 ==<br />
{{REG|MACC_HEVC_PPS1|offset=0x514|<br />
{{REG/FIELD|31:11||description=''reserved''}}<br />
{{REG/FIELD|10:8||values=<pre>log2_parallel_merge_level_minus2</pre>}}<br />
{{REG/FIELD|7||description=''reserved''}}<br />
{{REG/FIELD|6||values=<pre>pps_loop_filter_across_slices_enabled_flag</pre>}}<br />
{{REG/FIELD|5||values=<pre>loop_filter_across_tiles_enabled_flag</pre>}}<br />
{{REG/FIELD|4||values=<pre>entropy_coding_sync_enabled_flag</pre>}}<br />
{{REG/FIELD|3||values=<pre>tiles_enabled_flag</pre>}}<br />
{{REG/FIELD|2||values=<pre>transquant_bypass_enabled_flag</pre>}}<br />
{{REG/FIELD|1||values=<pre>weighted_bipred_flag</pre>}}<br />
{{REG/FIELD|0||values=<pre>weighted_pred_flag</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_SCALING_LIST_CTRL ==<br />
{{REG|MACC_HEVC_SCALING_LIST_CTRL|offset=0x518|<br />
{{REG/FIELD|31|MACC_HEVC_SCALING_LIST_ENABLED|description=Enable scaling lists}}<br />
{{REG/FIELD|30||description=maybe use default scaling lists}}<br />
{{REG/FIELD|29:0||description=''reserved''}}<br />
}}<br />
<br />
== MACC_HEVC_SLICE_HDR0 ==<br />
{{REG|MACC_HEVC_SLICE_HDR0|offset=0x520|<br />
{{REG/FIELD|31:30||description=''reserved''}}<br />
{{REG/FIELD|29:28||description=''unknown''}}<br />
{{REG/FIELD|27||description=''reserved''}}<br />
{{REG/FIELD|26:24||values=<pre>five_minus_max_num_merge_cand</pre>}}<br />
{{REG/FIELD|23:20|MACC_HEVC_SLICE_HDR_NUM_REF_IDX_L1|values=<pre>num_ref_idx_l1_active_minus1</pre>}}<br />
{{REG/FIELD|19:16|MACC_HEVC_SLICE_HDR_NUM_REF_IDX_L0|values=<pre>num_ref_idx_l0_active_minus1</pre>}}<br />
{{REG/FIELD|15:12||values=<pre>collocated_ref_idx</pre>}}<br />
{{REG/FIELD|11||values=<pre>collocated_from_l0_flag</pre>}}<br />
{{REG/FIELD|10|MACC_HEVC_SLICE_HDR_CABAC_INIT|values=<pre>cabac_init_flag</pre>}}<br />
{{REG/FIELD|9|MACC_HEVC_SLICE_HDR_MVD_L1_ZERO|values=<pre>mvd_l1_zero_flag</pre>}}<br />
{{REG/FIELD|8|MACC_HEVC_SLICE_HDR_SAO_CHROMA|values=<pre>slice_sao_chroma_flag</pre>}}<br />
{{REG/FIELD|7|MACC_HEVC_SLICE_HDR_SAO_LUMA|values=<pre>slice_sao_luma_flag</pre>}}<br />
{{REG/FIELD|6||values=<pre>slice_temporal_mvp_enabled_flag</pre>}}<br />
{{REG/FIELD|5:4||description=''unknown''}}<br />
{{REG/FIELD|3:2|MACC_HEVC_SLICE_HDR_SLICE_TYPE|values=<pre>slice_type</pre>}}<br />
{{REG/FIELD|1||values=<pre>dependent_slice_segment_flag</pre>}}<br />
{{REG/FIELD|0||values=<pre>first_slice_segment_in_pic_flag</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_SLICE_HDR1 ==<br />
{{REG|MACC_HEVC_SLICE_HDR1|offset=0x524|<br />
{{REG/FIELD|31:28||values=<pre>slice_tc_offset_div2</pre>}}<br />
{{REG/FIELD|27:24||values=<pre>slice_beta_offset_div2</pre>}}<br />
{{REG/FIELD|23||values=<pre>slice_deblocking_filter_disabled_flag</pre>}}<br />
{{REG/FIELD|22|MACC_HEVC_SLICE_HDR_LOOP_FILTER_ACROSS_SLICES|values=<pre>slice_loop_filter_across_slices_enabled_flag</pre>}}<br />
{{REG/FIELD|21||values=<pre>NumPocStCurrAfter == 0</pre>|description=''unsure''}}<br />
{{REG/FIELD|20:16||values=<pre>slice_cr_qp_offset</pre>}}<br />
{{REG/FIELD|15:13||description=''reserved''}}<br />
{{REG/FIELD|12:8||values=<pre>slice_cb_qp_offset</pre>}}<br />
{{REG/FIELD|7:6||description=''reserved''}}<br />
{{REG/FIELD|5:0|MACC_HEVC_SLICE_HDR_QP_DELTA|values=<pre>slice_qp_delta</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_SLICE_HDR2 ==<br />
{{REG|MACC_HEVC_SLICE_HDR2|offset=0x528|<br />
{{REG/FIELD|31:22||description=''reserved''}}<br />
{{REG/FIELD|21:8||values=<pre>num_entry_point_offsets</pre>}}<br />
{{REG/FIELD|7||description=''reserved''}}<br />
{{REG/FIELD|6:4||values=<pre>ChromaLog2WeightDenom</pre>}}<br />
{{REG/FIELD|3||description=''reserved''}}<br />
{{REG/FIELD|2:0||values=<pre>luma_log2_weight_denom</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_CTB_ADDR ==<br />
{{REG|MACC_HEVC_CTB_ADDR|offset=0x52c|<br />
{{REG/FIELD|31:25||description=''reserved''}}<br />
{{REG/FIELD|24:16|MACC_HEVC_CTB_ADDR_Y|description=start CTB y}}<br />
{{REG/FIELD|15:9||description=''reserved''}}<br />
{{REG/FIELD|8:0|MACC_HEVC_CTB_ADDR_X|description=start CTB x}}<br />
}}<br />
<br />
== MACC_HEVC_CTRL ==<br />
{{REG|MACC_HEVC_CTRL|offset=0x530|<br />
<br />
}}<br />
<br />
== MACC_HEVC_TRIG ==<br />
{{REG|MACC_HEVC_TRIG|offset=0x534|<br />
{{REG/FIELD|?:8|MACC_HEVC_TRIG_PARA|description=Parameter n}}<br />
{{REG/FIELD|?:0|MACC_HEVC_TRIG_FUNCTION|values=<pre><br />
0x0 = ?<br />
0x1 = ?<br />
0x2 = read n bits (n <= 32)<br />
0x3 = skip n bits (n <= 32)<br />
0x4 = read exp-golomb coded signed integer<br />
0x5 = read exp-golomb coded unsigned integer<br />
0x6 = ?<br />
0x7 = sync<br />
0x8 = decode H.265 slice<br />
</pre>|description=Function}}<br />
}}<br />
<br />
== MACC_HEVC_STATUS ==<br />
{{REG|MACC_HEVC_STATUS|offset=0x538|<br />
{{REG/FIELD|8|MACC_HEVC_STATUS_VLD_BUSY|description=VLD busy}}<br />
{{REG/FIELD|1|MACC_HEVC_STATUS_ERR|description=decoding error}}<br />
{{REG/FIELD|0|MACC_HEVC_STATUS_DONE|description=decoding finished}}<br />
}}<br />
<br />
== MACC_HEVC_CTU_NUM ==<br />
{{REG|MACC_HEVC_CTU_NUM|offset=0x53c|<br />
<br />
}}<br />
<br />
== MACC_HEVC_BITS_ADDR ==<br />
{{REG|MACC_HEVC_BITS_ADDR|offset=0x540|<br />
{{REG/FIELD|23:0|MACC_HEVC_BITS_ADDR|values=<pre>bits 31:8 of address</pre>|description=Bitstream start address}}<br />
}}<br />
<br />
== MACC_HEVC_BITS_OFFSET ==<br />
{{REG|MACC_HEVC_BITS_OFFSET|offset=0x544|<br />
<br />
}}<br />
<br />
== MACC_HEVC_BITS_LEN ==<br />
{{REG|MACC_HEVC_BITS_LEN|offset=0x548|<br />
<br />
}}<br />
<br />
== MACC_HEVC_BITS_END_ADDR ==<br />
{{REG|MACC_HEVC_BITS_END_ADDR|offset=0x54c|<br />
{{REG/FIELD|23:0|MACC_HEVC_BITS_END_ADDR|values=<pre>bits 31:8 of address</pre>|description=Bitstream end address}}<br />
}}<br />
<br />
== MACC_HEVC_EXTRA_OUT_CTRL ==<br />
{{REG|MACC_HEVC_EXTRA_OUT_CTRL|offset=0x550|<br />
<br />
}}<br />
<br />
== MACC_HEVC_EXTRA_OUT_LUMA_ADDR ==<br />
{{REG|MACC_HEVC_EXTRA_OUT_LUMA_ADDR|offset=0x554|<br />
<br />
}}<br />
<br />
== MACC_HEVC_EXTRA_OUT_CHROMA_ADDR ==<br />
{{REG|MACC_HEVC_EXTRA_OUT_CHROMA_ADDR|offset=0x558|<br />
<br />
}}<br />
<br />
== MACC_HEVC_REC_BUF_IDX ==<br />
{{REG|MACC_HEVC_REC_BUF_IDX|offset=0x55c|<br />
{{REG/FIELD|31:5||description=''reserved''}}<br />
{{REG/FIELD|4:0|MACC_HEVC_REC_BUF_IDX|description=output buffer index in picture list}}<br />
}}<br />
<br />
== MACC_HEVC_NEIGHBOR_INFO_ADDR ==<br />
{{REG|MACC_HEVC_NEIGHBOR_INFO_ADDR|offset=0x560|<br />
{{REG/FIELD|23:0|MACC_HEVC_NEIGHBOR_INFO_ADDR|values=<pre>bits 31:8 of address</pre>|description=Neighbor info buffer address}}<br />
}}<br />
<br />
== MACC_HEVC_TILE_LIST_ADDR ==<br />
{{REG|MACC_HEVC_TILE_LIST_ADDR|offset=0x564|<br />
{{REG/FIELD|23:0|MACC_HEVC_TILE_LIST_ADDR|values=<pre>bits 31:8 of address</pre>|description=Tile entry point list address}}<br />
}}<br />
<br />
Points to a list of entry point offsets and tile start/end CTBs<br />
<br />
struct {<br />
uint32_t entry_point_offset;<br />
uint32_t zero;<br />
uint16_t tile_start_ctb_x;<br />
uint16_t tile_start_ctb_y;<br />
uint16_t tile_end_ctb_x;<br />
uint16_t tile_end_ctb_y;<br />
} tile_list[num_entry_point_offsets];<br />
<br />
== MACC_HEVC_TILE_START_CTB ==<br />
{{REG|MACC_HEVC_TILE_START_CTB|offset=0x568|<br />
{{REG/FIELD|31:25||description=''reserved''}}<br />
{{REG/FIELD|24:16|MACC_HEVC_TILE_START_CTB_Y|description=start tile y}}<br />
{{REG/FIELD|15:9||description=''reserved''}}<br />
{{REG/FIELD|8:0|MACC_HEVC_TILE_START_CTB_X|description=start tile x}}<br />
}}<br />
<br />
== MACC_HEVC_TILE_END_CTB ==<br />
{{REG|MACC_HEVC_TILE_END_CTB|offset=0x56c|<br />
{{REG/FIELD|31:25||description=''reserved''}}<br />
{{REG/FIELD|24:16|MACC_HEVC_TILE_END_CTB_Y|description=end tile y}}<br />
{{REG/FIELD|15:9||description=''reserved''}}<br />
{{REG/FIELD|8:0|MACC_HEVC_TILE_END_CTB_X|description=end tile x}}<br />
}}<br />
<br />
== MACC_HEVC_SCALING_LIST_DC_COEF0 ==<br />
{{REG|MACC_HEVC_SCALING_LIST_DC_COEF0|offset=0x578|<br />
{{REG/FIELD|31:24||values=<pre>ScalingListDCCoeff32x32[1]</pre>}}<br />
{{REG/FIELD|23:16||values=<pre>ScalingListDCCoeff32x32[0]</pre>}}<br />
{{REG/FIELD|15:8||values=<pre>ScalingListDCCoeff16x16[1]</pre>}}<br />
{{REG/FIELD|7:0||values=<pre>ScalingListDCCoeff16x16[0]</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_SCALING_LIST_DC_COEF1 ==<br />
{{REG|MACC_HEVC_SCALING_LIST_DC_COEF1|offset=0x57c|<br />
{{REG/FIELD|31:24||values=<pre>ScalingListDCCoeff16x16[5]</pre>}}<br />
{{REG/FIELD|23:16||values=<pre>ScalingListDCCoeff16x16[4]</pre>}}<br />
{{REG/FIELD|15:8||values=<pre>ScalingListDCCoeff16x16[3]</pre>}}<br />
{{REG/FIELD|7:0||values=<pre>ScalingListDCCoeff16x16[2]</pre>}}<br />
}}<br />
<br />
== MACC_HEVC_BITS_DATA ==<br />
{{REG|MACC_HEVC_BITS_DATA|offset=0x5dc|<br />
{{REG/FIELD|31:0|MACC_HEVC_BITS_DATA|description=Data read from bitstream}}<br />
}}<br />
<br />
== MACC_HEVC_SRAM_ADDR ==<br />
{{REG|MACC_HEVC_SRAM_ADDR|offset=0x5e0|<br />
{{REG/FIELD|31:12||description=''reserved''}}<br />
{{REG/FIELD|11:0||description=SRAM address to write to (auto incrementing)}}<br />
}}<br />
<br />
== MACC_HEVC_SRAM_DATA ==<br />
{{REG|MACC_HEVC_SRAM_DATA|offset=0x5e4|<br />
{{REG/FIELD|31:0||description=Write data to SRAM}}<br />
}}<br />
<br />
Memory layout for H.265 decoding:<br />
0x000 - 0x01f Prediction Weight Luma List 0<br />
0x020 - 0x05f Prediction Weight Chroma List 0<br />
0x060 - 0x07f Prediction Weight Luma List 1<br />
0x080 - 0x0bf Prediction Weight Chroma List 1<br />
0x400 - 0x7ff Picture List<br />
0x800 - 0xbdf Scaling Lists<br />
0xc00 - 0xc0f Reference Picture List 0<br />
0xc10 - 0xc1f Reference Picture List 1<br />
<br />
Prediction Weight Luma Lists:<br />
struct {<br />
int8_t delta_luma_weight;<br />
int8_t luma_offset;<br />
} pred_weight_luma[16];<br />
<br />
Prediction Weight Chroma Lists:<br />
struct {<br />
int8_t delta_chroma_weight_cb;<br />
int8_t ChromaOffset_cb;<br />
int8_t delta_chroma_weight_cr;<br />
int8_t ChromaOffset_cr;<br />
} pred_weight_chroma[16];<br />
<br />
Picture List:<br />
struct {<br />
uint32_t pic_order_cnt;<br />
uint32_t pic_order_cnt;<br />
uint32_t extra_buffer_addr;<br />
uint32_t extra_buffer_addr;<br />
uint32_t luma_addr;<br />
uint32_t chroma_addr;<br />
uint32_t reserved;<br />
uint32_t reserved;<br />
} picture_list[32];<br />
<br />
Scaling Lists (in horizontal scan order):<br />
struct {<br />
uint8_t ScalingList8x8[6][64];<br />
uint8_t ScalingList32x32[2][64];<br />
uint8_t ScalingList16x16[6][64];<br />
uint8_t ScalingList4x4[6][16];<br />
} scaling_lists;<br />
<br />
Reference Picture Lists:<br />
uint8_t ref_picture[16]; // index to picture list (set bit7 for longterm reference)<br />
<br />
= ISP Engine Registers =<br />
<br />
== MACC_ISP_PIC_SIZE ==<br />
{{REG|MACC_ISP_PIC_SIZE|offset=0xa00|<br />
{{REG/FIELD|26:16|MACC_ISP_PIC_SIZE_WIDTH |description=width of source picture in macroblocks}}<br />
{{REG/FIELD|10:0 |MACC_ISP_PIC_SIZE_HEIGHT|description=height of source picture in macroblocks}}<br />
}}<br />
<br />
== MACC_ISP_PIC_STRIDE ==<br />
{{REG|MACC_ISP_PIC_STRIDE|offset=0xa04|<br />
{{REG/FIELD|26:16|MACC_ISP_PIC_STRIDE |description=stride of source picture in macroblocks}}<br />
{{REG/FIELD|10:0 |MACC_ISP_OUTPIC_STRIDE|description=stride of output picture in macroblocks}}<br />
}}<br />
<br />
== MACC_ISP_CTRL ==<br />
{{REG|MACC_ISP_CTRL|offset=0xa08|<br />
{{REG/FIELD|31:29|MACC_ISP_CTRL_COLOR_FORMAT|description=Source picture color format<br />
|values=<pre><br />
0x0 = nv12<br />
0x1 = nv16<br />
0x2 = tile32x32<br />
0x3 = nv16?<br />
0x4 = BGGR<br />
0x5 = RGGB<br />
0x6 = GBRG<br />
0x7 = GRBG<br />
</pre>}}<br />
{{REG/FIELD| 28 |MACC_ISP_CTRL_COLOR_SPACE |description=RGB to YCbCr color transformation mode<br />
|values=<pre><br />
? = BT601<br />
? = BT709<br />
</pre>}}<br />
{{REG/FIELD|27:25|MACC_ISP_CTRL_? |description=Output picture dimensions division factor<br />
|values=<pre><br />
0x0 = /1 0x4 = /1<br />
0x1 = ? 0x5 = ? <br />
0x2 = /2 0x6 = /2<br />
0x3 = /4 0x7 = /4<br />
</pre>}}<br />
{{REG/FIELD| 24 |MACC_ISP_CTRL_? |description=Output picture color format<br />
|values=<pre><br />
0 = nv12<br />
1 = nv16<br />
</pre>}}<br />
{{REG/FIELD| 19 |MACC_ISP_CTRL_OUTPUT_EN |description=Enable output}}<br />
{{REG/FIELD| 16 |MACC_ISP_CTRL_SCALER_EN |description=Enable scaler/Clear IRQ status}}<br />
{{REG/FIELD| 0 |MACC_ISP_CTRL_IRQ_EN |description=Enable IRQ from ISP}}<br />
}}<br />
<br />
== MACC_ISP_TRIG ==<br />
{{REG|MACC_ISP_TRIG|offset=0xa0c|<br />
{{REG/FIELD| 3:0 |MACC_ISP_TRIG_FUNCTION|description=Function<br />
|values=<pre>1 = launch</pre>}}<br />
}}<br />
<br />
== MACC_ISP_SCALER_SIZE ==<br />
{{REG|MACC_ISP_SCALER_SIZE|offset=0xa2c|<br />
{{REG/FIELD|15:8 |MACC_ISP_SCALER_SIZE_HEIGHT|description=scale picture to height macroblocks}}<br />
{{REG/FIELD| 7:0 |MACC_ISP_SCALER_SIZE_WIDTH |description=scale picture to width macroblocks}}<br />
}}<br />
<br />
== MACC_ISP_SCALER_OFFSET_Y ==<br />
{{REG|MACC_ISP_SCALER_OFFSET_Y|offset=0xa30|<br />
{{REG/FIELD|31:16|MACC_ISP_SCALER_Y_OFFSET|description=picture luma y position}}<br />
{{REG/FIELD|15:0 |MACC_ISP_SCALER_X_OFFSET|description=picture luma x position<br />
|values=<pre>0x0080 = 0.5 pixels</pre>}}<br />
}}<br />
<br />
== MACC_ISP_SCALER_OFFSET_C ==<br />
{{REG|MACC_ISP_SCALER_OFFSET_C|offset=0xa34|<br />
{{REG/FIELD|31:16|MACC_ISP_SCALER_Y_OFFSET|description=picture chroma y position}}<br />
{{REG/FIELD|15:0 |MACC_ISP_SCALER_X_OFFSET|description=picture chroma x position<br />
|values=<pre>0x0080 = 0.5 pixels</pre>}}<br />
}}<br />
<br />
== MACC_ISP_SCALER_FACTOR ==<br />
{{REG|MACC_ISP_SCALER_FACTOR|offset=0x038|<br />
{{REG/FIELD|23:12|MACC_ISP_SCALER_Y_FACTOR|description=y scale factor}}<br />
{{REG/FIELD|11:0 |MACC_ISP_SCALER_X_FACTOR|description=x scale factor<br />
|values=<pre><br />
0x080 = 2x<br />
0x100 = 1x<br />
0x200 = 0.5x<br />
</pre>}}<br />
}}<br />
<br />
<br />
== MACC_ISP_OUTPUT_LUMA ==<br />
{{REG|MACC_ISP_OUTPUT_LUMA|offset=0xa70|<br />
{{REG/FIELD|31:0||description=Output picture luma address.}}<br />
}}<br />
<br />
== MACC_ISP_OUTPUT_CHROMA ==<br />
{{REG|MACC_ISP_OUTPUT_CHROMA|offset=0xa74|<br />
{{REG/FIELD|31:0||description=Output picture chroma address.}}<br />
}}<br />
<br />
== MACC_ISP_WB_THUMB_LUMA ==<br />
{{REG|MACC_ISP_WB_THUMB_LUMA|offset=0xa78|<br />
{{REG/FIELD|31:0||description=WriteBack Thumb buffer offset, luma(Y) component}}<br />
}}<br />
<br />
== MACC_ISP_WB_THUMB_CHROMA ==<br />
{{REG|MACC_ISP_WB_THUMB_CHROMA|offset=0xa7c|<br />
{{REG/FIELD|31:0||description=WriteBack Thumb buffer offset, chroma component}}<br />
}}<br />
<br />
== MACC_ISP_SRAM_INDEX ==<br />
{{REG|MACC_ISP_SRAM_INDEX|offset=0xae0|<br />
{{REG/FIELD|31:0||description=Auto incremental pointer for read/write VE SRAM}}<br />
}}<br />
<br />
== MACC_ISP_SRAM_DATA ==<br />
{{REG|MACC_ISP_SRAM_DATA|offset=0xae4|<br />
{{REG/FIELD|31:0||description=Serial write/read buffer register for read/write VE SRAM}}<br />
}}<br />
<br />
When scaler is enabled (MACC_ISP_CTRL_SCALER_EN), and MACC_ISP_SRAM_INDEX set to 0x400 the next 64 values written into MACC_ISP_SRAM_DATA are treated as coefficients for a polyphase filter in the following mode.<br />
<br />
|0 31|32 64| <br />
---------------------------------|--------------------------------<br />
| table A | table B |<br />
---------------------------------|--------------------------------<br />
All coefficients are signed 16 bit values.<br />
0x0100 = 1.0<br />
0x0080 = 0.5<br />
0x0000 = 0.0<br />
0xffff = -1/0x100<br />
0xff00 = -1.0 (?)<br />
<br />
Horizontal direction.<br />
Table A => 4-tap, 16-phase polyphase filter coefficients (h0, h1, h2, h3)<br />
| data written<br />
offset |31 16|15 0|<br />
----------------------<br />
2*i+0 | h1 | h0 |<br />
2*i+1 | h3 | h2 |<br />
----------------------<br />
<br />
Vertical direction.<br />
Table B => 2-tap, 32-phase polyphase filter coefficients (h0, h1)<br />
| data written<br />
offset |31 16|15 0|<br />
-----------------------<br />
i | h1 | h0 |<br />
<br />
= AVC Engine Register =<br />
<br />
== MACC_AVC_JPEG_CTRL ==<br />
{{REG|MACC_AVC_JPEG_CTRL|offset=0xb04|<br />
{{REG/FIELD| 31 | MACC_AVC_JPEG_CTRL_FILL1<br />
|description=fill the remaining bits as 1 for byte boundary alignment}}<br />
{{REG/FIELD| 30 | MACC_AVC_JPEG_CTRL_STUFF<br />
|description=if last byte written is 0xff, stuff 0x00}}<br />
{{REG/FIELD|26:16| MACC_AVC_JPEG_CTRL_BIAS_C<br />
|values=<pre>0x400 / (chroma dc quantization value)</pre><br />
|description=chroma dc component bias}}<br />
{{REG/FIELD|10:0 | MACC_AVC_JPEG_CTRL_BIAS_Y<br />
|values=<pre>0x400 / (luma dc quantization value)</pre><br />
|description=luma dc component bias}}<br />
}}<br />
<br />
<br />
== MACC_AVC_H264_CTRL ==<br />
{{REG|MACC_AVC_H264_CTRL|offset=0xb04|<br />
{{REG/FIELD| 31 | MACC_AVC_H264_CTRL_EPTB<br />
|values=<pre><br />
0x0 = enable<br />
0x1 = disable<br />
</pre><br />
|description=automatically insert emulation_prevention_three_byte in bitstream}}<br />
{{REG/FIELD|30:9 ||description=''unknown''}}<br />
{{REG/FIELD| 8 | MACC_AVC_H264_CTRL_ENTROPY_CODING<br />
|values=<pre><br />
0x0 = CAVLC<br />
0x1 = CABAC<br />
</pre><br />
|description=entropy_coding_mode_flag}}<br />
{{REG/FIELD| 7:6 ||description=''unknown''}}<br />
{{REG/FIELD| 5:4 | MACC_AVC_H264_CTRL_SLICE_TYPE<br />
|values=<pre><br />
0x0 = I<br />
0x1 = P<br />
0x2 = unknown<br />
0x3 = looks like B, but unsure<br />
</pre><br />
|description=Slice type}}<br />
{{REG/FIELD| 3:0 ||description=''unknown''}}<br />
}}<br />
<br />
== MACC_AVC_H264_QP ==<br />
{{REG|MACC_AVC_H264_QP|offset=0xb08|<br />
{{REG/FIELD|31:19||description=''reserved''}}<br />
{{REG/FIELD|18:16||values=<pre>chroma_qp_index_offset</pre><br />
|description=must have some range limit (spec says -12 to 12, but only 3 bits)}}<br />
{{REG/FIELD|15:14||description=''reserved''}}<br />
{{REG/FIELD|13:8 ||values=<pre>pic_init_qp + slice_qp_delta</pre>}}<br />
{{REG/FIELD| 7:6 ||description=''unknown''}}<br />
{{REG/FIELD| 5:0 ||values=<pre><br />
pic_init_qp + slice_qp_delta<br />
<br />
valid: 0x01 to 0x45<br />
</pre><br />
|description=''why double?''}}<br />
}}<br />
<br />
== MACC_AVC_CTRL ==<br />
{{REG|MACC_AVC_CTRL|offset=0xb14|<br />
{{REG/FIELD| 7 | MACC_AVC_CTRL_IRQ_EN |description=Enable IRQ form AVC}}<br />
}}<br />
<br />
<br />
== MACC_AVC_TRIG ==<br />
{{REG|MACC_AVC_TRIG|offset=0xb18|<br />
{{REG/FIELD| 16 | MACC_AVC_TRIG_FORMAT<br />
|values=<pre><br />
0x0 = h264<br />
0x1 = jpeg<br />
</pre>}}<br />
{{REG/FIELD|12:8 | MACC_AVC_TRIG_NBITS<br />
|values=<pre><br />
0 - 31<br />
</pre><br />
|description=Number of put bits}}<br />
{{REG/FIELD| 3:0 | MACC_AVC_TRIG_FUNCTION<br />
|values=<pre><br />
0x1 = Put bits<br />
0x8 = Launch encoding<br />
</pre><br />
|description=Function}}<br />
}}<br />
<br />
== MACC_AVC_STATUS ==<br />
{{REG|MACC_AVC_STATUS|offset=0xb1c|<br />
{{REG/FIELD|31:16||description=unknown, related to macroblocks number?}}<br />
{{REG/FIELD|12:4 ||values=<pre><br />
0x26 = nominal<br />
0x06 = ?<br />
</pre><br />
|description=unknown}}<br />
{{REG/FIELD| 4:0 | MACC_AVC_STATUS_RESULT<br />
|values=<pre><br />
0x0 = nominal<br />
0x1 = success (at encoder finish)<br />
0x2 = error (at pic size zero)<br />
(at max bits written)<br />
</pre><br />
<pre><br />
write 1 to bit to clear bit<br />
0x1 clears bit 1<br />
0x3 clears bit 1 and bit 2<br />
</pre><br />
|description=result, in IRQ should be cleared first 7:0 bits}}<br />
}}<br />
<br />
== MACC_AVC_BITS_DATA ==<br />
{{REG|MACC_AVC_BITS_DATA|offset=0xb20|<br />
{{REG/FIELD|31:0 | MACC_AVC_BITS_DATA |description=Data to be written by put bits.}}<br />
}}<br />
<br />
== MACC_AVC_VLE_ADDR ==<br />
{{REG|MACC_AVC_VLE_ADDR|offset=0xb80|<br />
{{REG/FIELD|31:0 ||description=Address to output the encoded bitstream}}<br />
}}<br />
<br />
== MACC_AVC_VLE_END ==<br />
{{REG|MACC_AVC_VLE_END|offset=0xb84|<br />
{{REG/FIELD|31:0 ||values=<pre><br />
MACC_AVC_VLE_ADDR + (size of buffer) - 1<br />
</pre><br />
|description=End position of the cyclic buffer, after reached starts from beginning.}}<br />
}}<br />
<br />
== MACC_AVC_VLE_OFFSET ==<br />
{{REG|MACC_AVC_VLE_OFFSET|offset=0xb88|<br />
{{REG/FIELD|31:0 ||values=<pre><br />
write only<br />
set MACC_AVC_VLE_LENGTH = bits[27:0]<br />
???? reset position to (start address) + bits[4:0]<br />
</pre><br />
|description=Offset in bits of the position to start writing}}<br />
}}<br />
<br />
== MACC_AVC_VLE_MAX ==<br />
{{REG|MACC_AVC_VLE_MAX|offset=0xb8c|<br />
{{REG/FIELD|27:0 ||values=<pre><br />
0x0010000 = 8192 bytes<br />
0xfff0000 = 33546240 bytes<br />
<br />
bits[15:0] always zero<br />
</pre><br />
|description=Maximum number of bits to write}}<br />
}}<br />
<br />
== MACC_AVC_VLE_LENGTH ==<br />
{{REG|MACC_AVC_VLE_LENGTH|offset=0xb90|<br />
{{REG/FIELD|31:0 ||mode=R|values=<pre>MACC_AVC_VLE_OFFSET + (bits written)</pre>}}<br />
}}<br />
<br />
== MACC_AVC_SRAM_INDEX ==<br />
{{REG|MACC_AVC_SRAM_INDEX|offset=0xbe0|<br />
{{REG/FIELD|31:0 ||description=Auto incremental pointer for read/write VE SRAM}}<br />
}}<br />
<br />
<br />
== MACC_AVC_SRAM_DATA ==<br />
{{REG|MACC_AVC_SRAM_DATA|offset=0xbe4|<br />
{{REG/FIELD|31:0 |}}<br />
}}<br />
For mpeg/mjpeg, [[#MACC_AVC_SDRAM_INDEX|MACC_AVC_SDRAM_INDEX]] is the start index to write the quantization matrix elements into MACC_AVC_SRAM_DATA. If index is 64, then the first 64 elements are for chroma component, and the next 64 wrap around to become luma.<br />
<br />
0 63|64 127<br />
----------------------------------------------------------------------------<br />
| luma quantization matrix | chroma quantization matrix | index by natural order<br />
---------------------------------------------------------------------------- <br />
MACC_AVC_SRAM_DATA[23:16] = (Q / 2) + 0.5<br />
MACC_AVC_SRAM_DATA[15:0] = (0xffff / Q)<br />
When compared with libjpeg, there are still rounding errors in the coefficients value, around 1 unit of difference.<br />
<br />
(Quantized coefficients) = round(C / Q)<br />
= floor((C + 0.5Q) / Q)<br />
<br />
= References =<br />
<references /><br />
<br />
[[Category:Video Engine]]<br />
[[Category:A10 Register guide]]<br />
[[Category:A13 Register guide]]<br />
[[Category:A20 Register guide]]<br />
[[Category:A13 Register guide]]<br />
[[Category:A31 Register guide]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=R8&diff=18258
R8
2016-09-21T16:55:11Z
<p>Nove: Cedarx is the name of software not hardware, see http://linux-sunxi.org/Cedar_Engine for the why.</p>
<hr />
<div>{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = <br />
| cpu = ARM Cortex-A8 @ 1Ghz<br />
| ltwo = <br />
| extensions = NEON, VFPv3<br />
| memory = DDR2, DDR3 (max 512MB)<br />
| gpu = [[Mali400|Mali 400]] <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = LCD<br />
| audio = Mic, Headphone<br />
| network = -<br />
| storage = NAND (max 2 * 32GB), SD Card 3.0, SPI NOR Flash, USB Storage<br />
| usb = 2 (1 HOST, 1 OTG)<br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/clq/r/R8.html Product Page]<br />
}}<br />
<br />
[[Allwinner]] '''R8''' is SoC designed based on [[A13]] featuring one core Cortex-A8 ARM CPU with [[Cedar Engine]] VPU and [[Mali 400]] GPU.<br />
<br />
=Overview=<br />
==Main components of the R8:==<br />
* CPU: [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8 1GHz (ARM v7) Processor] which have both [[Vector Floating Point Unit|VFPv3]] and [[NEON]] co-processors: <br />
** FPU: [[Vector Floating Point Unit]] (standard ARM VFPv3 FPU Floating Point Unit)<br />
** SIMD: [[NEON]] (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
<br />
The R8 is a modified version of the A13, targeted to IoT devices.<br />
== R8 SoC Features ==<br />
* CPU<br />
** ARM Cortex-A8 single core<br />
** 256KB L2-Cache<br />
** 32KiB (Instruction) / 32KiB (Data)<br />
** SIMD NEON, VFP3<br />
* GPU<br />
** ARM Mali400<br />
** Complies with OpenGL ES 2.0<br />
* Memory<br />
** DDR2/DDR3 controller (upto 512 MB)<br />
** NAND Flash controller and 64-bit ECC<br />
* Video<br />
** HD H.264 video decoding<br />
** Full HD video decoding<br />
** H.264 Medium Profile 720P@30fps encoding<br />
** 1080p@30fps decoding<br />
* Display<br />
** CPU/RGB LCD interface<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV sensor<br />
* Peripherals<br />
** USB 2.0 OTG & USB 2.0 Host<br />
** 4x UARTs(all with IrDA)<br />
** 3x SPI controllers(master/slave mode)<br />
** 3x i2c controllers (called two wire interfaces TWI) standard mode (100Kbps) & fast-mode (up to 400K bps)<br />
** Internal 4-wire touch panel controller with pressure sensor and 2-point touch<br />
** Internal 24-bit Audio Codec for 2-Ch headphone and 1-Ch microphone<br />
** PWM controller<br />
* package: eLQFP 176-pin 22 mm × 22 mm (0.40 mm Pitch)<br />
<br />
= Documentation =<br />
<br />
* [https://github.com/NextThingCo/CHIP-Hardware/raw/master/CHIP%5Bv1_0%5D/CHIPv1_0-BOM-Datasheets/Allwinner%20R8%20Datasheet%20V1.2.pdf Allwinner R8 Datasheet v1.2]<br />
* [https://github.com/NextThingCo/CHIP-Hardware/raw/master/CHIP%5Bv1_0%5D/CHIPv1_0-BOM-Datasheets/Allwinner%20R8%20User%20Manual%20V1.1.pdf Allwinner R8 Manual v1.1]<br />
* A13 documentation is available on [https://github.com/allwinner-zh/documents/tree/master/A13 A13 AllWinners documentation repository on Github] (for comparison)<br />
<br />
= Devices =<br />
* [[NextThingCo_CHIP]]<br />
<br />
= See Also =<br />
* [[A13]]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus&diff=17885
Cedrus
2016-07-05T21:51:33Z
<p>Nove: Add link to the sunxi-cedrus repository.</p>
<hr />
<div>== Overview ==<br />
Cedrus is a project intended for fully 100% libre and open source software, for using the hardware accelerated video decoding/encoding engine found in sunxi devices. Replacing the proprietary library that has a long history of license ambiguity issues and in certain cases even (L)GPL violations.<br />
<br />
The name is derived from the Cedrus tree, which commonly is known as [http://en.wikipedia.org/wiki/Cedrus Cedar].<br />
<br />
=== Development ===<br />
Interested people are welcome to join the development channel '''#cedrus''' on Freenode IRC.<br />
<br />
The main repository for the ''out-of-tree'' V4L2 driver is at [https://github.com/linux-sunxi/sunxi-cedrus sunxi-cedrus].<br />
<br />
=== Current status ===<br />
<br />
The hardware is already well understood by the means of the reverse-engineering effort, which very quick got successful results. And a large majority of the [[VE_Register_guide|hardware registers]] are documented, with this information some Proof of Concept (PoC) [https://github.com/jemk/cedrus example source code] was written to verify that the hardware can be configured correctly from the information obtained.<br />
To forward verify, there was implemented a [https://github.com/linux-sunxi/libvdpau-sunxi vdpau driver backend] which is quite usable and can be used by any media player that uses the [https://en.wikipedia.org/wiki/VDPAU vdpau framework].<br />
<br />
The Cedrus project aims for a proper driver and software that can be mainlined and upstreamed to the proper places, this can't happen with the vendor kernel driver in its limitations, source code quality or transbording as a security risk.<br />
<br />
Steps for this proper driver and software can be seen in its [[VE_Planning|planning phase]].<br />
<br />
See for more information.<br />
* [[VE_Register_guide|'''Video Engine Register Guide''']]<br />
* [[Cedrus/libvdpau-sunxi|'''libvdpau-sunxi''']]<br />
* [[VE_Planning|'''Video Engine Planning]].<br />
<br />
=== Supported codec matrix ===<br />
{{:Cedrus/Supported Codec Feature Matrix}}<br />
<br />
<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=GPL_Violations&diff=17884
GPL Violations
2016-07-05T21:34:29Z
<p>Nove: Add a information note about the Cedrus project.</p>
<hr />
<div>[[Allwinner]] has repeatedly violated the [https://gnu.org/licenses/gpl GPL] (and by proxy so have most hardware manufacturers and resellers using or selling products based on Allwinner chipsets). Either by not providing (Linux/Android) kernel or u-boot source at all, or by delivering trees with pre-built binaries and no matching source code. They even blatantly use [https://gnu.org/licenses/lgpl LGPL] licensed code in their userspace libraries for media decoding.<br />
<br />
Over time, Allwinner has only increased the binary blobs present in their kernel trees, showing clearly that - even though Allwinner in the meantime joined [http://linaro.org Linaro] - it is not progressing. Quite the opposite actually, and one has to worry about what value Linaro membership really has if a member is allowed to behave like this.<br />
<br />
Allwinner also [http://www.linuxfoundation.org/news-media/announcements/2015/06/new-linux-foundation-members-advance-open-source-enterprise joined the Linux Foundation] as of June 2015, while compliance issues clearly remain.<br />
<br />
= In the linux kernel =<br />
<br />
Inclusion of binaries in the kernel source tree are a clear and obvious violation of the license of the linux kernel (GPL). Please note that different SoC variants had different SDK code drops from Allwinner, and their GPL license compliance status may vary.<br />
{| class="wikitable"<br />
! rowspan=2 | SoC name<br />
! rowspan=2 | Code drop<br />
! colspan=2 | Known GPL license incompatibilities<br />
|-<br />
! providing critical functionality || providing optional functionality<br />
|- style="background: lightgreen;"<br />
| Allwinner [[A10]]/[[A13]]//[[A20]] || || No problems known or worth mentioning. || No problems known or worth mentioning.<br />
|- style="background: orange;"<br />
| Allwinner [[H3]] || h3-lichee-1.0.tar.gz || While being open source, some of the Allwinner's code in the kernel has either no license boilerplace or an "all rights reserved" license notice. Most notably this includes HDMI support. || style="background: red;" | Some binary-only libraries are used for touchscreen, NAND, ISP, HDCP.<br />
|}<br />
<br />
== Camera support ==<br />
<br />
=== libisp ===<br />
libisp is a driver for the Image signal processor (HawkView ISP), used for camera picture preprocessing and image enhancement.<br />
<br />
GPL violations in:<br />
* [[A31#GPL_Violations |A31/A31s SDK]]<br />
* [[A23#GPL_violations |A23 SDK]]<br />
* [[A80#GPL_violations |A80 SDK]]<br />
<br />
=== Other camera code ===<br />
<br />
For A80, [[A80#GPL_violations|allwinner introduced 3 further blobs]], 2 for MIPICSI, and one for a "Face detector."<br />
<br />
GPL violations in:<br />
* [[A80#GPL_violations |A80 SDK]]<br />
<br />
== Touchscreen support ==<br />
<br />
Some binary blobs for touchscreen drivers are present in several SDKs.<br />
<br />
GPL violations in:<br />
* [[A31#GPL_Violations |A31/A31a SDK]]<br />
* [[A23#GPL_violations |A23 SDK]]<br />
* [[A80#GPL_violations |A80 SDK]]<br />
<br />
= U-boot =<br />
<br />
Inclusion of binaries in the u-boot source tree are a clear and obvious violation of the license of u-boot (GPL).<br />
<br />
Allwinner published the [https://github.com/allwinner-zh/bootloader u-boot source dump] on Github on 2015.01.15.<br />
== Other u-boot issues ==<br />
<br />
* drivers/video_sunxi/sunxi_v2/de_bsp/hdmi/aw/libhdcp<br />
* board/sunxi/sun8iw7/box_standby/cpus_pm/cpus_pm_binary.code<br />
* board/sunxi/sun8iw6/box_standby/cpus_pm/cpus_pm_binary.code<br />
* tools/gen_check_sum<br />
<br />
= CedarX =<br />
<br />
{{MBOX INFO|The hardware block which hardware accelerates decoding and encoding of video codecs, called [[Video Engine]], [[Cedar Engine]] or also know as VPU, was '''successful reversed-engineered''' to the point of allowing the use of hardware decoding for the most popular video codecs. Find more at the '''[[Cedrus|Cedrus project]]''' wiki page.<br />
<br />
The linux-sunxi community has all the information required to create a proper driver that can be mainlined, without the need of the source-code of this CedarX software library, that only has use to:<br />
* Comply with the (L)GPL License.<br />
* Be used as a source of documentation for the few parts and video codecs still not yet reversed-engineered.}}<br />
<br />
<br />
While Allwinner has published some code on their [https://github.com/allwinner-zh/media-codec github account], they are not compliant yet. It seems that they feel that producing only code for those codecs that actively used LGPLed symbols is enough, and that they intend to keep the other codes under wraps. This is not how the LGPL works (as it applies to the full and complete binaries produced earlier, and not to some rewritten or restructured code produced today), and Allwinner should by now be very much aware of it.<br />
<br />
{{todo|TODO:}} This is the userspace library that implements media decoding (JPEG, MPEG2/4, h264, VC1, VP6/8, ...). This driver is [[CedarX_binary_analysis |a mix and match of many bits]], including some reference decoders, surrounded by allwinner and hw specific code. But, crucially, several parts of it have been taken straight from libavcodec from the FFMPEG project. This code is LGPL, but since this code has been adapted and included, CedarX is not a dependency and the LGPL applies to the whole library, forcing Allwinner to release the lot.<br />
<br />
Also, [[CedarXPlayerTest]] has staticly linked in ffmpeg demuxer.</div>
Nove
https://linux-sunxi.org/index.php?title=VLC&diff=17681
VLC
2016-06-16T21:52:51Z
<p>Nove: </p>
<hr />
<div>This page is about how to use [https://en.wikipedia.org/wiki/VLC_media_player VLC media player] in sunxi devices with hardware accelerated video decoding.<br />
<br />
<br />
VLC media player works with hardware accelerated video decoding by using [[Cedrus/libvdpau-sunxi]] as VDPAU backend.<br />
<br />
<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=CedarX/VLC&diff=17679
CedarX/VLC
2016-06-16T20:57:32Z
<p>Nove: Add redirect to vlc main page.</p>
<hr />
<div>{{MBOX OBSOLETE|'''The content of this page is obsolete and its use is not recommend.'''<br />
|extratext=This instructions of how to build and use are based in a VLC fork which is not in active development (older more than 4 years from last activity). The added support depends in an very old version of the binary libraries, that are incompatible with the ''frequent'' API changes of newer versions of [[CedarX]] binary libraries.<br />
}}<br />
{{MBOX NOTE|'''For how to use [[VLC]] in sunxi, please see the [[VLC|VLC main page]].}}<br />
<br />
VLC also known as "''VideoLAN Client''" player is a open-source cross-platform video player. For more info check the wikipedia.<br />
<br />
VLC support for [[CedarX]] was added by Wills Wang. VLC support and especially this page is work in progress.<br />
<br />
= Compilation =<br />
<br />
In building tree, the default libvecore.so is armhf version, it come from [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armhf/libvecore/libvecore.so here]<br />
<br />
If you use armel, you need replace it with [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armel/libvecore/libvecore.so this version]<br />
<br />
Build libcedarx at first, do:<br />
<pre><br />
git clone https://github.com/willswang/libcedarx<br />
cd libcedarx<br />
./autogen.sh<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path><br />
make<br />
make install<br />
</pre><br />
<br />
If the above fails at autogen.sh, be sure to install libtools.<br />
<pre><br />
apt-get install libtool<br />
</pre><br />
<br />
Build vlc with cedar support, do:<br />
<pre><br />
apt-get build-dep vlc #only once, both target and host rootfs<br />
apt-get remove lua5.2 # may not be needed on your system, you must use lua 5.1 to build vlc<br />
git clone https://github.com/willswang/vlc<br />
cd vlc<br />
./bootstrap<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path> --enable-cedar<br />
make<br />
make install<br />
</pre><br />
<br />
If you dont want to cross-compile, remove --host, set prefix to /usr and compile on device, compilation time is around one and a half hours.<br />
<br />
= Usage =<br />
Give everyone rights to use disp and [[CedarX]]<br />
<pre><br />
chmod 777 /dev/disp<br />
chmod 777 /dev/cedar_dev<br />
</pre><br />
Start vlc with command line interface:<br />
<pre><br />
cvlc --demux ffmpeg --codec cedar --vout cedarfb --no-osd <media file><br />
</pre><br />
You can use standard cvlc hotkeys, but remember that there is no OSD support yet.<br />
<br />
= Problems/TODO =<br />
* Is fb0_scaler_mode_enable/fb1_scaler_mode_enable needs to be disabled for cedarfb?<br />
* No output modules support apart from cedarfb which uses raw framebuffer access (not compatible with xf86-video-mali and any other driver/device that wants to write raw at the same moment).<br />
* No support for GUI of the VLC, only command line VLC is supported<br />
* 1080p and such movies with high bitrate sometimes buffer too slow and frames are dropping.<br />
* No support for OSD because of lack of YUV420<br />
<br />
[[Category:Software]]<br />
[[Category:Software]]</div>
Nove
https://linux-sunxi.org/index.php?title=CedarX/VLC&diff=17678
CedarX/VLC
2016-06-16T20:33:54Z
<p>Nove: Mark this page as with obsolete content.</p>
<hr />
<div>{{MBOX OBSOLETE|'''The content of this page is obsolete and its use is not recommend.'''<br />
|extratext=This instructions of how to build and use are based in a VLC fork which is not in active development (older more than 4 years from last activity). The added support depends in an very old version of the binary libraries, that are incompatible with the ''frequent'' API changes of newer versions of [[CedarX]] binary libraries.<br />
}}<br />
<br />
VLC also known as "''VideoLAN Client''" player is a open-source cross-platform video player. For more info check the wikipedia.<br />
<br />
VLC support for [[CedarX]] was added by Wills Wang. VLC support and especially this page is work in progress.<br />
<br />
<br />
'''NOTE:''' This page describe how build VLC with closed binary blob as we now have opensource support for H264 and MPEG12 codecs with VDPAU, so better use it instead blob in common cases.<br />
= Compilation =<br />
<br />
In building tree, the default libvecore.so is armhf version, it come from [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armhf/libvecore/libvecore.so here]<br />
<br />
If you use armel, you need replace it with [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armel/libvecore/libvecore.so this version]<br />
<br />
Build libcedarx at first, do:<br />
<pre><br />
git clone https://github.com/willswang/libcedarx<br />
cd libcedarx<br />
./autogen.sh<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path><br />
make<br />
make install<br />
</pre><br />
<br />
If the above fails at autogen.sh, be sure to install libtools.<br />
<pre><br />
apt-get install libtool<br />
</pre><br />
<br />
Build vlc with cedar support, do:<br />
<pre><br />
apt-get build-dep vlc #only once, both target and host rootfs<br />
apt-get remove lua5.2 # may not be needed on your system, you must use lua 5.1 to build vlc<br />
git clone https://github.com/willswang/vlc<br />
cd vlc<br />
./bootstrap<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path> --enable-cedar<br />
make<br />
make install<br />
</pre><br />
<br />
If you dont want to cross-compile, remove --host, set prefix to /usr and compile on device, compilation time is around one and a half hours.<br />
<br />
= Usage =<br />
Give everyone rights to use disp and [[CedarX]]<br />
<pre><br />
chmod 777 /dev/disp<br />
chmod 777 /dev/cedar_dev<br />
</pre><br />
Start vlc with command line interface:<br />
<pre><br />
cvlc --demux ffmpeg --codec cedar --vout cedarfb --no-osd <media file><br />
</pre><br />
You can use standard cvlc hotkeys, but remember that there is no OSD support yet.<br />
<br />
= Problems/TODO =<br />
* Is fb0_scaler_mode_enable/fb1_scaler_mode_enable needs to be disabled for cedarfb?<br />
* No output modules support apart from cedarfb which uses raw framebuffer access (not compatible with xf86-video-mali and any other driver/device that wants to write raw at the same moment).<br />
* No support for GUI of the VLC, only command line VLC is supported<br />
* 1080p and such movies with high bitrate sometimes buffer too slow and frames are dropping.<br />
* No support for OSD because of lack of YUV420<br />
<br />
[[Category:Software]]<br />
[[Category:Software]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus/Supported_Codec_Feature_Matrix&diff=17648
Cedrus/Supported Codec Feature Matrix
2016-06-15T21:51:28Z
<p>Nove: The left side of the table is about the hardware.</p>
<hr />
<div>In this colorful table is represented what is understood and supported by hardware in the '''left side''', the designation VE+Number are the video engine hardware version and above are the SoCs were found. Here are only SoCs and hardware versions which was confirmed or reported, the ones that aren't here should and are expected to be very equal in mode.<br />
<br />
The '''right side''' represents the state of software. Take notice about the PoC (Prof of Concept) in which only exists for demonstration the correct understanding about the working of the hardware, sometimes the creation of this PoC is skipped.<br />
<br />
{| border="1px" cellpadding="4px" style="border-collapse:collapse; border: 0px solid #A44444; text-align: center;"<br />
|colspan=" 3" style="border: 0px;"| <br />
|A10/A20 || A13 || A31s || A80 || A33 || H3 || A64 <br />
|rowspan="99" style="border: 0px; min-width: 10px"| ||colspan="2" style="border: 0px"| Software Support<br />
|-<br />
!style="border: 0px"| !! subengine !! codec <br />
! VE1623 !! VE1625 !! VE1633 !! VE1639 !! VE1667 !! VE1680 !! VE1689 <br />
! PoC !! libvdpau-sunxi <br />
|-style="background-color: #77FF77"<br />
|rowspan="18"| decoder ||rowspan="11"| [[VE_Register_guide#MPEG_Engine_Registers|0x100]] || JPEG/MJPEG <br />
|colspan="7"| baseline profile only<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| MPEG1 <br />
|colspan="7"|<br />
| ||<br />
|-style="background-color: #77FF77"<br />
| MPEG2 <br />
|colspan="7"|<br />
| ||<br />
|-style="background-color: #FFFF77"<br />
| MPEG4 <br />
|colspan="7"|<br />
|style="background-color:#FFFFFF"| ||<br />
|-style="background-color: #FFFF77"<br />
| MS-MPEG4 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||rowspan="3" style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #FF7777"<br />
| WMV1 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FF7777"<br />
| WMV2 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FFFF77"<br />
| DIVX <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #FFFF77"<br />
| XDIV <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||rowspan="5" style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #FF7777"<br />
| H263 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FF7777"<br />
| VP6 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #CCCCCC"<br />
| rowspan=" 2"| ? || Sorenson <br />
|colspan="7"| Unconfirmed<br />
|<br />
|-style="background-color: #CCCCCC"<br />
| AVS <br />
|colspan="7"| Unconfirmed<br />
|<br />
|-style="background-color: #77FF77"<br />
| rowspan=" 2"| [[VE_Register_guide#H264_Engine_Registers|0x200]] || H264 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #77FF77"<br />
| VP8 <br />
|colspan="7"|<br />
| ||style="background-color: #FFFFFF"| n.a.<br />
|-style="background-color: #FF7777"<br />
| rowspan=" 1"| [[VE_Register_guide#VC1_Engine_Registers|0x300]] || VC1/WMV9 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #CCCCCC"<br />
| rowspan=" 1"| [[VE_Register_guide#RMVB_Engine_Registers|0x400]] || RMVB<br />
|colspan="7"| Unconfirmed<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| rowspan=" 1"| [[VE_Register_guide#HEVC_Engine_Registers|0x500]] || H265 <br />
|colspan="5" style="background-color: #FFFFFF"| ||colspan="2"|8bits<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #77FF77"<br />
|rowspan=" 2"|encoder <br />
|rowspan=" 2"| [[VE_Register_guide#ISP_Engine_Registers|0xa00]]</br>[[VE_Register_guide#AVC_Encoder_Engine_Registers|0xb00]]<br />
| JPEG/MJPEG<br />
|colspan="2"|baseline profile only||colspan="5" style="background-color: #FFAA77"| not tried because of no time to try<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| H264 <br />
|colspan="2"|baseline profile only||colspan="5" style="background-color: #FFAA77"| not tried because of no time to try<br />
|No B frames ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #CCCCCC"<br />
|rowspan=" 1"|decoder ||rowspan=" 1"| 0xe00 || JPEG<br />
|colspan="5" style="background-color: #FFFFFF"| ||colspan="2"| Unconfirmed<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-<br />
|}<br />
<br />
<br />
As can be seen in this table with the color of green, the most used video codecs are already fully reversed engineered. The codecs that are still missing are too old or/and obsolete and aren't used anymore for the creation of new video content. The content (video files) that exists encoded in this codecs is in the great majority not beyond standard definition, meaning that the task of decoding is easy done with just software decode by cpu.<br />
For this reason this codecs aren't a priority to work on.<br />
<br />
If anyone has a need for a yet to be support codec, please contact the people involved in the cedrus project to find what can be arranged.</div>
Nove
https://linux-sunxi.org/index.php?title=FFmpeg&diff=17647
FFmpeg
2016-06-15T21:32:21Z
<p>Nove: Explain this page.</p>
<hr />
<div>{{MBOX OUTDATED|'''This ffmpeg fork is without an active maintainer and its hardware h264 encoding implemention is based from an older version of the proof of concept source-code.'''<br />
|extratext=Per this reason this implementation doesn't represent the actual state of knowledge about the workings of h264 encoding in the hardware. Moreover because the vendor's kernel doesn't have any future, the little time available by the people working in the [[Cedrus|Cedrus project]] is concentrated in pushing the mainlineable driver forward, meaning any work in the encoding side will always be second priority.<br />
<br />
Anyone that wishes to work in improving the use of h264 encoding with the vendor's kernel, is very welcome to join [[Cedrus|Cedrus project]], we will be very glad to help make this possible.<br />
}}<br />
{{MBOX NOTE|'''The following is only ''working'' with 3.4 kernel and in A10/A10s/A13/A20 SOCs.'''}}<br />
<br />
== FFmpeg for sunxi ==<br />
<br />
This is an FFmpeg implementation for sunxi devices based on great work by jemk & alcantor (i.e cedrus ).<br />
<br />
Here is the git address: https://github.com/stulluk/FFmpeg-Cedrus<br />
<br />
The repository contains a *deb file for easy installation trial.<br />
<br />
( Please see readme)<br />
<br />
Typical usage to capture from CSI camera and encode to h264 via Cedrus library and output as RTSP:<br />
<br />
ffmpeg -f v4l2 -video_size 640x480 -i /dev/video0 -pix_fmt nv12 -r 25 -c:v cedrus264 -f mpegts - | cvlc - --sout "#:rtp{sdp=rtsp://:8554/}"<br />
<br />
( TBD)</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus/libvdpau-sunxi&diff=17646
Cedrus/libvdpau-sunxi
2016-06-15T20:06:38Z
<p>Nove: Use message box template.</p>
<hr />
<div>{{MBOX OUTDATED|'''This page is kind of outdated and needs a cleanup.'''<br />
|extratext=Prerequisites, the OSD part and memory reservation have changed a bit with the last few commits. See the [https://github.com/linux-sunxi/libvdpau-sunxi README] in the meantime.}}<br />
<br />
== Overview ==<br />
<br />
[https://github.com/linux-sunxi/libvdpau-sunxi libvdpau-sunxi] is a vdpau driver backend implementation for the [https://en.wikipedia.org/wiki/VDPAU vdpau framework].<br />
<br />
[[ Cedrus/libvdpau_integration_matrix ]] gives an overview about the VDPAU API functions currently supported in libvdpau-sunxi.<br />
It also lists the required functions for various programs.<br />
<br />
== Installation ==<br />
{{MBOX NOTE|'''SECURITY NOTE''': Currently the open source driver is implemented as replacement of the blob. Blob and current open source replacement driver (libvdpau-sunxi) use Allwinner's kernel driver that remaps registers for use in userspace, with Allwinner's display driver used for hardware overlay. Together with access to physical memory, and dangerous VE DMA ability it makes a serious security problem.<br />
<br />
That should be replaced in a proper way in ongoing mainline process.}}<br />
<br />
=== Prerequisites ===<br />
Various things are required to get cedrus to play back video. This list can act as a quick start.<br />
* [http://linux-sunxi.org/Kernel_arguments Proper memory reservation]<br />
* cedar module either compiled in or the module loaded<br />
* write access permissions on /dev/disp and /dev/cedar_dev<br />
:* on A10/A20, A13, add /dev/g2d for osd<br />
:* on A33 or H3, add /dev/ion<br />
* libvdpau-sunxi library installed<br />
* enviroment variable telling libvdpau which library to use<br />
<br />
=== Reserve memory for the VPU ===<br />
The VE needs a block of memory to store (de)coded frames in. The kernel needs to be informed about this before booting.<br />
To do so, the kernel command line needs to be modified. This can be done at compiletime or by modifying the bootloaders [[Kernel_arguments]]. By default Allwinner reserves 80 Megabytes but depending on the player being used and video being decoded, less can suffice or more can be necessary. Feel free to experiment with the amount, but if available, 128 MiB is a nice number to test things with. This can be set by the following kernel argument.<br />
<pre>sunxi_ve_mem_reserve=128</pre><br />
<br />
'''NOTE:''' This kernel parameter is ignored in recent linux-sunxi 3.4 kernels, if CMA is enabled in kernel configuration.<br />
If CONFIG_CMA=y, ve_size is hardcoded to 80MB in sunxi_cedar kernel module.<br />
<br />
For A33 or H3, if you use the kernel from official SDK, you should modify the memory reservation configuration of ion memory allocator. 32 MB seems to be enough for 720p H.264 decoding, and 64MB is enough for 1080p H.264 decoding.<br />
<br />
=== Cedar module ===<br />
Depending on where the kernel came from, the Cedar kernel driver is either available as module or built in. To see whether it is available, check whether /dev/cedar_dev exists. If not, run ''modprobe sun4i_cedar_dev'' (in future versions this should be called sunxi_cedar_dev, and for official kernel of A33 or H3 it's called cedar_dev). There should now be a /dev/cedar_dev.<br />
<br />
==== Write access persmissions ====<br />
To be able to pass data to the VE, proper permission to /dev/cedar_dev is required.<br />
<br />
For testing, manually setting permissions is fine.<br />
<pre>chown <username>:<usergroup> /dev/cedar_dev<br />
chmod 666 /dev/cedar_dev</pre><br />
The VE only decodes the video codec. To have it appear on the display, write access permission to /dev/disp is required.<br />
<pre>chown <username>:<usergroup> /dev/disp<br />
chmod 666 /dev/disp</pre><br />
For the official kernel of A33 or H3, cedar do not allocate memory by itself, but it uses ion. So for these devices, write and read permission to /dev/ion is needed.<br />
<pre>chown <username>:<usergroup> /dev/ion<br />
chmod 666 /dev/ion</pre><br />
<br />
To do this properly with udev rules, create files for each under /etc/udev/rules.d/<br />
<br />
50-disp.rules<br />
<pre>KERNEL=="disp", MODE="0660", GROUP="video"</pre><br />
50-cedar.rules<br />
<pre>KERNEL=="cedar_dev", MODE="0660", GROUP="video"</pre><br />
50-ion.rules<br />
<pre>KERNEL=="ion", MODE="0660", GROUP="video"</pre><br />
<br />
=== Installing libvdpau-sunxi library ===<br />
There are currently no pre-compiled binaries available and have to be compiled from source. This most likely has to be performed on the target device, while possible to be cross compiled.<br />
==== Prerequisites ====<br />
* git (yum install git | apt-get install git | emerge git)<br />
* gcc (yum group-install "Development Tools" | apt-get install build-essential)<br />
* libvdpau-dev >= 0.9 (yum install libvdpau-dev | apt-get install libvdpau-dev | emerge libvdpau)<br />
<br />
==== Compiling source ====<br />
The current libvdpau-sunxi code is stored on github.<br />
<pre>git clone https://github.com/linux-sunxi/libvdpau-sunxi.git<br />
cd libvdpau-sunxi<br />
make<br />
sudo make install</pre><br />
Pay close attention as to where these libraries get installed. Depending on the distro in use, it's most likely they will need to be put in '''/usr/lib/vdpau'''. If they are not put there, manually copy them there.<br />
With the driver now installed, it is important to tell vdpau to use this library. By default it will try to load and use the nVidia vdpau implementation.<br />
<pre>export VDPAU_DRIVER=sunxi</pre><br />
The latest git version of [[Xorg#fbturbo_driver]] can report the DRI2 VDPAU name as 'sunxi', if 'sunxi_cedar_mod' kernel module loaded successfully. See [https://github.com/ssvb/xf86-video-fbturbo/commit/4c7313c6db9ee770f39740c735268c88fcd136cf commit]<br />
<br />
=== Playing video ===<br />
With everything setup properly, it should now be possible to playback hardware accelerated media!<br />
<br />
The best test file would be one of the well known sample media's. The big buck bunny is an often used one.<br />
http://samplemedia.linaro.org/H264/big_buck_bunny_1080p_H264_AAC_25fps_7200K.MP4<br />
<br />
Depending if you use mpv or mplayer2, the following options are required.<br />
For mplayer2:<br />
<pre> mplayer -vo vdpau -vc ffmpeg12vdpau,ffh264vdpau, [filename]</pre><br />
For mpv:<br />
<pre> mpv --vo=vdpau --hwdec=vdpau --hwdec-codecs=all [filename]</pre><br />
<br />
Note: There have been reports that some mplayer versions in certain repositories are not compiled with vdpau support.<br />
<br />
Now you can also try to use other files, but note it has to be mpeg1, mpeg2 or h264 encoded!<br />
<br />
=== OSD support ===<br />
Now we have simple OSD implementation, using g2d hardware.<br />
<br />
Access to g2d (as xorg turbo driver) is also required.<br />
<pre>chmod 666 /dev/g2d</pre><br />
<br />
To do this properly with udev rules, create a file under /etc/udev/rules.d/<br />
<br />
50-g2d.rules<br />
<pre>KERNEL=="g2d", MODE="0660", GROUP="video"</pre><br />
and make sure that the user wanting to decode video is in the video group!<br />
<br />
To turn on OSD support during runtime:<br />
<br />
<pre>export VDPAU_OSD=1</pre><br />
<br />
<br />
Note: mplayer's "-ass" osd not currently supported, due to lack of 'alpha only' surfaces support in current g2d driver<br />
<br />
<br />
[[Category:Tutorial]]<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus/libvdpau-sunxi&diff=17645
Cedrus/libvdpau-sunxi
2016-06-15T20:03:12Z
<p>Nove: Remove linebreak.</p>
<hr />
<div>{{MBOX OUTDATED|'''This page is kind of outdated and needs a cleanup.'''<br />
|extratext=Prerequisites, the OSD part and memory reservation have changed a bit with the last few commits. See the [https://github.com/linux-sunxi/libvdpau-sunxi README] in the meantime.}}<br />
<br />
== Overview ==<br />
<br />
[https://github.com/linux-sunxi/libvdpau-sunxi libvdpau-sunxi] is a vdpau driver backend implementation for the [https://en.wikipedia.org/wiki/VDPAU vdpau framework].<br />
<br />
[[ Cedrus/libvdpau_integration_matrix ]] gives an overview about the VDPAU API functions currently supported in libvdpau-sunxi.<br />
It also lists the required functions for various programs.<br />
<br />
== Installation ==<br />
<div style="border: 1px solid #AA88AA; background-color: #EEEEDD; padding: 0.5em 1em"><br />
'''SECURITY NOTE''': Currently the open source driver is implemented as replacement of the blob. Blob and current open source replacement driver (libvdpau-sunxi) use Allwinner's kernel driver that remaps registers for use in userspace, with Allwinner's display driver used for hardware overlay. Together with access to physical memory, and dangerous VE DMA ability it makes a serious security problem.<br />
<br />
That should be replaced in a proper way in ongoing mainline process. <br />
</div><br />
<br />
=== Prerequisites ===<br />
Various things are required to get cedrus to play back video. This list can act as a quick start.<br />
* [http://linux-sunxi.org/Kernel_arguments Proper memory reservation]<br />
* cedar module either compiled in or the module loaded<br />
* write access permissions on /dev/disp and /dev/cedar_dev<br />
:* on A10/A20, A13, add /dev/g2d for osd<br />
:* on A33 or H3, add /dev/ion<br />
* libvdpau-sunxi library installed<br />
* enviroment variable telling libvdpau which library to use<br />
<br />
=== Reserve memory for the VPU ===<br />
The VE needs a block of memory to store (de)coded frames in. The kernel needs to be informed about this before booting.<br />
To do so, the kernel command line needs to be modified. This can be done at compiletime or by modifying the bootloaders [[Kernel_arguments]]. By default Allwinner reserves 80 Megabytes but depending on the player being used and video being decoded, less can suffice or more can be necessary. Feel free to experiment with the amount, but if available, 128 MiB is a nice number to test things with. This can be set by the following kernel argument.<br />
<pre>sunxi_ve_mem_reserve=128</pre><br />
<br />
'''NOTE:''' This kernel parameter is ignored in recent linux-sunxi 3.4 kernels, if CMA is enabled in kernel configuration.<br />
If CONFIG_CMA=y, ve_size is hardcoded to 80MB in sunxi_cedar kernel module.<br />
<br />
For A33 or H3, if you use the kernel from official SDK, you should modify the memory reservation configuration of ion memory allocator. 32 MB seems to be enough for 720p H.264 decoding, and 64MB is enough for 1080p H.264 decoding.<br />
<br />
=== Cedar module ===<br />
Depending on where the kernel came from, the Cedar kernel driver is either available as module or built in. To see whether it is available, check whether /dev/cedar_dev exists. If not, run ''modprobe sun4i_cedar_dev'' (in future versions this should be called sunxi_cedar_dev, and for official kernel of A33 or H3 it's called cedar_dev). There should now be a /dev/cedar_dev.<br />
<br />
==== Write access persmissions ====<br />
To be able to pass data to the VE, proper permission to /dev/cedar_dev is required.<br />
<br />
For testing, manually setting permissions is fine.<br />
<pre>chown <username>:<usergroup> /dev/cedar_dev<br />
chmod 666 /dev/cedar_dev</pre><br />
The VE only decodes the video codec. To have it appear on the display, write access permission to /dev/disp is required.<br />
<pre>chown <username>:<usergroup> /dev/disp<br />
chmod 666 /dev/disp</pre><br />
For the official kernel of A33 or H3, cedar do not allocate memory by itself, but it uses ion. So for these devices, write and read permission to /dev/ion is needed.<br />
<pre>chown <username>:<usergroup> /dev/ion<br />
chmod 666 /dev/ion</pre><br />
<br />
To do this properly with udev rules, create files for each under /etc/udev/rules.d/<br />
<br />
50-disp.rules<br />
<pre>KERNEL=="disp", MODE="0660", GROUP="video"</pre><br />
50-cedar.rules<br />
<pre>KERNEL=="cedar_dev", MODE="0660", GROUP="video"</pre><br />
50-ion.rules<br />
<pre>KERNEL=="ion", MODE="0660", GROUP="video"</pre><br />
<br />
=== Installing libvdpau-sunxi library ===<br />
There are currently no pre-compiled binaries available and have to be compiled from source. This most likely has to be performed on the target device, while possible to be cross compiled.<br />
==== Prerequisites ====<br />
* git (yum install git | apt-get install git | emerge git)<br />
* gcc (yum group-install "Development Tools" | apt-get install build-essential)<br />
* libvdpau-dev >= 0.9 (yum install libvdpau-dev | apt-get install libvdpau-dev | emerge libvdpau)<br />
<br />
==== Compiling source ====<br />
The current libvdpau-sunxi code is stored on github.<br />
<pre>git clone https://github.com/linux-sunxi/libvdpau-sunxi.git<br />
cd libvdpau-sunxi<br />
make<br />
sudo make install</pre><br />
Pay close attention as to where these libraries get installed. Depending on the distro in use, it's most likely they will need to be put in '''/usr/lib/vdpau'''. If they are not put there, manually copy them there.<br />
With the driver now installed, it is important to tell vdpau to use this library. By default it will try to load and use the nVidia vdpau implementation.<br />
<pre>export VDPAU_DRIVER=sunxi</pre><br />
The latest git version of [[Xorg#fbturbo_driver]] can report the DRI2 VDPAU name as 'sunxi', if 'sunxi_cedar_mod' kernel module loaded successfully. See [https://github.com/ssvb/xf86-video-fbturbo/commit/4c7313c6db9ee770f39740c735268c88fcd136cf commit]<br />
<br />
=== Playing video ===<br />
With everything setup properly, it should now be possible to playback hardware accelerated media!<br />
<br />
The best test file would be one of the well known sample media's. The big buck bunny is an often used one.<br />
http://samplemedia.linaro.org/H264/big_buck_bunny_1080p_H264_AAC_25fps_7200K.MP4<br />
<br />
Depending if you use mpv or mplayer2, the following options are required.<br />
For mplayer2:<br />
<pre> mplayer -vo vdpau -vc ffmpeg12vdpau,ffh264vdpau, [filename]</pre><br />
For mpv:<br />
<pre> mpv --vo=vdpau --hwdec=vdpau --hwdec-codecs=all [filename]</pre><br />
<br />
Note: There have been reports that some mplayer versions in certain repositories are not compiled with vdpau support.<br />
<br />
Now you can also try to use other files, but note it has to be mpeg1, mpeg2 or h264 encoded!<br />
<br />
=== OSD support ===<br />
Now we have simple OSD implementation, using g2d hardware.<br />
<br />
Access to g2d (as xorg turbo driver) is also required.<br />
<pre>chmod 666 /dev/g2d</pre><br />
<br />
To do this properly with udev rules, create a file under /etc/udev/rules.d/<br />
<br />
50-g2d.rules<br />
<pre>KERNEL=="g2d", MODE="0660", GROUP="video"</pre><br />
and make sure that the user wanting to decode video is in the video group!<br />
<br />
To turn on OSD support during runtime:<br />
<br />
<pre>export VDPAU_OSD=1</pre><br />
<br />
<br />
Note: mplayer's "-ass" osd not currently supported, due to lack of 'alpha only' surfaces support in current g2d driver<br />
<br />
<br />
[[Category:Tutorial]]<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus/libvdpau-sunxi&diff=17644
Cedrus/libvdpau-sunxi
2016-06-15T20:02:32Z
<p>Nove: Use message box template.</p>
<hr />
<div>{{MBOX OUTDATED|'''This page is kind of outdated and needs a cleanup.'''<br />
|extratext=Prerequisites, the OSD part and memory reservation have changed a bit with the last few commits. See the [https://github.com/linux-sunxi/libvdpau-sunxi README] in the meantime.}}<br />
</br><br />
== Overview ==<br />
<br />
[https://github.com/linux-sunxi/libvdpau-sunxi libvdpau-sunxi] is a vdpau driver backend implementation for the [https://en.wikipedia.org/wiki/VDPAU vdpau framework].<br />
<br />
[[ Cedrus/libvdpau_integration_matrix ]] gives an overview about the VDPAU API functions currently supported in libvdpau-sunxi.<br />
It also lists the required functions for various programs.<br />
<br />
== Installation ==<br />
<div style="border: 1px solid #AA88AA; background-color: #EEEEDD; padding: 0.5em 1em"><br />
'''SECURITY NOTE''': Currently the open source driver is implemented as replacement of the blob. Blob and current open source replacement driver (libvdpau-sunxi) use Allwinner's kernel driver that remaps registers for use in userspace, with Allwinner's display driver used for hardware overlay. Together with access to physical memory, and dangerous VE DMA ability it makes a serious security problem.<br />
<br />
That should be replaced in a proper way in ongoing mainline process. <br />
</div><br />
<br />
=== Prerequisites ===<br />
Various things are required to get cedrus to play back video. This list can act as a quick start.<br />
* [http://linux-sunxi.org/Kernel_arguments Proper memory reservation]<br />
* cedar module either compiled in or the module loaded<br />
* write access permissions on /dev/disp and /dev/cedar_dev<br />
:* on A10/A20, A13, add /dev/g2d for osd<br />
:* on A33 or H3, add /dev/ion<br />
* libvdpau-sunxi library installed<br />
* enviroment variable telling libvdpau which library to use<br />
<br />
=== Reserve memory for the VPU ===<br />
The VE needs a block of memory to store (de)coded frames in. The kernel needs to be informed about this before booting.<br />
To do so, the kernel command line needs to be modified. This can be done at compiletime or by modifying the bootloaders [[Kernel_arguments]]. By default Allwinner reserves 80 Megabytes but depending on the player being used and video being decoded, less can suffice or more can be necessary. Feel free to experiment with the amount, but if available, 128 MiB is a nice number to test things with. This can be set by the following kernel argument.<br />
<pre>sunxi_ve_mem_reserve=128</pre><br />
<br />
'''NOTE:''' This kernel parameter is ignored in recent linux-sunxi 3.4 kernels, if CMA is enabled in kernel configuration.<br />
If CONFIG_CMA=y, ve_size is hardcoded to 80MB in sunxi_cedar kernel module.<br />
<br />
For A33 or H3, if you use the kernel from official SDK, you should modify the memory reservation configuration of ion memory allocator. 32 MB seems to be enough for 720p H.264 decoding, and 64MB is enough for 1080p H.264 decoding.<br />
<br />
=== Cedar module ===<br />
Depending on where the kernel came from, the Cedar kernel driver is either available as module or built in. To see whether it is available, check whether /dev/cedar_dev exists. If not, run ''modprobe sun4i_cedar_dev'' (in future versions this should be called sunxi_cedar_dev, and for official kernel of A33 or H3 it's called cedar_dev). There should now be a /dev/cedar_dev.<br />
<br />
==== Write access persmissions ====<br />
To be able to pass data to the VE, proper permission to /dev/cedar_dev is required.<br />
<br />
For testing, manually setting permissions is fine.<br />
<pre>chown <username>:<usergroup> /dev/cedar_dev<br />
chmod 666 /dev/cedar_dev</pre><br />
The VE only decodes the video codec. To have it appear on the display, write access permission to /dev/disp is required.<br />
<pre>chown <username>:<usergroup> /dev/disp<br />
chmod 666 /dev/disp</pre><br />
For the official kernel of A33 or H3, cedar do not allocate memory by itself, but it uses ion. So for these devices, write and read permission to /dev/ion is needed.<br />
<pre>chown <username>:<usergroup> /dev/ion<br />
chmod 666 /dev/ion</pre><br />
<br />
To do this properly with udev rules, create files for each under /etc/udev/rules.d/<br />
<br />
50-disp.rules<br />
<pre>KERNEL=="disp", MODE="0660", GROUP="video"</pre><br />
50-cedar.rules<br />
<pre>KERNEL=="cedar_dev", MODE="0660", GROUP="video"</pre><br />
50-ion.rules<br />
<pre>KERNEL=="ion", MODE="0660", GROUP="video"</pre><br />
<br />
=== Installing libvdpau-sunxi library ===<br />
There are currently no pre-compiled binaries available and have to be compiled from source. This most likely has to be performed on the target device, while possible to be cross compiled.<br />
==== Prerequisites ====<br />
* git (yum install git | apt-get install git | emerge git)<br />
* gcc (yum group-install "Development Tools" | apt-get install build-essential)<br />
* libvdpau-dev >= 0.9 (yum install libvdpau-dev | apt-get install libvdpau-dev | emerge libvdpau)<br />
<br />
==== Compiling source ====<br />
The current libvdpau-sunxi code is stored on github.<br />
<pre>git clone https://github.com/linux-sunxi/libvdpau-sunxi.git<br />
cd libvdpau-sunxi<br />
make<br />
sudo make install</pre><br />
Pay close attention as to where these libraries get installed. Depending on the distro in use, it's most likely they will need to be put in '''/usr/lib/vdpau'''. If they are not put there, manually copy them there.<br />
With the driver now installed, it is important to tell vdpau to use this library. By default it will try to load and use the nVidia vdpau implementation.<br />
<pre>export VDPAU_DRIVER=sunxi</pre><br />
The latest git version of [[Xorg#fbturbo_driver]] can report the DRI2 VDPAU name as 'sunxi', if 'sunxi_cedar_mod' kernel module loaded successfully. See [https://github.com/ssvb/xf86-video-fbturbo/commit/4c7313c6db9ee770f39740c735268c88fcd136cf commit]<br />
<br />
=== Playing video ===<br />
With everything setup properly, it should now be possible to playback hardware accelerated media!<br />
<br />
The best test file would be one of the well known sample media's. The big buck bunny is an often used one.<br />
http://samplemedia.linaro.org/H264/big_buck_bunny_1080p_H264_AAC_25fps_7200K.MP4<br />
<br />
Depending if you use mpv or mplayer2, the following options are required.<br />
For mplayer2:<br />
<pre> mplayer -vo vdpau -vc ffmpeg12vdpau,ffh264vdpau, [filename]</pre><br />
For mpv:<br />
<pre> mpv --vo=vdpau --hwdec=vdpau --hwdec-codecs=all [filename]</pre><br />
<br />
Note: There have been reports that some mplayer versions in certain repositories are not compiled with vdpau support.<br />
<br />
Now you can also try to use other files, but note it has to be mpeg1, mpeg2 or h264 encoded!<br />
<br />
=== OSD support ===<br />
Now we have simple OSD implementation, using g2d hardware.<br />
<br />
Access to g2d (as xorg turbo driver) is also required.<br />
<pre>chmod 666 /dev/g2d</pre><br />
<br />
To do this properly with udev rules, create a file under /etc/udev/rules.d/<br />
<br />
50-g2d.rules<br />
<pre>KERNEL=="g2d", MODE="0660", GROUP="video"</pre><br />
and make sure that the user wanting to decode video is in the video group!<br />
<br />
To turn on OSD support during runtime:<br />
<br />
<pre>export VDPAU_OSD=1</pre><br />
<br />
<br />
Note: mplayer's "-ass" osd not currently supported, due to lack of 'alpha only' surfaces support in current g2d driver<br />
<br />
<br />
[[Category:Tutorial]]<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_OBSOLETE&diff=17643
Template:MBOX OBSOLETE
2016-06-15T19:59:35Z
<p>Nove: Message box template for old pages with obsolete content.</p>
<hr />
<div>{{MBOX<br />
|image=[[File:MBOX icon deletion.png]]<br />
|color=border-color: #EE2222; background-color: #FFDDDD<br />
|{{{1|'''The content of this page is obsolete.'''}}}<br />
|extratext={{{extratext|}}}<br />
}}<br />
[[Category:Outdated Pages]]</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_EDIT&diff=17642
Template:MBOX EDIT
2016-06-15T19:56:23Z
<p>Nove: Nove moved page Template:MBOX EDIT to Template:MBOX OUTDATED</p>
<hr />
<div>#REDIRECT [[Template:MBOX OUTDATED]]</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_OUTDATED&diff=17641
Template:MBOX OUTDATED
2016-06-15T19:56:23Z
<p>Nove: Nove moved page Template:MBOX EDIT to Template:MBOX OUTDATED</p>
<hr />
<div>{{MBOX<br />
|image=[[File:MBOX icon edit-clear.png]]<br />
|color=border-color: #EECC22; background-color: #FFEECC<br />
|{{{1|'''The content of this page is outdated and requires to be reviewed for accuracy.'''}}}<br />
|extratext={{{extratext|}}}<br />
}}<br />
[[Category:Outdated Pages]]</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_OUTDATED&diff=17640
Template:MBOX OUTDATED
2016-06-15T19:55:56Z
<p>Nove: Message box template for pages with outdated content that needs to be reviewed.</p>
<hr />
<div>{{MBOX<br />
|image=[[File:MBOX icon edit-clear.png]]<br />
|color=border-color: #EECC22; background-color: #FFEECC<br />
|{{{1|'''The content of this page is outdated and requires to be reviewed for accuracy.'''}}}<br />
|extratext={{{extratext|}}}<br />
}}<br />
[[Category:Outdated Pages]]</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_INFO&diff=17639
Template:MBOX INFO
2016-06-15T19:44:27Z
<p>Nove: Message box template for informational messages.</p>
<hr />
<div>{{MBOX<br />
|image=[[File:MBOX icon information.png]]<br />
|color=border-color: #2288EE; background-color: #DDEEFF<br />
|{{{1|}}}<br />
}}</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX_NOTE&diff=17638
Template:MBOX NOTE
2016-06-15T19:41:50Z
<p>Nove: Message box template for important notices/warnings.</p>
<hr />
<div>{{MBOX<br />
|image=[[File:MBOX icon important.png]]<br />
|color=border-color: #EE8822; background-color: #FFEEDD<br />
|{{{1|}}}<br />
}}</div>
Nove
https://linux-sunxi.org/index.php?title=File:MBOX_icon_deletion.png&diff=17637
File:MBOX icon deletion.png
2016-06-15T19:36:54Z
<p>Nove: https://commons.wikimedia.org/wiki/File:Deletion_icon.svg</p>
<hr />
<div>https://commons.wikimedia.org/wiki/File:Deletion_icon.svg</div>
Nove
https://linux-sunxi.org/index.php?title=File:MBOX_icon_edit-clear.png&diff=17636
File:MBOX icon edit-clear.png
2016-06-15T19:36:16Z
<p>Nove: https://commons.wikimedia.org/wiki/File:Edit-clear.svg</p>
<hr />
<div>https://commons.wikimedia.org/wiki/File:Edit-clear.svg</div>
Nove
https://linux-sunxi.org/index.php?title=File:MBOX_icon_information.png&diff=17635
File:MBOX icon information.png
2016-06-15T19:35:00Z
<p>Nove: https://commons.wikimedia.org/wiki/File:Information_icon4.svg</p>
<hr />
<div>https://commons.wikimedia.org/wiki/File:Information_icon4.svg</div>
Nove
https://linux-sunxi.org/index.php?title=File:MBOX_icon_important.png&diff=17634
File:MBOX icon important.png
2016-06-15T19:34:04Z
<p>Nove: https://commons.wikimedia.org/wiki/File:Ambox_important.svg</p>
<hr />
<div>https://commons.wikimedia.org/wiki/File:Ambox_important.svg</div>
Nove
https://linux-sunxi.org/index.php?title=Template:MBOX&diff=17633
Template:MBOX
2016-06-15T19:25:27Z
<p>Nove: Template base for uniform message boxes.</p>
<hr />
<div>{|style="margin: 0.7em; border-width: 1px 1px 1px 10px; border-style: solid; {{{color}}}"<br />
|style="padding: 0.2em; vertical-align: baseline;"|{{{image}}}<br />
|style="width:100%; padding-left: 0.2em; padding-right: 0.2em; vertical-align: baseline;"|{{{1}}}{{{extratext|}}}<br />
|}</div>
Nove
https://linux-sunxi.org/index.php?title=VE_Planning&diff=17616
VE Planning
2016-06-13T20:52:57Z
<p>Nove: Add presentation slides of Video4Linux2: Path to a Standardized Video Codec API.</p>
<hr />
<div>This is a page for planning the effort of the writing of a driver for the video engine in the right way (well, in the best possible way).<br />
<br />
__NOTOC__<br />
<br />
== V4L2 codec interface ==<br />
<br />
The only existent kernel framework suited for this type of hardware device is the video-for-linux [http://linuxtv.org/downloads/v4l-dvb-apis/codec.html codec interface].<br />
Presentation [https://events.linuxfoundation.org/images/stories/pdf/lceu2012_debski.pdf Video4Linux2: Path to a Standardized Video Codec API] and [[VE/V4L2_mem2mem/Others|Other users]] of this same framework.<br />
<br />
However not without a few obstacles.<br />
<br />
==== Tile format ====<br />
* For the tile format specific to this video engine, V4l2 doesn't have (yet) this pixel format. Until then, as in v4l2, the pixel formats are represented as fourcc identifiers in an u32 value. It will be sufficient to define this custom tile format in the driver and user headers. [http://lxr.free-electrons.com/ident?i=IPU_PIX_FMT_GBR24 Example.]<br />
<br />
==== 256MiB limit ====<br />
* This video engine requires contiguous physical memory buffers to be located in the lower 256MiB of memory.<br />
: ideally if possible instead of having a fixed memory region, all should be available for allocation<br />
:* videobuf2-dma-contig, allocates physical contiguous buffers, but to restrit to low 256M, requires ''dma_declare_coherent_memory'' to be called. [http://lxr.free-electrons.com/source/drivers/media/platform/s5p-mfc/s5p_mfc.c?v=3.17#L1021 Example.] The declared memory region must be reserved using the generic [http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt /reserved-memory] node.<br />
:* from outside mainline there exists also [https://android.googlesource.com/kernel/exynos.git/+/android-exynos-3.4/drivers/media/video/videobuf2-cma-phys.c videobuf2-cma-phys] and [https://android.googlesource.com/kernel/exynos.git/+/android-exynos-3.4/drivers/media/video/videobuf2-ion.c videobuf2-ion]<br />
<br />
==== Decoder batching ====<br />
* decoder will work notably faster when frames are batched (not one shoot mode).<br />
<br />
==== Device nodes ====<br />
* not all combination of the aggregated pixel formats (from isp subengine, encoder, decoder) are possible.<br />
: From this [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/82907/focus=82918 example], we can see that multiple device nodes is preferred. The use of three device nodes appears to be the most suited.<br />
<pre><br />
/dev/videoW<br />
isp subengine - raw pixel formats => raw pixel formats subset<br />
<br />
/dev/videoX<br />
encoder - raw pixel formats => bitstream formats<br />
<br />
/dev/videoY<br />
decoder - bitstream formats => raw pixel format<br />
</pre><br />
<br />
==== No parsing in kernel ====<br />
* this video engine is a fixed function engine, this is a advantage by its simplicity, but in other ways this means that bitstream parsing can't be done by a firmware. Bitstream parsing in the kernel is not allowed.<br />
<br />
:* More information from a[http://linuxtv.org/news.php?entry=2013-11-30.mchehab Linux Kernel Media Workshop] where this matter was discussed, copied here for easyness.<br />
<br />
<pre><br />
13: Hugues Fruchet: Video codecs<br />
<br />
There's a need to parse bitstream fields for those codecs, but that requires complex code (10K lines). Moving it to kernel could make it unstable, as it is harsh to write those parsers without any risk of causing crashes.<br />
It seems to be better to put those parsers inside libv4l, using an open source license.<br />
<br />
Results:<br />
<br />
Drivers that require proprietary user space components should stay out of mainline<br />
Multi-format buffers could be useful here<br />
The hardware/firmware needs a lot of data extracted from the bitstream next to the bitstream itself. This is a custom format, so it is OK to add a new pixelformat for each of those formats. Such complex parsing should be done in userspace in libv4l2.<br />
If very little parsing is required (MPEG), then that can be done in the kernel instead.<br />
Recommendation is to start simple with e.g. just an MPEG implementation.<br />
</pre><br />
<br />
:* [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/97350 '''Request API'''], is a newer still experimental addition to V4L2 and Media Controller framework. In resume, any number of controls (configuration data) can be packed in a object called ''request'', and if attached to a buffer, the driver can apply this configuration to the hardware when processing said buffer.<br />
::* [http://blogs.s-osg.org/planning-future-media-linux-linux-kernel-summit-media-workshop-seoul-south-korea/ Linux Kernel Summit Media WorkShop - Planning Out the Future of Media on Linux]<br />
::* [https://openiotelc2016.sched.org/event/6DAG/v4l2-on-steroids-the-request-api-laurent-pinchart V4L2 on steroids: The Request API] ([https://www.youtube.com/watch?v=W35u-hU22hY Video.])<br />
::* [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/101993 Media Request API (RFC patches)] [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/102395 v2]<br />
<br />
== Way to go forward. ==<br />
* initial we can ignore that bitstream parsing is been done in the kernel, and first aim to have a working driver.<br />
:* other option can be to split the driver in a common part that can be mainlined, and for each codec do as a submodule that can compiled out of tree. This also allows the distributions to choose which codecs to include.<br />
* this means that initially we will not worry about working for the inclusion in the mainline kernel (because the bitstream parsing will be rejected.)<br />
* using libv4l2 as suggested above to do the bitstream parsing in user space.<br />
:* in this [http://git.linuxtv.org/cgit.cgi/v4l-utils.git/tree/lib/libv4l2/libv4l2.c?id=56676348e48648146250aaf2770b2f8a6bd796cd#n21 paragraph] is explained that libv4l2 can transparently convert between formats, when the requested format mismatch the formats supported by the hardware driver. As in V4L2 a codec bitstream is considered as in equal mode to an image format, it should be possible to also convert bitstream format to a pre-parsed bitstream format compatible with the specificities of this video engine.<br />
:* there is also [http://git.linuxtv.org/cgit.cgi/v4l-utils.git/commit/lib/libv4l2/v4l2-plugin.c libv4l2 plugins], in which could offer a possible way to do this transparent bitstream conversion.<br />
:* perpendicular [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/91865/focus=92195 discussion] that reaffirms the place for bitstream parsers.<br />
<br />
== Progress status ==<br />
<i>Detail of the conclusion of each step for each target kernel version (sunxi-3.4 / distro kernel / mainline).</i><br />
<br />
== User Land ==<br />
* Will aim to preserve the compatibility with similar users of v4l2 codec interfaces. Within its limits.<br />
* By the motive of the numerous video codecs apis in existence and equal mode the number of media players, the implementation of the support is outside the scope of this effort.<br />
* Only will be written simple programs for testing and example in how to use.<br />
<br />
==== gstreamer ====<br />
* already includes [http://cgit.freedesktop.org/gstreamer/gst-plugins-good/tree/sys/v4l2/gstv4l2videodec.c support] for v4l2 mem2mem ''decoder'' devices. [http://gstconf.ubicast.tv/videos/the-development-of-video4linux-decoder-support/ the development of video4linux decoder support]<br />
<br />
* ''encoder'' is '''''work in progress''''' [https://bugzilla.gnome.org/show_bug.cgi?id=728438 Bug 728438 - v4l2: Implement a v4l2 video encoder ]<br />
<br />
==== ffmpeg ====<br />
<br />
* there were some [http://thread.gmane.org/gmane.comp.video.ffmpeg.devel/185764 patches] but they didn't go forward.<br />
<br />
[[Category:Cedrus]]</div>
Nove
https://linux-sunxi.org/index.php?title=Mali_binary_driver&diff=17555
Mali binary driver
2016-06-08T20:06:49Z
<p>Nove: Use video engine for the hardware.</p>
<hr />
<div>The sun4i and sun5i use a [[Mali400]]MP1 and sun7i uses Mali400MP2 (dual-core GPU). We have support available for several versions of the mali binary driver stack, even though our kernel tends to come with the R3P0 version. We support fbdev and X11 as windowing systems.<br />
<br />
= Mali and UMP kernel drivers =<br />
<br />
First [[Display|get a working display driver]].<br />
<br />
== Modules ==<br />
<br />
The default config for the kernel should have the Mali kernel drivers as modules. You should be able to load it by simply running<br />
<br />
<pre class="brush: bash"><br />
modprobe mali<br />
</pre><br />
<br />
A cleaner solution is to have the module autoloaded at boot, by adding the following to /etc/modules:<br />
<pre class="brush: bash"><br />
mali<br />
</pre><br />
<br />
If you use [[Xorg#fbturbo_driver | a properly set up Xserver]], then the necessary modules will be automatically loaded when X starts.<br />
<br />
== Device permission ==<br />
<br />
The default permissions of /dev/ump and /dev/mali make these unusable for normal users. Add a file to /etc/udev/rules.d/, perhaps called 50-mali.rules, with the following content:<br />
<pre class="brush: bash"><br />
KERNEL=="mali", MODE="0660", GROUP="video"<br />
KERNEL=="ump", MODE="0660", GROUP="video"<br />
</pre><br />
This should give a user belonging to the group video the right permissions to use the mali successfully.<br />
<br />
= Installing the UMP (Unified Memory Provider) userspace library =<br />
<br />
== From a package ==<br />
<br />
There are [[Packages|some packages available]] which fully install libUMP for you.<br />
<br />
== From source ==<br />
<br />
=== Prequisites ===<br />
<br />
libUMP only depends on libc and the '''ump''' kernel module.<br />
<br />
'''Debian/Ubuntu'''<br />
<pre class="brush: bash"><br />
apt-get install git build-essential autoconf libtool<br />
</pre><br />
<br />
'''Fedora'''<br />
<br />
<pre class="brush: bash"><br />
yum install gcc autoconf libtool git<br />
</pre><br />
<br />
=== Clone the repo ===<br />
<br />
<pre class="brush: bash"><br />
git clone https://github.com/linux-sunxi/libump.git<br />
cd libump<br />
</pre><br />
<br />
=== Build ===<br />
'''Building on Debian/Ubuntu'''<br />
<br />
If you are on debian or ubuntu, you should build the package.<br />
<br />
<pre class="brush: bash"><br />
apt-get install debhelper dh-autoreconf fakeroot pkg-config<br />
</pre><br />
<br />
Then build the packages, after descending into the git tree:<br />
<br />
<pre class="brush: bash"><br />
dpkg-buildpackage -b<br />
</pre><br />
<br />
When that finishes, install the main package:<br />
<br />
<pre class="brush: bash"><br />
dpkg -i ../libump_*.deb<br />
</pre><br />
<br />
'''Building on other distributions'''<br />
<br />
<pre class="brush: bash"><br />
autoreconf -i<br />
./configure --prefix=/usr<br />
make<br />
make install<br />
</pre><br />
<br />
= Installing the Mali userspace driver =<br />
<br />
== Prerequisites ==<br />
<br />
=== Building Tools ===<br />
<br />
You will need to have the basic building tools installed:<br />
<br />
'''Debian/Ubuntu'''<br />
<br />
<pre class="brush: bash"><br />
apt-get install git build-essential autoconf automake<br />
</pre><br />
<br />
''' Fedora '''<br />
<br />
<pre class="brush: bash"><br />
yum install gcc autoconf libtool git<br />
</pre><br />
<br />
=== X11 development files (optional) ===<br />
<br />
If you wish to install the X11 version of the mali binaries, then you also need to install this:<br />
<br />
'''Debian/Ubuntu'''<br />
<br />
<pre class="brush: bash"><br />
apt-get install xutils-dev<br />
</pre><br />
<br />
'''Fedora'''<br />
<br />
<pre class="brush: bash"><br />
yum install xorg-x11-server-devel<br />
</pre><br />
<br />
== Clone the repo ==<br />
<br />
<pre class="brush: bash"><br />
git clone --recursive https://github.com/linux-sunxi/sunxi-mali.git<br />
cd sunxi-mali<br />
</pre><br />
<br />
== Configure ==<br />
<br />
Before you follow the instructions in this section, make sure that you have loaded [[#Modules|the mali module]], so that the kernel driver version can be autodetected.<br />
<br />
Now you can descend into sunxi-mali, and you can let it detect your environment:<br />
<br />
<pre class="brush: bash"><br />
make config<br />
</pre><br />
<br />
It will state the detected environment, like so:<br />
<br />
<pre class="brush: bash"><br />
rm -f config.mk<br />
make config.mk<br />
make[1]: Entering directory `/home/libv/sunxi/sunxi-mali'<br />
make -f Makefile.config<br />
ABI="armhf" (Detected)<br />
VERSION="r3p0" (Detected)<br />
EGL_TYPE="x11" (Detected)<br />
make[2]: Entering directory `/home/libv/sunxi/sunxi-mali'<br />
echo "MALI_VERSION ?= r3p0" > config.mk<br />
echo "MALI_LIBS_ABI ?= armhf" >> config.mk<br />
echo "MALI_EGL_TYPE ?= x11" >> config.mk<br />
make[2]: Leaving directory `/home/libv/sunxi/sunxi-mali'<br />
make[1]: Leaving directory `/home/libv/sunxi/sunxi-mali'<br />
</pre><br />
<br />
In case it complains about missing libdri2.so.1, follow the instructions in the [[#libdri2 (r3p0 X11 only)|libdri2 (r3p0 X11 only)]] section and try again.<br />
<br />
== Dependencies ==<br />
<br />
The sunxi-mali build system checks whether the selected library has all of its dependencies resolved. You might need to resolve these dependencies through your package manager.<br />
<br />
=== libdri2 (r3p0 X11 only) ===<br />
<br />
Some distributions have '''libdri2''' compiled into the X11 binary, instead of having it as a separate library and package. If that is the case, you need to compile libdri2 manually.<br />
<br />
You may need to install the following dependencies on Debian. On Fedora, the package '''xorg-x11-server-devel''' should be enough.<br />
<br />
<pre class="brush: bash">apt-get install libx11-dev libxext-dev libdrm-dev x11proto-dri2-dev libxfixes-dev</pre><br />
<br />
To build the library:<br />
<br />
<pre class="brush: bash">git clone https://github.com/robclark/libdri2<br />
cd libdri2<br />
./autogen.sh<br />
./configure --prefix=/usr<br />
make<br />
make install<br />
ldconfig</pre><br />
<br />
== Install ==<br />
<br />
By following will install the GLES/EGL binaries into /usr/lib/, and EGL/GLES headers to /usr/include/:<br />
<br />
<pre class="brush: bash">make install</pre><br />
<br />
= Setting up the windowing system =<br />
<br />
== Framebuffer ==<br />
<br />
If you are using the framebuffer/fbdev version of the binaries, then your setup work is done.<br />
<br />
You might want to change the fbdev device used by setting the '''FRAMEBUFFER''' environment variable.<br />
<br />
== Xserver ==<br />
<br />
If you want a GLES capable Xserver, then you will need to install the fbturbo driver according to our [[Xorg#fbturbo_driver|Xorg page]].<br />
<br />
= Verifying the EGL/GLES driver stack =<br />
<br />
From the mali-sunxi repository, you can run:<br />
<br />
<pre class="brush: bash"><br />
make test<br />
</pre><br />
<br />
In case it complains about "/usr/bin/ld: /tmp/ccD8ofcr.o: undefined reference to symbol 'XNextEvent'", you probably need to add the linker option "-lX11" to the Makefile and try again.<br />
<br />
After it successfully builds, run:<br />
<br />
<pre class="brush: bash"><br />
test/test<br />
</pre><br />
<br />
And you should be able to see a smoothed triangle, either written out to the top left corner of the framebuffer, or in an X window. The console will tell you which renderer is being used:<br />
<br />
<pre><br />
...<br />
GL Vendor: "ARM"<br />
GL Renderer: "Mali-400 MP"<br />
GL Version: "OpenGL ES 2.0"<br />
...<br />
</pre><br />
<br />
Double check with:<br />
<pre class="brush: bash"><br />
es2_info<br />
</pre><br />
<br />
Success!<br />
<br />
= Common pitfalls =<br />
<br />
== Mesa libraries are still in the way ==<br />
<br />
If you are seeing one of this, it means Mesa is still used instead of Mali:<br />
<br />
<pre><br />
libEGL warning: failed to create a pipe screen for Mali DRI2<br />
libEGL warning: DRI2: failed to open Mali DRI2 (search paths /usr/lib/arm-linux-gnueabihf/dri)<br />
</pre><br />
<br />
<pre><br />
libEGL warning: failed to create a pipe screen for lima<br />
libEGL warning: DRI2: failed to open lima (search paths /usr/lib/arm-linux-gnueabihf/dri:${ORIGIN}/dri:/usr/lib/dri)<br />
</pre><br />
<br />
Then the current best advice is to move the mesa-egl aside:<br />
<br />
<pre class="brush: bash"><br />
mv /usr/lib/arm-linux-gnueabihf/mesa-egl/ /usr/lib/arm-linux-gnueabihf/.mesa-egl/<br />
</pre><br />
<br />
If not present, look for ''libGLESv2.so'', ''libEGL.so'' and their symlink in ''/usr/lib'' (and subdir); then, make them point to ''libMali.so''.<br />
<br />
<pre class="brush: bash"><br />
ln -s /usr/lib/libMali.so /usr/lib/libGLESv2.so<br />
...<br />
</pre><br />
<br />
Awkward, but at least gets you something workable.<br />
<br />
= See also =<br />
<br />
* [[Display | Setting up a working display driver]]<br />
* [[Xorg | Setting up an accelerated driver for the Xserver]]<br />
* [[Video Engine | Hardware media acceleration (video decoding)]].<br />
<br />
[[Category:Tutorial]]<br />
[[Category:Proprietary Software]]</div>
Nove
https://linux-sunxi.org/index.php?title=Xorg&diff=17553
Xorg
2016-06-08T20:05:58Z
<p>Nove: Use video engine for the hardware.</p>
<hr />
<div>This page contains an explanation of how to set up the X server for our hardware.<br />
<br />
= fbdev driver =<br />
<br />
X tends to come preinstalled with the standard fbdev driver. This gives you a working environment, but it might be lagging a bit, and you get no hardware supported 2d or 3d acceleration.<br />
<br />
No action needs to be taken for this driver to work though, you only need to have [[Display|a working display driver]].<br />
<br />
= fbturbo driver =<br />
<br />
fbturbo driver works on both mainline and legacy (sunxi-3.x) kernels, utilizing a combination of various acceleration options to make your desktop experience much more fluid:<br />
* NEON CPU instructions<br />
* sunxi G2D 2D acceleration (legacy only)<br />
* sunxi display engine for overlays and hardware cursor (legacy only)<br />
* Mali GPU acceleration for 3D/GL applications<br />
<br />
<br />
For Mali support see [[Mali_binary_driver | our Mali binary driver installation howto]]).<br />
<br />
This driver is a further development from the ARM provided mali xorg driver, which is available from [http://github.com/linux-sunxi/xf86-video-mali our sunxi repositories], but that driver only provides Mali support and no NEON or 2D acceleration, and doesn't use the sunxi display engine.<br />
<br />
== Manual build ==<br />
=== Prerequisites ===<br />
<br />
For debian or ubuntu you need the following development packages for building X drivers:<br />
<br />
<pre class="brush: bash"><br />
apt-get install git build-essential xorg-dev xutils-dev x11proto-dri2-dev libltdl-dev libtool automake <br />
</pre><br />
<br />
If you intend to use the Mali GPU, then you need to first [[Mali_binary_driver | install libUMP]] as well.<br />
<br />
=== Clone the repository ===<br />
<br />
Now get the fbturbo xf86 driver (from the 0.4.0 release tag):<br />
<br />
<pre class="brush: bash"><br />
git clone -b 0.4.0 https://github.com/ssvb/xf86-video-fbturbo.git<br />
cd xf86-video-fbturbo<br />
</pre><br />
<br />
=== Build ===<br />
<pre class="brush: bash"><br />
autoreconf -vi<br />
./configure --prefix=/usr<br />
make<br />
</pre><br />
<br />
=== Installation ===<br />
<br />
<pre class="brush: bash"><br />
make install<br />
</pre><br />
<br />
=== Configuration ===<br />
Then copy over the default xorg.conf for the fbturbo driver (the preferred location for xorg.conf would be /etc/X11/ instead of /usr/share/X11/xorg.conf.d/):<br />
<pre class="brush: bash"><br />
rm /usr/share/X11/xorg.conf.d/99-sunxifb.conf<br />
cp xorg.conf /etc/X11/xorg.conf<br />
</pre><br />
<br />
== Packages ==<br />
<br />
For some distributions, there are packages available. For more information, check our [[Packages | packages howto]].<br />
<br />
== Verification ==<br />
You should now be able to (re)start your xserver, have a quick look through /var/log/Xorg.0.log to verify that the correct driver has been loaded:<br />
<br />
<pre><br />
...<br />
(II) Module fbturbo: vendor="X.Org Foundation"<br />
compiled for 1.12.4, module version = 0.4.0<br />
Module class: X.Org Video Driver<br />
ABI class: X.Org Video Driver, version 12.1<br />
(II) FBTURBO: driver for framebuffer: fbturbo<br />
(--) using VT number 7<br />
...<br />
</pre><br />
<br />
== Common issues ==<br />
<br />
=== The log complains about being compiled without libUMP ===<br />
<br />
If you have the following lines in your Xorg.0.log, then you need to install libUMP (or the libump-dev package), and then rebuild and install the fbturbo driver.<br />
<br />
<pre><br />
(II) FBTURBO(0): no 3D acceleration because the driver has been compiled without libUMP<br />
(II) FBTURBO(0): if this is wrong and needs to be fixed, please check ./configure log<br />
</pre><br />
<br />
=== The screen goes off and will not restart until reset ===<br />
This seems to be linked (to be verified) to fbturbo (former name sunxifb). DPMS has 3 options : standby, suspend and off. The standby and suspend options work. But DPMS off put off the screen with the following error on console and in dmesg :<br />
<br />
<pre> disp clks: lcd 146000000 pre_scale 1 hdmi 146000000 pll 219000000 2x 1</pre><br />
<br />
A workaround is to add in /usr/share/X11/xorg.conf.d/99-sunxifb.conf, in <code>Section "Device"</code>:<br />
<pre> Option "OffTime" "0"</pre><br />
<br />
However, it you still have problems, you can disable DPMS completely in the X server by properly editing xorg.conf (located either in /etc/X11 or /usr/share/X11/xorg.conf.d) add adding a Screen and Monitor section that disables DPMS. The following xorg.conf works with xf86-video-fbturbo (the new name of xf86-video-sunxifb):<br />
<br />
<pre><br />
Section "Screen"<br />
Identifier "My Screen"<br />
Device "fbturbo device"<br />
Monitor "My Monitor"<br />
EndSection<br />
<br />
Section "Device"<br />
Identifier "fbturbo device"<br />
Driver "fbturbo"<br />
Option "fbdev" "/dev/fb0"<br />
Option "SwapbuffersWait" "true"<br />
EndSection<br />
<br />
Section "Monitor"<br />
Identifier "My Monitor"<br />
Option "DPMS" "false"<br />
EndSection<br />
</pre><br />
<br />
Another suggested option is to alter the other DPMS timers (OffTime is sometimes called BlankTime):<br />
<pre><br />
Section "ServerLayout"<br />
Identifier "ServerLayout0"<br />
Option "StandbyTime" "0"<br />
Option "SuspendTime" "0"<br />
EndSection<br />
<br />
</pre><br />
<br />
= See also =<br />
<br />
* [[Display|Display driver setup]]<br />
* [[Mali_binary_driver | How to install the Mali binary 3D driver]]<br />
* [[Video Engine| Hardware Media acceleration]]<br />
* [[GraphicsPerformanceX11]]<br />
* [[Benchmarks]]<br />
<br />
[[Category:Tutorial]]<br />
[[Category:Software]]</div>
Nove
https://linux-sunxi.org/index.php?title=Display&diff=17552
Display
2016-06-08T20:03:58Z
<p>Nove: Use video engine for the hardware.</p>
<hr />
<div><br />
When you are using a ready made image for your device your display should be configured automatically.<br />
<br />
In script.bin it is defined what display output is used and what hardware lines are used for connecting the output.<br />
<br />
On [[kernel arguments]] you can specify the video mode used on the output or override autodetection on outputs that support EDID.<br />
<br />
<br />
== Framebuffer console at boot ==<br />
<br />
To see boot traces you need to put all display related modules into linux kernel (3.4 branch ATM) :<br />
<br />
<pre><br />
CONFIG_FB_SUNXI=y<br />
CONFIG_FB_SUNXI_LCD=y<br />
CONFIG_FB_SUNXI_HDMI=y<br />
<br />
CONFIG_FRAMEBUFFER_CONSOLE=y<br />
CONFIG_FONT_8x8=y<br />
CONFIG_FONT_8x16=y<br />
</pre><br />
<br />
Then change u-boot config console=xxx parameter to tty0. If you want to still use a serial console you can define multiple consoles. For example "console=ttyS0,115200 console=tty0".<br />
<br />
<br />
== Changing resolution ==<br />
<br />
The initial display resolution at boot time is defined in script.bin (fex-file), and can be overridden by [[Kernel_arguments|kernel command line options]].<br />
<br />
But you can change it afterward by using this tool from doozan forum:<br />
<pre><br />
http://forum.doozan.com/read.php?6,9002<br />
https://github.com/doozan/a10-tools/blob/master/a10_display.c<br />
</pre><br />
Tool changes display timings for wanted resolution. After that you'll need to set correct resolution with fbset -xres xxx -yres xxx<br />
<br />
There is also a utility called a10disp that requires that version 1.0 or later of the sunxi kernel display driver is available (linux-sunxi 3.4.43 or later). It can be used to show information about the current display mode, change the resolution and color depth of HDMI modes, and switch between LCD and HDMI output. It can be found at http://www.github.com/hglm/a10disp.git.<br />
<br />
== Framebuffer tips ==<br />
=== Blanking timeout ===<br />
The framebuffer has a default blank screen saver. The timeout (in seconds) can be changed or disabled (0) with a kernel parameter:<br />
consoleblank=0<br />
<br />
=== Unblank ===<br />
To blank or unblank a framebuffer, you can set 0 or 1 in this sysfs entry:<br />
/sys/class/graphics/fb0/blank<br />
<br />
=== Hide cursor ===<br />
If you are running a console on your framebuffer, you can hide the cursor with a kernel parameter:<br />
vt.global_cursor_default=0<br />
<br />
It can be changed at runtime by setting 0 or 1 in this sysfs entry:<br />
/sys/class/graphics/fbcon/cursor_blink<br />
<br />
All these parameters can be changed with setterm command.<br />
<br />
=== Rotation ===<br />
You can rotate the framebuffer by supplying fbcon=rotate:<n> kernel parameter, where n can be one of the following.<br />
* 0 - normal orientation (0 degree)<br />
* 1 - clockwise orientation (90 degrees)<br />
* 2 - upside down orientation (180 degrees)<br />
* 3 - counterclockwise orientation (270 degrees)<br />
<br />
Alternatively you could echo <n> to <br />
/sys/class/graphics/fbcon/rotate<br />
after kernel has booted. For more see Documentation/fb/fbcon.txt in kernel tree.<br />
<br />
== HDMI ==<br />
<br />
If you are using a device with HDMI and have proper script.bin for your device setting up display is as simple as adding ''disp.screen0_output_mode=EDID'' to your kernel command line in boot.scr file. You can specify a fixed mode like ''disp.screen0_output_mode=1280x1024p60'' or a fallback in case EDID did not work ''disp.screen0_output_mode=EDID:1280x1024p60''. The supported fallback display modes are currently hardcoded in the disp driver. Looking at the clock table in https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.0/drivers/video/sunxi/disp/disp_clk.c might be helpful.<br />
<br />
Warning: some monitors require ''hdmi.audio=EDID:0'' option in the kernel command line to work correctly! Otherwise they are confused by the audio data embedded in the HDMI signal. The 1680x1050 monitors are known to be particularly bad in this respect.<br />
<br />
=== boot.scr ===<br />
<br />
<pre><br />
# fixed mode<br />
setenv bootargs console=tty0 hdmi.audio=EDID:0 disp.screen0_output_mode=1280x720p60 root=/dev/mmcblk0p1 rootwait panic=10<br />
<br />
# try EDID first, if it did not work fallback to specific output mode<br />
setenv bootargs console=tty0 hdmi.audio=EDID:0 disp.screen0_output_mode=EDID:1280x720p60 root=/dev/mmcblk0p1 rootwait panic=10<br />
</pre><br />
<br />
To generate a new boot.scr you need to edit boot.cmd file and then make a new boot.scr binary file.<br />
<br />
<pre><br />
mkimage -C none -A arm -T script -d <boot.cmd-file> boot.scr<br />
</pre><br />
<br />
<br />
=== script.bin/fex file===<br />
<br />
The settings in the [disp_init] section of the script.bin/fex file define the display output enabled at boot.<br />
<br />
An example configuration for HDMI:<br />
<br />
<pre><br />
[disp_init]<br />
disp_init_enable = 1<br />
disp_mode = 0<br />
screen0_output_type = 3<br />
screen0_output_mode = 4<br />
fb0_framebuffer_num = 2<br />
fb0_format = 10<br />
fb0_pixel_sequence = 0<br />
fb0_scaler_mode_enable = 0<br />
</pre><br />
<br />
* disp_mode selects single-screen output or different dual screen modes. Generally this is 0, which means use screen0 with fb0 (one screen).<br />
* screen0_output_type = 3 means HDMI output.<br />
* screen0_output_mode selects the video/monitor mode to use (resolution and refresh rate). See the table in the [[Fex_Guide#disp_init_configuration|Fex guide]].<br />
* fb0_framebuffer_num selects the number of buffers for fb0, generally you need 2 or more for video acceleration or Mali (3D), 3 is better.<br />
* fb0_format and fb0_pixel_sequence determine the pixel format in the framebuffer. The above example (values of 10 and 0) selects the most common variant of 32bpp truecolor (ARGB).<br />
* fb0_scaler_mode_enable selects whether the scaler should be enabled. Enabling it does not really scale pixels, it configures the scaler to scale pixels 1-to-1 which can fix screen refresh-related problems at 1080p resolution. See the section below.<br />
<br />
Similar parameter are defined for screen1 (which is usually disabled in practice).<br />
<br />
See the [[Fex_Guide##disp_init_configuration|Fex guide]] for a more detailed description.<br />
<br />
== LVDS ==<br />
<br />
See:<br />
[[Cubieboard/LVDS]]<br />
<br />
<br />
== VGA ==<br />
<br />
TBD<br />
<br />
<br />
== TV/CVBS ==<br />
<br />
The composite output can be used by configuring a screen in TV mode (2).<br /><br />
Then DAC #3 must be configured for composite (0).<br /><br />
Be sure to choose the right mode for your TV (PAL = 11 / NTSC = 14).<br />
<br />
[[Fex_Guide##disp_init_configuration|Fex]] example:<br />
<br />
[disp_init]<br />
disp_init_enable = 1<br />
disp_mode = 0<br />
screen0_output_type = 2<br />
screen0_output_mode = 11<br />
[tv_out_dac_para]<br />
dac_used = 1<br />
dac3_src = 0<br />
<br />
== Using two displays ==<br />
<br />
A10 has support for using two independent display outputs. Depending on board wiring and other hardware limitations not all output combinations may be possible. More information is available on our [[Dual Monitor Support]] page.<br />
<br />
== Using hardware scaler ==<br />
<br />
In some configurations turning the hardware scaler on or off in script.bin solves some issues.<br />
<br />
More specifcally. when driving a high bandwidth screen resolution (specifically 1920x1080 (1080p) with 32bpp at 60Hz) the Allwinner chip may sometimes be starved for memory bandwidth for refreshing the screen, especially if other components on the chip are utilizing a lot of memory bandwidth. The symptom is a "wavy screen" with most of the screen scanlines bouncing up and down quickly. This has been observed on an A10 in the Xorg environment (small bouncing), and on an A20 in X when running GLES accelerated Mali applications (heavy bouncing), especially with a large window size. Turning on "scaler mode" seems to solve the issue in both cases (sometimes it can be enough to lower the refresh rate, for example use 1080p at 50 Hz instead of 60 Hz). Scaler mode can be enabled by changing script.bin (fb0_scaler_mode_enable = 1) or using a runtime mode-setting utility such as [[http://www.github.com/hglm/a10disp.git]].<br />
<br />
== Driving LCDs ==<br />
<br />
Tablet LCDs can generally may be made to work provided that the LCD parameters in script.bin are correct (see [[Fex_Guide#lcd.5B0.2F1.5D_configuration|Fex guide LCD parameter section]]). Usually these will be need to be obtained from the script.bin in Android's bootloader partition (/dev/block/nanda). Normally you would use Android's script.bin (converted to .fex) as a base and adopt it for linux-sunxi.<br />
<br />
Tthe script.bin settings in the [disp_init] section (see [[Fex_Guide#disp_init_configuration|Fex guide]]) for Android tablets are usually configured to boot with screen0 on the LCD. A fex file configured to boot from LCD might like this:<br />
<br />
<pre><br />
[disp_init]<br />
disp_init_enable = 1<br />
disp_mode = 0<br />
screen0_output_type = 1<br />
screen0_output_mode = 4<br />
screen1_output_type = 1<br />
screen1_output_mode = 4<br />
fb0_framebuffer_num = 2<br />
fb0_format = 10<br />
fb0_pixel_sequence = 0<br />
fb0_scaler_mode_enable = 0<br />
fb0_width = 0<br />
fb0_height = 0<br />
fb1_framebuffer_num = 2<br />
fb1_format = 10<br />
fb1_pixel_sequence = 0<br />
fb1_scaler_mode_enable = 0<br />
fb1_width = 0<br />
fb1_height = 0<br />
</pre><br />
<br />
screen0_output_type = 1 means LCD. The screen0_output_mode probably does not matter when the output type is LCD, since the LCD resolution is defined in the LCD parameter section.<br />
<br />
Switching between LCD and HDMI at runtime works using a utility such as http://www.github.com/hglm/a10disp.git. Driving two screens (such as LCD and HDMI) at the same time (which the hardware supports) has not been extensively tested or verified.<br />
<br />
= See Also =<br />
* [[Sunxi_disp_driver_interface|IOCTLs for Allwinners disp driver.]]<br />
* [[Xorg|Setting up Xorg]]<br />
* [[Mali_binary_driver|Mali binary driver]]<br />
* [[Video Engine|Hardware Media decoding]]<br />
<br />
[[Category:tutorial]]</div>
Nove
https://linux-sunxi.org/index.php?title=VLC&diff=17551
VLC
2016-06-08T20:00:31Z
<p>Nove: Nove moved page VLC to CedarX/VLC</p>
<hr />
<div>#REDIRECT [[CedarX/VLC]]</div>
Nove
https://linux-sunxi.org/index.php?title=CedarX/VLC&diff=17550
CedarX/VLC
2016-06-08T20:00:31Z
<p>Nove: Nove moved page VLC to CedarX/VLC</p>
<hr />
<div>VLC also known as "''VideoLAN Client''" player is a open-source cross-platform video player. For more info check the wikipedia.<br />
<br />
VLC support for [[CedarX]] was added by Wills Wang. VLC support and especially this page is work in progress.<br />
<br />
<br />
'''NOTE:''' This page describe how build VLC with closed binary blob as we now have opensource support for H264 and MPEG12 codecs with VDPAU, so better use it instead blob in common cases.<br />
= Compilation =<br />
<br />
In building tree, the default libvecore.so is armhf version, it come from [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armhf/libvecore/libvecore.so here]<br />
<br />
If you use armel, you need replace it with [https://github.com/linux-sunxi/cedarx-libs/blob/master/libcedarv/linux-armel/libvecore/libvecore.so this version]<br />
<br />
Build libcedarx at first, do:<br />
<pre><br />
git clone https://github.com/willswang/libcedarx<br />
cd libcedarx<br />
./autogen.sh<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path><br />
make<br />
make install<br />
</pre><br />
<br />
If the above fails at autogen.sh, be sure to install libtools.<br />
<pre><br />
apt-get install libtool<br />
</pre><br />
<br />
Build vlc with cedar support, do:<br />
<pre><br />
apt-get build-dep vlc #only once, both target and host rootfs<br />
apt-get remove lua5.2 # may not be needed on your system, you must use lua 5.1 to build vlc<br />
git clone https://github.com/willswang/vlc<br />
cd vlc<br />
./bootstrap<br />
./configure --host=arm-linux-gnueabihf --prefix=<your installation path> --enable-cedar<br />
make<br />
make install<br />
</pre><br />
<br />
If you dont want to cross-compile, remove --host, set prefix to /usr and compile on device, compilation time is around one and a half hours.<br />
<br />
= Usage =<br />
Give everyone rights to use disp and [[CedarX]]<br />
<pre><br />
chmod 777 /dev/disp<br />
chmod 777 /dev/cedar_dev<br />
</pre><br />
Start vlc with command line interface:<br />
<pre><br />
cvlc --demux ffmpeg --codec cedar --vout cedarfb --no-osd <media file><br />
</pre><br />
You can use standard cvlc hotkeys, but remember that there is no OSD support yet.<br />
<br />
= Problems/TODO =<br />
* Is fb0_scaler_mode_enable/fb1_scaler_mode_enable needs to be disabled for cedarfb?<br />
* No output modules support apart from cedarfb which uses raw framebuffer access (not compatible with xf86-video-mali and any other driver/device that wants to write raw at the same moment).<br />
* No support for GUI of the VLC, only command line VLC is supported<br />
* 1080p and such movies with high bitrate sometimes buffer too slow and frames are dropping.<br />
* No support for OSD because of lack of YUV420<br />
<br />
[[Category:Software]]<br />
[[Category:Software]]</div>
Nove
https://linux-sunxi.org/index.php?title=Video_Engine&diff=17528
Video Engine
2016-06-06T21:29:24Z
<p>Nove: Remove the redirect and add the software pages.</p>
<hr />
<div>This page is related to the hardware, for software see.<br />
<br />
* '''[[CedarX]]''' Allwinner's Media framework software libraries.<br />
* '''[[Cedrus]]''' The project for a 100% libre open source driver and software.<br />
<br />
<br />
<br />
= What should this hardware block be called? =<br />
{{:Category:Video Engine}}<br />
<br />
[[Category:Video Engine]]<br />
[[Category:Cedrus]]<br />
[[Category:CedarX]]</div>
Nove
https://linux-sunxi.org/index.php?title=Allwinner_SoC_Family&diff=17527
Allwinner SoC Family
2016-06-06T20:01:07Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>= SoC series =<br />
<br />
== "A"-Series ==<br />
Based on ARMv7 Cortex-A cores (Cortex-A7, A8 and A15) targeted for high-end devices like digital media players, tablets, and netbooks:<br />
{| class="wikitable"<br />
| [[A10|Allwinner A10]] || <small>(sun4i)</small> || 1 x Cortex-A8 CPU-core<br />
|-<br />
| [[A13|Allwinner A13]] || <small>(sun5i)</small> || 1 x Cortex-A8 CPU-core<br />
|-<br />
| [[A10s|Allwinner A10s]] || <small>(sun5i)</small> || 1 x Cortex-A8 CPU-core<br />
|-<br />
| [[A20|Allwinner A20]] || <small>(sun7i)</small> || 2 x Cortex-A7 CPU-cores<br />
|-<br />
| [[A23|Allwinner A23]] || <small>(sun8i)</small> || 2 x Cortex-A7 CPU-cores<br />
|-<br />
| [[A31|Allwinner A31]] || <small>(sun6i)</small> || 4 x Cortex-A7 CPU-cores<br />
|-<br />
| [[A31s|Allwinner A31s]] || <small>(sun6i)</small> || 4 x Cortex-A7 CPU-cores<br />
|-<br />
| [[A33|Allwinner A33]] || <small>(sun8i)</small> || 4 x Cortex-A7 CPU-cores<br />
|-<br />
| [[A80|Allwinner A80]] || <small>(sun9i)</small> || 4 x Cortex-A7 CPU-cores + 4 x Cortex-A15 CPU-cores&nbsp;<br /><small>(using ARM big.LITTLE heterogeneous CPU architecture)</small><br />
|-<br />
| [[A83T|Allwinner A83T]]&nbsp; || <small>(sun8i)</small>&nbsp; || 8 x Cortex-A7 CPU-cores<br />
|}<br />
<br />
'''64-bit'''<br />
{| class="wikitable"<br />
| [[A64|Allwinner A64]]&nbsp; || <small>(sun50i)</small>&nbsp; || 4 x Cortex-A53 CPU-core<br />
|}<br />
<br />
== "H"-Series ==<br />
Based on ARMv7/ARMv8 Cortex-A cores (A7/A53) targeted for video OTT (over-the-top) boxes and high-end gaming consoles:<br />
{| class="wikitable"<br />
| [[H3|Allwinner H3]]&nbsp; || <small>(sun8i)</small>&nbsp; || 4 x Cortex-A7 CPU-core&nbsp;<br />
|-<br />
| [[H8|Allwinner H8]]<ref>http://www.allwinnertech.com/clq/processorh/AllwinnerH8.html</ref> || <small>(sun8i)</small> || 8 x Cortex-A7 CPU-core<br />
|}<br />
<br />
'''64-bit'''<br />
{| class="wikitable"<br />
| [[H64|Allwinner H64]]<ref>http://www.allwinnertech.com/plus/view.php?aid=6056</ref> || <small>(sun50i)</small> || 4 x Cortex-A53 CPU-core<br />
|}<br />
<br />
== "R"-Series ==<br />
<br />
{| class="wikitable"<br />
| [[R8|Allwinner R8]]<ref>http://www.allwinnertech.com/en/clq/R_series/2015/0514/R8.html</ref> || <small>(sun5i)</small>&nbsp; || 1 x Cortex-A8 CPU-core<br />
|-<br />
| [[R16|Allwinner R16]]<ref>http://www.allwinnertech.com/en/clq/R_series/2015/0514/R16.html</ref> || <small>(sun8i)</small> || 4 x Cortex-A7 CPU-core<br />
|-<br />
| [[R58|Allwinner R58]]<ref>http://www.allwinnertech.com/en/clq/R_series/2015/0514/R58.html</ref>&nbsp; || <small>(sun8i)</small> || 8 x Cortex-A7 CPU-core<br />
|}<br />
<br />
The Allwinner R8 is repackaged version of the A13. This SoC gets used in the minicomputer presented in Next Thing Co.'s [[NextThingCo CHIP|''C.H.I.P.'']] kickstarter project ("The $9 computer")<ref>http://nextthing.co/</ref>.<br />
<br />
By comparing the product pages the R16 seems to be a relabeled version of A33.<br />
<br />
'''64-bit'''<br />
{| class="wikitable"<br />
| [[R18|Allwinner R18]]|| <small>sun50i</small> || 4 x Cortex-A53 CPU-core<br />
|}<br />
<br />
== "F"-Series ==<br />
:'''{{note|The F series is not supported by the linux-sunxi community due to lack of developers and hardware. ''sun3i'' have only official linux support, ''sunii'' have no linux support, only Allwinner's "Melis" RTOS.}}'''<br />
<br />
Based on ARMv6 ARM926-EJS core and currently targeted for low market devices such as cheap ebook readers, etc.<br />
<br />
{| class="wikitable"<br />
| [[C100|Boxchip C100]] || <small>(sun3i)</small><br />
|-<br />
| [[E200|Boxchip E200]] || <small>(sun3i)</small><br />
|-<br />
| [[F20|Boxchip F20]] || <small>(sun3i)</small><br />
|-<br />
| [[F10|Boxchip F10]] <small>aka SoChip SC9800 aka Teclast T8100</small>&nbsp; || <small>(sunii)</small><br />
|-<br />
| [[F13|Boxchip F13]] || <small>(sunii)</small><br />
|-<br />
| [[F13|Boxchip F15]] <small>aka SoChip SC8600 aka Teclast T7200</small> || <small>(sunii)</small><br />
|-<br />
| [[F18|Boxchip F18]] || <small>(sunii)</small><br />
|}<br />
<br />
= 2013 naming scheme change =<br />
<br />
Initially, Allwinner named their SoCs chronologically:<br />
* sun4i = A10<br />
* sun5i = A13/A10s<br />
* sun6i = A31<br />
* sun7i = A20<br />
<br />
But, somewhere in 2013, Allwinner decided to update their naming scheme to be based on the ARM core used instead: (taken from the A80 SDK kernel code)<br />
<pre>sunxi<br />
|-- sun4i ----------------------------- : cortex-a8<br />
| |-- sun4iw1 --------------- wafer1<br />
| | `-- sun4iw1p1 ----- a10<br />
| `-- sun4iw2 --------------- wafer2<br />
| |-- sun4iw2p1 ----- a13<br />
| |-- sun4iw2p2 ----- a12<br />
| `-- sun4iw2p3 ----- a10s<br />
|-- sun8i ----------------------------- : cortex-a7 smp<br />
| |-- sun8iw1 --------------- wafer1<br />
| | |-- sun8iw1p1 ----- a31<br />
| | `-- sun8iw1p2 ----- a31s<br />
| |-- sun8iw2 --------------- wafer2<br />
| | |-- sun8iw2p1 ----- a20<br />
| | `-- sun8iw2p2<br />
| |-- sun8iw3 --------------- wafer3<br />
| | |-- sun8iw3p1 ----- a23<br />
| | `-- sun8iw3p2<br />
| |-- sun8iw5<br />
| | `-- sun8iw5p1 ----- a33<br />
| `-- sun8iw6<br />
| `-- sun8iw6p1 ----- a83t<br />
| `-- sun8iw7<br />
| `-- sun8iw7p1 ----- h3<br />
|-- sun9i ----------------------------- : cortex-a15.cortex-a7 big.LITTLE<br />
| `-- sun9iw1<br />
| |-- sun9iw1p1 ----- a80<br />
| `-- sun9iw1p2 ----- a80t<br />
`-- sun50i ----------------------------- : cortex-a53 smp<br />
`-- sun50iw1<br />
`-- sun50iw1p1 ----- a64</pre><br />
<br />
This new naming scheme is of absolutely no value with respect to the rest of the SoC. The actual ARM core(s) used are usually the least important piece of information for SoC support. This table completely ignores the fact that A20 is an updated A10 and is pin compatible. It also ignores the fact that A31 introduced a lot of changes which were carried on to the A23/A33 and possibly A80 parts. It therefore is quite likely that this naming scheme was purely a marketing decision, and that Allwinner marketing will change its mind again.<br />
<br />
= Features =<br />
* CPU: ARMv7-A [http://en.wikipedia.org/wiki/ARM_Cortex-A7 Cortex-A7], [http://en.wikipedia.org/wiki/ARM_Cortex-A15 Cortex-A15] or [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8] Central Processor Unit with (co-)processor extensions:<br />
** Advanced SIMD: [http://en.wikipedia.org/wiki/ARM_architecture#Advanced_SIMD_.28NEON.29 NEON] (ARM's extended general-purpose advanced SIMD vector processing extension engine)<br />
** [[Vector Floating Point Unit]] ([http://en.wikipedia.org/wiki/ARM_architecture#Floating-point_.28VFP.29 VFPU]): ARM VFPv3 lite (Cortex-A8) / VFPv4 (Cortex-A7)<br />
** Security Extensions: <br />
*** [http://en.wikipedia.org/wiki/ARM_architecture#Security_extensions_.28TrustZone.29 TrustZone] secure world<br />
*** [[Security_System|Security accelerator]] supporting AES, DES, 3DES, SHA-1, MD5 and pseudo-random number generation<br />
** [http://en.wikipedia.org/wiki/ARM_architecture#Thumb-2 Thumb-2] instruction set extension for optimized code to reduce memory footprint and improve performance<br />
* GPU: [[Mali400]], Mali400-MP2, SGX544 or PowerVR G6230 Graphics Procesor Unit, supporting OpenGL ES2.<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
* HDMI-transmitter with [http://en.wikipedia.org/wiki/HDMI#CEC HDMI CEC] (Consumer Electronics Control), with exception of A13 which lacks HDMI-transmitter and SATA-controller<ref>[http://olimex.wordpress.com/2012/04/24/cortex-a8-in-tqfp-sure-allwinner-a13/ "Cortex A8 in TQFP? sure Allwinner A13"] ''Retrieved 23 September 2012''</ref><br />
* Hardware virtualization capabilities (Cortex-A7 only).<br />
* Up to 4GB memory (Cortex-A8), Up to 1TB memory with LPAE (Cortex-A7 only).<br />
<br />
== Comparison table ==<br />
{| class="wikitable"<br />
! scope="row" | !! [[A10]] !! [[A10s]] !! [[A13]] !! [[A20]] !! [[A23]] !! [[A31]] !! [[A31s]] !! [[A33]] !! [[A80]]<br />
|-<br />
! scope="row" | Generation <br />
| sun4i || sun5i || sun5i || sun7i || sun8i || sun6i || sun6i || sun8i || sun9i <br />
|-<br />
! scope="row" | CPU<br />
| Cortex-A8 || Cortex-A8 || Cortex-A8 || Cortex-A7 || Cortex-A7 ||Cortex-A7 || Cortex-A7 || Cortex-A7 || Cortex-A7 / A15 <br />
|-<br />
! scope="row" | CPU Maximum frequency<br />
| 1 GHz|| 1 GHz || 1 GHz|| 960 MHz|| 1.5 GHz || ? GHz || ? GHz || 1.5 GHz || 2 (??) GHz<br />
|-<br />
! scope="row" | Cores<br />
| 1 || 1 || 1 || 2 || 2 || 4 || 4 || 4 || 2 x 4<br />
|-<br />
! scope="row" | Extensions<br />
| NEON, VFPv3, Thumb-2 || NEON, VFPv3, Thumb-2 || NEON, VFPv3, Thumb-2 || NEON, VFPv3 / VFPv4, Thumb-2 ||NEON, VFPv3 / VFPv4, Thumb-2 || NEON, VFPv3 / VFPv4, Thumb-2 || NEON, VFPv3 / VFPv4, Thumb-2 || NEON, VFPv3 / VFPv4, Thumb-2 || ? (A80)<br />
|-<br />
! scope="row" | Memory<br />
| DDR2, DDR3</br> (max 2GB @ DDR800) || DDR2, DDR3</br> (max 2GB @ DDR800) || DDR2, DDR3</br> (max 512MB @ DDR800) || LPDDR3, DDR3,</br>LPDDR2 || DDR3</br>(max 1GB) || 2-channel DDR3, LPDDR2, </br>2-channel DDR3L, DDR3U || DDR3, DDR3L, LPDDR2 || ? (A33) || 2-channel DDR3, DDR3L, LPDDR3, LPDDR2</br> up to 8GB<br />
|-<br />
! scope="row" | GPU<br />
| [[Mali400]]</br>320&nbsp;MHz || [[Mali400]]</br>320&nbsp;MHz || [[Mali400]]</br>320&nbsp;MHz || [[Mali400]]-MP2</br>350&nbsp;MHz || [[Mali400]]-MP2 || SGX544</br>200&nbsp;MHz || SGX544</br>200&nbsp;MHz || [[Mali400]]-MP2 || 64-core PowerVR G6230<br />
|-<br />
! scope="row" | GPU API<br />
| OpenGL ES 2.0, OpenVG 1.1 || OpenGL ES 2.0, OpenVG 1.1 || OpenGL ES 2.0, OpenVG 1.1 || OpenGL ES 2.0, OpenVG 1.1 || OpenGL ES 2.0, OpenVG 1.1 || OpenGL ES 2.0, OpenVG 1.1, OpenCL 1.1, and DirectX 9.3 || OpenGL ES 2.0, OpenVG 1.1, OpenCL 1.1, and DirectX 9.3 || OpenGL ES 2.0, OpenVG 1.1 || OpenGL 3.x, OpenGL ES Next,3.0,2.0, Open CL 1.x, DirectX 11 level 9_3/10_0<ref>http://www.imgtec.com/news/detail.asp?ID=845</ref><br />
|-<br />
! scope="row" | [[Cedar Engine|Video decoder]]<br />
| 2160p || 1080p || 1080p || 2160p, 4K×2K, 1080p 3D || 1080p@60fps || 2160p, 4K×2K, 1080p 3D || 2160p, 1080p 3D || 1080p@60fps || ? (A80)<br />
|-<br />
! scope="row" | [[Cedar Engine|Video encoder]]<br />
| H.264 1080p@30fps, JPEG || H.264 1080p@30fps, JPEG || H.264 1080p@30fps, JPEG || H.264 1080p@30fps, JPEG || 1080p@60fps || H.264 1080p@60fps, JPEG || H264 1080p@30fps, 720p@60fps || ? (A33) || H.264 HP/VP8 4Kx2K@30fp<br />
|-<br />
! scope="row" | Audio decoder<br />
| AC3, DTS || ? || ? || AC3, DTS || - || ? (A31) || ? (A31S) || ? (A33) || ? (A80)<br />
|-<br />
! scope="row" | Video interfaces<br />
| HDMI 1.3, YPbPr, VGA, CPU/RGB/LVDS LCD || HDMI 1.3, RGB/LVDS LCD || RGB LCD, VGA|| HDMI 1.4, CVBS, YPbPr, VGA, CPU/RGB/LVDS LCD || CPU/RGB/LVDS LCD, MIPI DSI || HDMI 1.4, MIPI DSI, 2-channel LVDS, 2-channel RGB LCD || HDMI 1.4, LVDS, RGB LCD || ? (A33) || HDMI 4K, RGB LCD 2048x1536@60fps, dual-channel LVDS 1920x1080@60fps, 4-lane MIPI DSI 1920x1200@60fps, 4-lane eDP 2560x1600@60fps<br />
|-<br />
! scope="row" | Audio interfaces<br />
| I2S, SPDIF, AC97 || I2S, AC97 || I2S, AC97 || I2S, PCM, AC97 || I2S, PCM || 2 I2S, 2 PCM || I2S, 2 PCM || ? (A33) || ? (A80)<br />
|-<br />
! scope="row" | USB OTG<br />
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || ? (A33) || 1<br />
|-<br />
! scope="row" | USB Host<br />
| 2 || 1 || 1 || 2 || 1 || 2 || 2 || ? (A33) || 2x USB Host, USB 3.0/2.0 Dual-Role (host/device)<br />
|-<br />
! scope="row" | Ethernet<br />
| EMAC || EMAC || - || EMAC/GMAC || - || GMAC || GMAC || - || GMAC<br />
|-<br />
! scope="row" | Storage<br />
| NAND (max 64GB), SATA II, SD Card 3.0 || NAND (max 64GB), SD Card 3.0 || NAND (max 64GB), SD Card 3.0 || NAND, MMC, [http://olimex.wordpress.com/2013/04/05/allwinners-a10-and-a20-are-they-really-pin-to-pin-compatible-and-drop-in-replacement/#comment-5452 SATA] || raw NAND, eMMC, SD card || 4 x SD Card, eMMC NAND, 2-channel raw NAND || 4 x SD Card, eMMC NAND, raw NAND || 3 x SD Card, eMMC NAND, raw NAND || 4 x SD/MMC<br />
|-<br />
! scope="row" | Package<br />
| BGA441</br>19&nbsp;mm&nbsp;×&nbsp;19&nbsp;mm</br>0.80&nbsp;mm Pitch || BGA336</br>14&nbsp;mm&nbsp;×&nbsp;14&nbsp;mm</br>0.65&nbsp;mm Pitch || eLQFP176</br>20&nbsp;mm&nbsp;×&nbsp;20&nbsp;mm ||BGA441</br>19&nbsp;mm&nbsp;×&nbsp;19&nbsp;mm</br>0.80&nbsp;mm Pitch || FBGA280</br>14&nbsp;mm&nbsp;x&nbsp;14&nbsp;mm&nbsp;x&nbsp;1.4&nbsp;mm</br>0.80&nbsp;mm Pitch || BGA609</br>18&nbsp;mm&nbsp;×&nbsp;8&nbsp;mm</br>0.65&nbsp;mm Pitch || ? (A31S) || ? (Allwinner: pin compatible with A23) || ? (A80)<br />
|-<br />
! scope="row" | Lithography<br />
| 55 nm || 55 nm|| 55 nm || 40 nm || 40 nm || 40 nm || 40 nm || 40 nm || 28 nm<br />
|}<br />
<ref>http://blog.thinkteletronics.com/all-mobile-socsolutions/ All Mobile Soc/Solutions.</ref><br />
<br />
= References =<br />
<references /><br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A23&diff=17526
A23
2016-06-06T19:35:31Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| manufacturer = Allwinner<br />
| process = 40nm<br />
| cpu = Dual-Core ARM Cortex-A7 @ 1.5GHz<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR3/DDR3<br />
| gpu = [[Mali400]] MP2 @ 600MHz<br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = CPU/RGB LCD, LVDS, MIPI DSI<br />
| audio = I2S, PCM, AC97<br />
| network = <br />
| storage = MMC, NAND<br />
| usb = OTG, 2x Host<br />
| other = <br />
| release_date = November 2013<br />
| website = [http://www.allwinnertech.com/en/product/A23.html Product Page]<br />
}}<br />
<br />
Allwinner [[A23]] (sun8i) SoC features a Dual-Core Cortex-A7 ARM CPU, and a [[Mali400]] MP2 GPU from ARM. It is a lower power cut-down version of the [[A20]].<br />
<br />
=Overview=<br />
<br />
The A23 is not supported in the linux-sunxi 3.4 kernel and in u-boot-sunxi, but there is basic support in the [[Linux mainlining effort|mainline Linux kernel]] (since kernel 3.17/3.18) and in [[Mainline_U-Boot#v2015.04|mainline u-boot]] (since v2015.04). <br />
<br />
=A23 SoC Features=<br />
[[File:Allwinner_A23.jpg|thumb|A23 SoC on a IPPO Q8H]]<br />
* CPU<br />
** ARM Cortex-A7 Dual-Core<br />
** 256KiB L2-Cache (shared between two cores)<br />
** 32KiB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
** Large Physical Address Extensions (LPAE) 1TB<br />
* GPU<br />
** ARM Mali400 MP2<br />
** Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).<br />
** Complies with OpenGL ES 2.0<br />
* Memory<br />
** DDR3/DDR3L controller<br />
** NAND Flash controller and 64-bit ECC<br />
* Video<br />
** HD H.264 2160P video decoding<br />
** Full HD video decoding<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@30fps encoding<br />
** 3840×1080@30fps 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** CPU/RGB/LVDS LCD interface 1920×1080 resolution<br />
** MIPI DSI interface up to 1280x800 resolution<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV sensor<br />
** Integrated 24-bit parallel YUV 444 I/F<br />
** 5M/8M CMOS sensor support<br />
** Dual-sensor support<br />
* Audio<br />
** Integrated HI-FI 100dB Audio Codec<br />
** Dual MIC noise cancellation<br />
* PMIC<br />
** X-Powers AXP223, designed for the A23, connected via Allwinner's [[Reduced Serial Bus | Reduced Serial Bus (RSB) ]]<br />
<br />
= Documentation =<br />
<br />
* [http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf A23 User Manual v1.0] <small>(PDF, 696 pages, 2013-08-30)</small><br />
* [http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf A23 Datasheet v1.0] <small>(PDF, 35 pages, 2013-08-30)</small><br />
Some other documents were found online:<br />
<br />
* [http://wenku.baidu.com/view/21cbdf68a5e9856a57126046.html?re=view A23 SDRAM support list]<br />
* [http://wenku.baidu.com/view/d9aabf6b58fb770bf68a5536.html?re=view A23 NAND support list]<br />
* [http://wenku.baidu.com/view/797b0d1ff01dc281e53af0f4.html?re=view A23 PCB design notes (Chinese)]<br />
* [http://wenku.baidu.com/view/dedb8bbd4693daef5ef73dba.html?re=view A23 Tablet reference design schematics]<br />
<br />
= Software =<br />
<br />
== Original SDK ==<br />
<br />
* [http://dl.linux-sunxi.org/SDK/A23-v1.0/ SDK (4GB tarball)]<br />
* [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/ SDK (unpacked)]<br />
<br />
The SDK contains customized sources for U-boot, Linux, Android and buildroot.<br />
It also has a gnueabi cross compile toolchain.<br />
<br />
=== SDK Content ===<br />
* Linux Kernel: A23/lichee/linux-3.4<br />
* Buildroot: A23/lichee/buildroot<br />
* U-boot: A23/lichee/brandy/u-boot-2011.09<br />
* ARM gnueabi cross compile toolchain: A23/lichee/brandy/gcc-linaro/<br />
* Android: A23/android<br />
* Various Allwinner tools: A23/lichee/tools<br />
<br />
Use the "pack" script under "A23/lichee/tools/pack" to build an image. (not tested)<br />
<br />
== Boot0 ==<br />
[[BROM|Boot0]] initializes the DRAM, basic clocks and loads U-boot from NAND or MMC.<br />
There is no boot1 on A23. Boot0 directly loads U-boot.<br />
<br />
Allwinner has in the meantime published the source code for boot0 in their github repository.<br />
<br />
Binaries of boot0 can be found in the SDK: [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/tools/pack/chips/sun8iw3p1/bin/ A23/lichee/tools/pack/chips/sun8iw3p1/bin]<br />
<br />
fes1_sun8iw3p1.bin is for FEL mode.<br />
<br />
== U-boot ==<br />
There are 3 U-boot sources available.<br />
<br />
=== Allwinner ===<br />
Allwinner's SDK contains a customized U-boot, based on v2011.09. This works with either NAND or MMC.<br />
It contains drivers for LCD display, MMC, NAND, normal UARTs, USB OTG, RSB, PMIC, and the ability to update various images.<br />
<br />
=== Sunxi Community ===<br />
[[U-boot|u-boot-sunxi]] has basic support for A23, which includes UART console (including R_UART) and MMC.<br />
Disclaimer: no one has actually booted a kernel with this yet.<br />
<br />
Work still needed: <br />
* SPL (DRAM initialization code) <br />
* [[Reduced_Serial_Bus]] driver (to talk to AXP PMIC).<br />
<br />
=== Mainline U-Boot ===<br />
<br />
[[Mainline_U-Boot#v2015.04|mainline u-boot]] has support for the A23 (incl. SPL and AXP223 PMIC support) since v2015.04. <br />
<br />
== Kernel code ==<br />
<br />
=== Allwinner ===<br />
There is a kernel tree currently available which contains a quick backport of the A23-v1.0 SDK, [https://github.com/libv/linux-sunxi/tree/a23sdk_frankenkernel it is called "a23sdk_frankenkernel".]<br />
<br />
This tree contains:<br />
* The Android 3.4.39 kernel<br />
* loads of nasty backports on top:<br />
** direct commits from upstream or android trees<br />
** commits from upstream or android trees with changes to certain files removed<br />
* the remaining diff to the A23-v1.0 SDK packed on top:<br />
** with fixed encodings (to UTF-8), where possible, as some allwinner side encoding mess-up has destroyed data<br />
** fixed file permissions<br />
** remaining changes which could not easily be tracked back to upstream or android tree commits<br />
<br />
TODO:<br />
* remove useless/dead files:<br />
** vexpress and realview ael.<br />
** changes to other architectures.<br />
** pointless scripts<br />
** other obviously useless files.<br />
* Separate out some drivers to their original versions so allwinner specific changes become visible:<br />
** the 3 mali kernel driver versions <br />
** the many added wireless drivers<br />
* build and run testing.<br />
<br />
=== Sunxi Community ===<br />
Patches for basic A23 support on mainline have been posted on the mailing list.<br />
You can also find them [https://github.com/wens/linux/tree/sunxi-a23 here].<br />
<br />
== GPL violations ==<br />
<br />
The [http://dl.linux-sunxi.org/SDK/A23-v1.0/ v1.0 SDK] contains many binaries and is therefor violating the GPLv2 quite directly:<br />
<br />
* Kernel:<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/kernel/drivers/devfreq/dramfreq/mdfs/mdfs.code kernel/drivers/devfreq/dramfreq/mdfs/mdfs.code]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/kernel/drivers/arisc/binary/arisc_sun8iw1p1.code kernel/drivers/arisc/binary/arisc_sun8iw1p1.code]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/kernel/drivers/arisc/binary/arisc_sun9iw1p1.code kernel/drivers/arisc/binary/arisc_sun9iw1p1.code]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/drivers/media/video/sunxi-vfe/lib/libisp <tt>drivers/media/video/sunxi-vfe/lib/libisp</tt>]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/modules/nand/sun8iw1p1/libnand_sun8iw1p1 <tt>modules/nand/sun8iw1p1/libnand_sun8iw1p1</tt>]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/modules/nand/sun8iw3p1/libnand_sun8iw3p1 <tt>modules/nand/sun8iw3p1/libnand_sun8iw3p1</tt>]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/modules/nand/sun9iw1p1/libnand_sun9iw1p1 <tt>modules/nand/sun9iw1p1/libnand_sun9iw1p1</tt>]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/drivers/input/touchscreen/aw5x06/libAW5306 <tt>drivers/input/touchscreen/aw5x06/libAW5306</tt>]<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/linux-3.4/drivers/input/touchscreen/gslx680new/gsl_point_id_20130415 <tt>drivers/input/touchscreen/gslx680new/gsl_point_id_20130415</tt>]<br />
* U-boot:<br />
** [http://dl.linux-sunxi.org/SDK/A23-v1.0/unpacked/A23/lichee/brandy/u-boot-2011.09/nand_sunxi/sun8iw3/libnand-sun8iw3 <tt>nand_sunxi/sun8iw3/libnand-sun8iw3</tt>]<br />
<br />
We are still waiting on action from Allwinner to resolve this.<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A23 Devices</categorytree><br />
= See also =<br />
* [[A20]]<br />
<br />
=References=<br />
<references /><br />
<br />
= External links =<br />
* [http://www.allwinnertech.com/en/clq/processora/A23.html Product Page]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=Sending_patches&diff=17525
Sending patches
2016-06-06T19:34:51Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>We currently use the [[Mailing list]] as a code review and integration tool, feel free to send your patches using ''git send-email''.<br />
<br />
== Patches for New Devices ==<br />
<br />
Patches going upstream (mainline) are managed on other mailing lists and by their particular maintainers.<br />
You need not subscribe to these list for sending patches. To ensure your patches integrate well, use<br />
the following repositories. Find information how to actually make the modifications in the section linked<br />
in the ''Topic'' column.<br />
<br />
{| class="wikitable"<br />
|- <br />
! Topic || Repository to patch against || Patch receiver(s) || Example<br />
|-<br />
| [[New Device howto#Step 6: Add support to sunxi-boards|Fex]]|| https://github.com/linux-sunxi/sunxi-boards || To:linux-sunxi@googlegroups.com ||[https://groups.google.com/forum/#!searchin/linux-sunxi/fex/linux-sunxi/WzSXGbtv_KY/OyfzdMdfv64J]<br />
|-<br />
| [[U-boot#Adding_a_new_device_to_U-Boot|u-boot-sunxi]] ({{Remove|Deprecated!}}) || https://github.com/linux-sunxi/u-boot-sunxi.git || To:linux-sunxi@googlegroups.com ||[https://groups.google.com/forum/#!searchin/linux-sunxi/u-boot$20patch/linux-sunxi/QH_pNnofdhA/IvONhc3kMmYJ]<br />
|-<br />
| [[Mainline_U-boot#Adding a new device to upstream U-Boot|mainline u-boot]] || http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=tree;hb=refs/heads/next ||To:u-boot@lists.denx.de<br>Cc:linux-sunxi@googlegroups.com ||[http://lists.denx.de/pipermail/u-boot/2015-January/201954.html], [http://lists.denx.de/pipermail/u-boot/2015-January/201959.html]<br />
|-<br />
| linux-sunxi || https://github.com/linux-sunxi/linux-sunxi.git || To:linux-sunxi@googlegroups.com ||[https://groups.google.com/forum/#!searchin/linux-sunxi/patch/linux-sunxi/bf2od9vmUUU/RbYsI5TSFgkJ]<br />
|-<br />
| [[Mainline_Kernel_Howto#Adding_a_new_device|mainline kernel (.dts)]] || https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/tree/?h=sunxi/for-next || Use the get_maintainer script as shown below<br>Cc:linux-sunxi@googlegroups.com ||[https://groups.google.com/forum/#!topic/linux-sunxi/Xu0qNroC7HQ]<br />
|}<br />
<br />
== Patches for Tools and Drivers ==<br />
<br />
The main repositories to clone and base from are all maintained at [https://github.com/linux-sunxi/ GitHub ( https://github.com/linux-sunxi/ )] - these include linux kernel sources, u-boot sources, tools and other associated libraries such as MALI 3D graphics and CEDAR Video engine.<br />
<br />
== Setting up git send-email ==<br />
<br />
# Install git-email addon using your favorite package manager<br />
# <code>$ git config --global sendemail.smtpserver ''smtp.yourisp.com''</code><br />
# <code>$ git config --global sendemail.smtpuser ''yourusernameforsmtp''</code><br />
# <code>$ git config --global sendemail.smtppass ''yourpassword''</code><br />
# <code>$ git config --global sendemail.from ''your@email.com''</code><br />
# <code>$ git config --global sendemail.chainreplyto false</code><br />
<br />
== Using git send-email ==<br />
<br />
# <code>$ git format-patch -1 ''longcommithashhere''</code><br />
# <code>$ git send-email ''0001-whatever-file-it-generated.patch''</code><br />
<br />
If you're sending patches to the mainline kernel, you can get a list of the recipients of the patch using:<br />
# <code>$ ./scripts/get_maintainer.pl ''0001-whatever-file-it-generated.patch''</code><br />
<br />
It will ask you whom to send it to (use ''dev@linux-sunxi.org'') and that's it!<br />
<br />
== More information ==<br />
* [http://garbas.si/blog/2011/send-patches-using-git-send-email Send patches using git send-email]<br />
* [https://felipec.wordpress.com/2009/10/25/git-send-email-tricks/ git send-email tricks]<br />
* [http://lxr.free-electrons.com/source/Documentation/SubmittingPatches Linux Documentation: Submitting patches]<br />
* [https://www.youtube.com/watch?v=LLBrBBImJt4 Youtube: Write and Submit your first Linux kernel Patch By Greg Kroah-Hartman]<br />
<br />
[[Category:Community]]<br />
[[Category:Development]]</div>
Nove
https://linux-sunxi.org/index.php?title=E200&diff=17524
E200
2016-06-06T19:33:23Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div><br />
{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = ?<br />
| cpu = ARM926-EJS<br />
| ltwo = 256KB<br />
| extensions = NEON, VFPv3<br />
| memory = 16-bit SDR/DDR<br />
| gpu = <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = CVBS,RGB<br />
| audio = <br />
| network = <br />
| storage = NAND,SD-Card(16 Gb Max)<br />
| usb = 2.0 OTG<br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/product/F1E200.html Product Page]<br />
}}<br />
<br />
Specs from [http://www.allwinnertech.com/product/F1E200.html product page]:<br />
<br />
'''CPU''' ARM926-EJS 16KB I-Cache 16KB D-Cache<br />
<br />
'''Video''' Decoding up to 1080P including H.264, H.263, MPEG-1, 2, 4, XVID<br />
<br />
'''Display''' CVBS output, CPU/RGB LCD Interface<br />
<br />
'''RAM''' 16-bit SDR/DDR<br />
<br />
'''Flash''' SLC/MLC NAND, 2 Flash chips, 64-bit ECC, up to 16GB (total?), R/W Max 15MB/s<br />
<br />
<br />
'''Connectivity''' USB 2.0 OTG, 2 MMC/SD Card Controller, 2 SPI, 2 TWI, 3 UART<br />
<br />
'''Boot Devices''' NAND Flash, SPI NOR FLASH, SD Card, USB<br />
<br />
OS Melis 2.0 <br />
<br />
'''device example''' [http://www.hermann-uwe.de/blog/the-trekstor-ebook-reader-3-0-ebr30-a-review-and-dissection Trekstor EBR30-a (TFT)] [[Prestigio_PER3464B]] [http://www.prestigio.com/catalogue/MultiReaders/MultiReader_3884 Prestigio 3884 TFT touch screen reader]<br />
<br />
[http://randomprojects.org/wiki/TrekStor_eBook_Reader_3.0_EBR30-a_%28Weltbild_%2B_Hugendubel_Edition%29#Pinout CPU pinout (WIP)]<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>E200 Devices</categorytree><br />
<br />
[[Category:System_on_Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A20&diff=17523
A20
2016-06-06T19:32:46Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = [[File:Allwinner_A20.png|250px]]<br />
| manufacturer = Allwinner<br />
| process = 40nm<br />
| cpu = Dual-Core ARM Cortex-A7<br />
| ltwo = <br />
| extensions = <br />
| memory = LPDDR3/DDR3/LPDDR2<br />
| gpu = [[Mali400]] MP2<br />
| vpu = <br />
| apu = <br />
| video = HDMI 1.4, CVBS, YPbPr, VGA, CPU/RGB/LVDS LCD<br />
| audio = I2S, PCM, AC97<br />
| network = <br />
| storage = MMC, NAND, SATA<br />
| usb = OTG, 2x Host<br />
| other = <br />
| release_date = December 2012<br />
| website = [http://www.allwinnertech.com/en/clq/processora/A20.html Product Page]<br />
}}<br />
<br />
Allwinner [[A20]] (sun7i) SoC features a Dual-Core Cortex-A7 ARM CPU, and a [[Mali400]] MP2 GPU from ARM.<br />
<br />
Allwinner A20 is a low-end (budget) version of the [[A31]]. It shares its Cortex-A7 ARM CPU architecture, but at the same time it is also pin-to-pin compatible with [[A10]].<br />
<br />
A20 is fully supported by the community from linux-sunxi 3.4 kernel and later.<br />
<br />
=Overview=<br />
A20 CPU consists of dual ARM Cortex-A7 cores, and integrates the Mali400 MP2 GPU. Together with [[Cedar Engine]] multimedia processing unit that is capable of up to 2160p (3840x1080@30fps 4k resolution or 1080p 3D decoding) video decoding, with integrated HDMI 1.4 output support, and H.264 HP (High Profile) in 1080p at 30fps video encoding.<br />
<br />
==Main components of the A20 ==<br />
* CPU: Dual-Core ARM [http://en.wikipedia.org/wiki/ARM_Cortex-A7 Cortex-A7 1GHz Processor (r0p4, revidr=0x0)] which have both VFP4 and NEON SIMD co-processors that share 32 floating point double-precision registers together<ref>[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/BABDAHCE.html Cortex-A7 MPCore Technical Reference Manual — 1.3. Features]</ref>: <br />
** FPU: standard ARM VFPv4-D32 FPU Floating Point Unit<br />
** SIMD: NEON (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400|Mali400 MP2]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
* HDMI-transmitter: HDMI CEC (Consumer Electronics Control)<br />
<br />
==Cortex-A7==<br />
Cortex-A7 is 100% ISA compatible with the Cortex-A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration.<ref>http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices</ref><ref>http://en.wikipedia.org/wiki/ARM_Cortex-A7_MPCore</ref><ref>http://www.arm.com/products/processors/cortex-a/cortex-a7.php</ref><br />
<br />
=== Virtualization ===<br />
Cortex A7 and A15 includes hardware virtualization support.<br />
<br />
* It is managed by Xen ([http://www-archive.xenproject.org/files/xensummit_seoul11/nov2/2_XSAsia11_JGoodacre_HW_accelerated_virtualization_in_the_ARM_Cortex_processors.pdf Presentation of Cortex A7 and A15 capabilities for virtualisation], [http://www-archive.xenproject.org/products/xen_arm.html Xen ARM] on xenproject.org, [http://blog.xen.org/index.php/2012/09/21/xensummit-sessions-new-pvh-virtualisation-mode-for-arm-cortex-a15arm-servers-and-x86/ PVH mode] on blog.xen.org, [http://wiki.xen.org/wiki/Xen_ARMv7_with_Virtualization_Extensions Xen ARMv7 with Virtualization Extensions] on xenproject.org wiki)<br />
<br />
* [http://wiki.xen.org/wiki/Xen_ARM_with_Virtualization_Extensions/Allwinner there is a guide about running xen on a20]<br />
<br />
* [http://www.virtualopensystems.com/ Some guides to deploy virtualization on Cotex-A15 and source for virtualization with KVM on Cortex-A15 on github]<br />
<br />
* [http://www.ok-labs.com/releases/release/open-kernel-labs-delivers-okl4-mobile-virtualization-for-arm-Cortex-A7 Open Kernel Labs Delivers OKL4 Mobile Virtualization for ARM Cortex-A7 Processors]<br />
<br />
On the kvm branch of kernel.org, there is description of Cortex-A15 Virtualization extensions VGIC registers :<br />
<br />
* [https://git.kernel.org/cgit/virt/kvm/kvm.git/tree/Documentation/devicetree/bindings/arm/gic.txt GIC of ARM on kvm branch of the kernel]<br />
<br />
After the ARM Cortex-A7 documentation:<br />
<br />
* GIC memory MAP on Cortex-A7<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.1. GIC memory-map</ref>:<br />
0x4000-0x4FFF Virtual interface control, common base address<br />
0x5000-0x5FFF Virtual interface control, processor-specific base address<br />
0x6000-0x7FFF Virtual CPU interface<br />
* Virtual Maintenance Interrupt (PPI6)<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.2. Interrupt sources</ref> <br />
* 2 virtual interrupt signals, nVIRQ and nVFIQ<ref>Cortex-A7 MPCore Technical Reference Manual - 8.2.4. GIC configuration</ref><br />
* With MMU-400, Intermediate Physical Address (IPA) ca be used by guest OS<ref>CoreLink MMU-400 System Memory Management Unit Technical Reference Manual - 1.1. About the MMU-400</ref><br />
<br />
==A20 SoC Features==<br />
[[File:Allwinner A20.jpg|thumb|A20 SoC on a [[Cubieboard2]]]]<br />
* CPU<br />
** ARM Cortex-A7 Dual-Core ([http://infocenter.arm.com/help/topic/com.arm.doc.epm016887/index.html revision r0p4])<br />
** 256KiB L2-Cache (shared between two cores)<br />
** 32KiB (Instruction) / 32KiB (Data) L1-Cache per core<br />
** SIMD NEON, VFP4<br />
** Virtualization<br />
** Large Physical Address Extensions (LPAE) 1TB<br />
* GPU<br />
** ARM Mali400 MP2<br />
** Featuring 1 vertex shader (GP) and 2 fragment shaders (PP).<br />
** Complies with OpenGL ES 2.0<br />
* Memory<br />
** LPDDR2/DDR3/DDR3L controller<br />
** NAND Flash controller and 64-bit ECC<br />
* Video<br />
** HD H.264 2160P video decoding<br />
** Full HD video decoding<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@30fps encoding<br />
** 3840×1080@30fps 3D decoding<br />
** Complies with RTSP, HTTP,HLS,RTMP,MMS streaming media protocol<br />
* Display<br />
** Support multi-channel HD display<br />
** Integrated HDMI 1.4<br />
** CPU/RGB/LVDS LCD interface 1920×1080 resolution<br />
** CVBS/YPbPr/VGA support<br />
** Integrated TV decoder<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV sensor<br />
** Integrated 24-bit parallel YUV 444 I/F<br />
** 5M/8M CMOS sensor support<br />
** Dual-sensor support<br />
* Audio<br />
** Integrated HI-FI 100dB Audio Codec<br />
** Dual MIC noise cancellation<br />
* package: BGA441 19 mm × 19 mm (0.80 mm Pitch)<br />
<br />
= Documentation =<br />
<br />
Latest documentation is available on [https://github.com/allwinner-zh/documents/tree/master/A20 AllWinners documentation repository on Github]<br />
<br />
* [http://dl.linux-sunxi.org/A20/A20%20Brief%202013-04-07.pdf A20 Product Brief] (Outdated)<br />
* [http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf A20 User Manual] (Outdated v1.0)<br />
<br />
= Software =<br />
== Original SDKs ==<br />
We have made some SDKs available on our server:<br />
* A20-SDK-2.0 ([http://dl.linux-sunxi.org/SDK/A20-SDK-2.0/aw.tar.bz2 Full])<br />
* A20_SDK_20130319 ([http://dl.linux-sunxi.org/SDK/A20/A20_SDK_20130319.tar.gz Reduced], [http://dl.linux-sunxi.org/SDK/A20/A20_SDK_20130319/ Unpacked])<br />
<br />
== GPL Violations ==<br />
<br />
See [[GPL_Violations#CedarX|CedarX violations.]]<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A20 Devices</categorytree><br />
= See also =<br />
* [[Mali400]]<br />
* [[A10]]<br />
* [[A10s]]<br />
* [[A13]]<br />
* [[A31]]<br />
<br />
=References=<br />
<references /><br />
<br />
= External links =<br />
* [http://allwinnertech.com/en/clq/processora/A20.html Product Page]<br />
* [https://github.com/amery/linux-allwinner/tree/import/lichee-3.3/a20-dev kernel source code for Allwinner A20]<br />
* [https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A20-PDFs/A20_PAD_STD_V1_1.rar?raw=true Allwinner A20 EVB Schematics]<br />
* [https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A20-PDFs/A20%20brief%2020130306.pdf?raw=true Allwinner A20 product brief]<br />
* [http://en.wikipedia.org/wiki/Allwinner_A20 Allwinner A20 article on wikipedia.org]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=R8&diff=17522
R8
2016-06-06T19:31:07Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = <br />
| cpu = ARM Cortex-A8 @ 1Ghz<br />
| ltwo = <br />
| extensions = NEON, VFPv3<br />
| memory = DDR2, DDR3 (max 512MB)<br />
| gpu = [[Mali400|Mali 400]] <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = LCD<br />
| audio = Mic, Headphone<br />
| network = -<br />
| storage = NAND (max 2 * 32GB), SD Card 3.0, SPI NOR Flash, USB Storage<br />
| usb = 2 (1 HOST, 1 OTG)<br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/clq/r/R8.html Product Page]<br />
}}<br />
<br />
[[Allwinner]] '''R8''' is SoC designed based on [[A13]] featuring one core Cortex-A8 ARM CPU with [[Cedar Engine]] VPU and [[Mali 400]] GPU.<br />
<br />
=Overview=<br />
==Main components of the R8:==<br />
* CPU: [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8 1GHz (ARM v7) Processor] which have both [[Vector Floating Point Unit|VFPv3]] and [[NEON]] co-processors: <br />
** FPU: [[Vector Floating Point Unit]] (standard ARM VFPv3 FPU Floating Point Unit)<br />
** SIMD: [[NEON]] (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
<br />
The R8 is a modified version of the A13, targeted to IoT devices.<br />
== R8 SoC Features ==<br />
* CPU<br />
** ARM Cortex-A7 single core<br />
** 256KB L2-Cache<br />
** 32KiB (Instruction) / 32KiB (Data)<br />
** SIMD NEON, VFP3<br />
* GPU<br />
** ARM Mali400<br />
** Complies with OpenGL ES 2.0<br />
* Memory<br />
** DDR2/DDR3 controller (upto 512 MB)<br />
** NAND Flash controller and 64-bit ECC<br />
* Video<br />
** HD H.264 video decoding<br />
** Full HD video decoding<br />
** H.264 Medium Profile 720P@30fps encoding<br />
** 1080p@30fps decoding<br />
* Display<br />
** CPU/RGB LCD interface<br />
* Camera<br />
** Integrated parallel 8-bit I/F YUV sensor<br />
* Peripherals<br />
** USB 2.0 OTG & USB 2.0 Host<br />
** 4x UARTs(all with IrDA)<br />
** 3x SPI controllers(master/slave mode)<br />
** 3x i2c controllers (called two wire interfaces TWI) standard mode (100Kbps) & fast-mode (up to 400K bps)<br />
** Internal 4-wire touch panel controller with pressure sensor and 2-point touch<br />
** Internal 24-bit Audio Codec for 2-Ch headphone and 1-Ch microphone<br />
** PWM controller<br />
* package: eLQFP 176-pin 22 mm × 22 mm<br />
<br />
= Documentation =<br />
<br />
* [https://github.com/NextThingCo/CHIP-Hardware/raw/master/CHIP%5Bv1_0%5D/CHIPv1_0-BOM-Datasheets/Allwinner%20R8%20Datasheet%20V1.2.pdf Allwinner R8 Datasheet v1.2]<br />
* [https://github.com/NextThingCo/CHIP-Hardware/raw/master/CHIP%5Bv1_0%5D/CHIPv1_0-BOM-Datasheets/Allwinner%20R8%20User%20Manual%20V1.1.pdf Allwinner R8 Manual v1.1]<br />
* A13 documentation is available on [https://github.com/allwinner-zh/documents/tree/master/A13 A13 AllWinners documentation repository on Github] (for comparison)<br />
<br />
= Devices =<br />
* [[NextThingCo_CHIP]]<br />
<br />
= See Also =<br />
* [[A13]]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A31&diff=17521
A31
2016-06-06T19:27:26Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = [[File:Allwinner_A31s.jpg|250px]]<br />
| manufacturer = Allwinner<br />
| process = 40nm<br />
| cpu = Quad-Core ARM Cortex-A7<br />
| ltwo = <br />
| extensions = <br />
| memory = 2-channel DDR3/LPDDR2, 2-channel DDR3L, maximum of 4GB total (2GB per channel) <br />
| gpu = SGX544<br />
| vpu = <br />
| apu = <br />
| video = HDMI 1.4, MIPI DSI, 2-channel LVDS, 2-channel RGB LCD<br />
| audio = I2S, PCM<br />
| network = <br />
| storage = 4x SD Card, eMMC NAND, 2-channel raw NAND<br />
| usb = OTG, 2x Host<br />
| other = <br />
| release_date = December 2012<br />
| website = [http://www.allwinnertech.com/en/product/A31.html Product Page]<br />
}}<br />
<br />
Allwinner A31 (sun6i) SoC features a Quad-Core Cortex-A7 ARM Processor SoC, and a [[Power VR]] SGX544 (with 8 shader engines) GPU from Imagination Technologies.<ref>http://www.cnx-software.com/2012/12/09/allwinner-a31-and-a20-processors-details/ Allwinner Publishes A31 and A20 Processors Details</ref><br />
<br />
=Overview=<br />
A31 powered by 4 CPU and 8 GPU (Power VR SGX544 for Ployer and Power VR SGX544MP2 for Onda).<br />
[[File:A31-Onda.jpg|thumbnail|A31 Graph]]<br />
<br />
A31 CPU architecture consists of quad ARM Cortex-A7 cores to deliver decent computing capability while consuming less power, and integrates the PowerVR SGX544 GPU. It also features [[Cedar Engine]] multimedia processing unit that is capable of up to 2160p (3840x1080@30fps 4k resolution or 1080p 3D decoding) video decoding, with integrated HDMI 1.4 output support, and H.264 HP (High Profile) in 1080p at 30fps video encoding.<br />
<br />
Proper Linux support now difficult for A31 due to the [[Power VR]] GPU, though; however, its kernel source is available[http://git.rhombus-tech.net/linux] now and also for U-boot[http://git.rhombus-tech.net/?p=u-boot.git;a=tree;h=refs/heads/allwinner-sunxi-a31;hb=refs/heads/allwinner-sunxi-a31].<br />
<br />
==Cortex-A7==<br />
Cortex-A7 is 100% ISA compatible with the Cortex-A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration.<ref>http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices</ref><ref>http://en.wikipedia.org/wiki/ARM_Cortex-A7_MPCore</ref><ref>http://www.arm.com/products/processors/cortex-a/cortex-a7.php</ref><br />
<br />
== A31s ==<br />
<br />
The A31s is the same die as the A31 in a different package. In terms of hardware specification and functionality they are identical.<br />
<br />
=A31 SoC Features=<br />
* CPU:<br />
** ARM Cortex-A7 Quad-Core ([http://infocenter.arm.com/help/topic/com.arm.doc.epm016887/index.html revision r0p3])<br />
** 256KB L1-Cache<br />
** 1MB L2-Cache<br />
* GPU:<br />
** [[Power VR]] SGX 544<br />
** Eight logic cores (8 shader engines)<br />
** Comply with Open GL ES2.0, Open CL1.x, DX 9_3<br />
* Video:<br />
** UHD H.264 4K ×2K @30fps video decoding<br />
** Full HD video decoding<br />
** BD Directory, BD ISO and BD m2ts video decoding<br />
** H.264 High Profile 1080P@60fps encoding<br />
** 3840x1080@30fps 3D decoding<br />
** Comply with RTSP, HTTP, HLS, RTMP, MMS streaming media protocol<br />
* Display:<br />
** Dual-Channel LVDS 1920 ×1080@60fps<br />
** 4-lane MIPI DSI 1920 × 1200@ 60fps<br />
** Dual-Channel RGB/CPU 2048 ×1536@60fps<br />
** Integrated HDMI 1.4 4K ×2K@ 30fps<br />
* Camera:<br />
** Integrated Parallel & MIPI I/F sensor<br />
** Integrated Powerful ISP, supporting Raw Data CMOS sensor<br />
** 5M/8M/12M CMOS Sensor supported<br />
** 8/10/12-bit RGB Bayer sensor supported<br />
* Memory:<br />
** Dual-Channel LPDDR2/DDR3/DDR3L Controller<br />
** Dual-Channel NAND FLASH Controller<br />
** 64-bit ECC<br />
* PMIC:<br />
** A31exclusively tailor-made PMIC [[AXP221]]<br />
** 21-CH power output and 2.2A Flash charging<br />
** Comply with USB 3.0 power supply standard<br />
* Embedded Controller:<br />
** [[AR100]], an OpenRISC controller. Manages deep powersave modes.<br />
* Audio:<br />
** Integrated HI-FI 100dB Audio Codec<br />
** Three MIC<br />
** One MIC with Noise cancellation<br />
* OS: <br />
** Support Android 4.2 or up<br />
** Support Microsoft Windows 8<br />
<br />
=History=<br />
The A31 was initially rumored to be called the A40 instead. On July 9 ''[http://www.cnbeta.com/articles/196089.htm cnbeta.com]'' and ''[http://www.chinaeshops.com/blog/ampe-allwinner-cortex-a7-quad-core-tablet-is-coming.html chinaeshops]'' speculated that the next [[SoC]] from [[Allwinner]] will be a Quad-Core Cortex-A7 ARM Processor SoC, and twice as many GPU cores as it has CPU cores, (it was also unclear early on which GPU it would had, and rumors speculated on Mali 450, Mali T604, or Mali T658 GPU).<br />
<br />
"''This new SoC was thus most likely be either called Allwinner A40 if the pictures from iLife Tech banners taken at Hong Kong Electronics Fair 13-16 October 2012 are correct''".<ref>http://plus.google.com/u/0/106075758531242552855/posts/CZohK9dHWUn</ref><br />
<br />
"''It's look like Veda confirm the rumor with a tablet, Veda X75, which include an A40 (Quad-Core / 8GPU)''".<ref>http://www.new-dragon.cn/product.asp?id=74</ref><br />
<br />
Onda V972, a 10-inch Android tablet, was the first device to be publicly announced to come with an Allwinner A31 SoC.<ref>http://www.cnx-software.com/2012/12/06/240-onda-v972-allwinner-a31-quad-core-android-tablet-with-9-7-retina-display/</ref><br />
<br />
= Documentation =<br />
<br />
* [http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf A31 User Manual v1.1] <small>(PDF, 1050 pages, 2013-06-30)</small><br />
* [http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf A31 datasheet v1.3] <small>(PDF, 42 pages, 2013-11-06)</small><br />
* [http://dl.linux-sunxi.org/A31/A31%20Datasheet%20-%20v1.00%20(2012-11-06).pdf A31 datasheet v1.0] <small>(PDF, 43 pages, 2012-11-06)</small><br />
* [http://dl.linux-sunxi.org/A31/A31%20Brief%20v1.1.pdf A31 Brief v1.1] <small>(PDF, 3 pages)</small><br />
<br />
= Software =<br />
== Original SDKs ==<br />
We have made some SDKs available on our server:<br />
* a31_V4.5_MerriiLinux_Humming ([http://dl.linux-sunxi.org/SDK/A31/a31_V4.5_MerriiLinux_Humming.tar.gz Full], [http://dl.linux-sunxi.org/SDK/A31/a31_V4.5_MerriiLinux_Humming-stripped.tar.xz Reduced], [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/ Unpacked])<br />
* a31_hummbingbird_V3.3_v2_kfb_0k ([http://dl.linux-sunxi.org/SDK/A31/a31_hummbingbird_V3.3_v2_kfb_0k.tar.gz Full], [http://dl.linux-sunxi.org/SDK/A31/a31_hummbingbird_v3.3_v2_kfb_ok-stripped.tar.xz Reduced], [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_hummbingbird_v3.3_v2_kfb_ok/ Unpacked]) <br />
* a31_v4.5_hummingbird_kfb_ok ([http://dl.linux-sunxi.org/SDK/A31/a31_v4.5_hummingbird_kfb_ok.tar.gz Full], [http://dl.linux-sunxi.org/SDK/A31/a31_v4.5_hummingbird_kfb_ok-stripped.tar.xz Reduced], [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/ Unpacked])<br />
<br />
== GPL Violations ==<br />
<br />
The publically available SDKs contain kernel and u-boot trees which include and depend on several binaries. Allwinner is [[GPL_Violations |violating the GPL quite directly here]].<br />
<br />
=== a31_hummbingbird_V3.3_v2_kfb_0k SDK ===<br />
==== kernel ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_hummbingbird_v3.3_v2_kfb_ok/lichee/linux-3.3/drivers/input/touchscreen/ drivers/input/touchscreen/libAW5306]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_hummbingbird_v3.3_v2_kfb_ok/lichee/linux-3.3/drivers/media/video/sunxi-vfe/lib/ drivers/media/video/sunxi-vfe/lib/libisp]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_hummbingbird_v3.3_v2_kfb_ok/lichee/linux-3.3/modules/nand_v2/ modules/nand_v2/libnand]<br />
<br />
==== u-boot ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_hummbingbird_v3.3_v2_kfb_ok/lichee/u-boot/nand_sunxi/ nand_sunxi/libnand]<br />
<br />
=== a31_V4.5_MerriiLinux_Humming SDK ===<br />
==== kernel ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/linux-3.3/drivers/input/touchscreen/ drivers/input/touchscreen/libAW5306]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/linux-3.3/drivers/media/video/sunxi-vfe/lib/ drivers/media/video/sunxi-vfe/lib/libisp]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/linux-3.3/modules/nand/ modules/nand/libnand]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/linux-3.3/modules/nand_v2/ modules/nand_v2/libnand]<br />
<br />
==== u-boot ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/brandy/u-boot-2011.09/nand_sunxi/sun7iw1/ nand_sunxi/sun7iw1/libnand-sun7iw1]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/brandy/u-boot-2011.09/nand_sunxi/sun8iw1/ nand_sunxi/sun8iw1/libnand-sun8iw1]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/brandy/u-boot-2011.09/nand_sunxi/sun8iw3/ nand_sunxi/sun8iw3/libnand-sun8iw3]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_V4.5_MerriiLinux_Humming/brandy/u-boot-2011.09/nand_sunxi/sun9iw1/ nand_sunxi/sun9iw1/libnand-sun9iw1]<br />
<br />
=== a31_v4.5_hummingbird_kfb_ok SDK ===<br />
==== kernel ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/linux-3.3/drivers/media/video/sunxi-vfe/lib/ drivers/media/video/sunxi-vfe/lib/libisp]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/linux-3.3/modules/nand_v2/ modules/nand_v2/libnand]<br />
<br />
[http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/linux-3.3/drivers/input/touchscreen/AW5306_ts.c AW5306 code] does seem to be available in this release, which reveals that this is [http://www.awinic.com.cn/cn/index/index.aspx Awinic code]<br />
<br />
==== u-boot ====<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/brandy/u-boot-2011.09/nand_sunxi/sun7iw1/ nand_sunxi/sun7iw1/libnand-sun7iw1]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/brandy/u-boot-2011.09/nand_sunxi/sun8iw1/ nand_sunxi/sun8iw1/libnand-sun8iw1]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/brandy/u-boot-2011.09/nand_sunxi/sun8iw3/ nand_sunxi/sun8iw3/libnand-sun8iw3]<br />
* [http://dl.linux-sunxi.org/SDK/A31/unpacked-stripped/a31_v4.5_hummingbird_kfb_ok/lichee/brandy/u-boot-2011.09/nand_sunxi/sun9iw1/ nand_sunxi/sun9iw1/libnand-sun9iw1]<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A31 Devices</categorytree><br />
= See also =<br />
* [[A10]]<br />
* [[A10s]]<br />
* [[A13]]<br />
* [[A20]]<br />
* [[A23]]<br />
* [[A31 EVB]]<br />
* [[A33]]<br />
* [[Power VR]]<br />
<br />
=Owners of the SoC on IRC=<br />
bamvor, ojn, drachensun or mripard own an A31-based board.<br />
<br />
=Community Support=<br />
There is no support for the A31 and the A31s in u-boot-sunxi and in the linux-sunxi 3.4 kernel, but both [[Mainline U-boot|mainline u-boot]] and the [[Linux mainlining effort| mainline Linux kernel]] have basic support for the A31 and A31s (cf. the respective links for further information).<br />
<br />
=References=<br />
<references /><br />
<br />
= External links =<br />
* [http://allwinnertech.com/en/clq/processora/A31.html Product Page]<br />
* [http://www.gizmochina.com/2012/12/05/ampe-a10-tablet-tear-down-with-allwinner-a31-quad-core-processor/ A31 PCB - tablet tear down]<br />
* [http://linux-sunxi.org/images/3/38/A31_Brief_v1.1.pdf Allwinner A31 Brief]<br />
* [http://linux-sunxi.org/images/e/e1/PAD_APP4_STD_V1_40_20120927.pdf Allwinner A31 Block Diagram]<br />
* [http://service.awbase.com:8000/faq/index.php/A31_DDR%E5%88%97%E8%A1%A8 A31 Supported DDR list]<br />
* [http://service.awbase.com:8000/faq/index.php/A31_NAND%E5%88%97%E8%A1%A8 A31 Supported NAND list]<br />
* [http://service.awbase.com:8000/faq/index.php/A31_LCD%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A31 Supported LCD modules list]<br />
* [http://service.awbase.com:8000/faq/index.php/A31_C-TOUCH%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A31 Supported Capacitive touch sensor list]<br />
* [http://service.awbase.com:8000/faq/index.php/A31_Camera%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A31 Supported Camera devices list]<br />
* [http://git.rhombus-tech.net/linux Allwinner A31 kernel source code]<br />
* [http://git.rhombus-tech.net/?p=u-boot.git;a=tree;h=refs/heads/allwinner-sunxi-a31;hb=refs/heads/allwinner-sunxi-a31 Allwinner A31 U-boot source code]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A13&diff=17520
A13
2016-06-06T19:26:24Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = 55''nm''<br />
| cpu = ARM Cortex-A8 @ 1Ghz<br />
| ltwo = 256KB<br />
| extensions = NEON, VFPv3<br />
| memory = DDR2, DDR3 (max 512MB @ DDR800)<br />
| gpu = [[Mali400|Mali 400 MP1]] <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = LCD<br />
| audio = Mic, Headphone<br />
| network = -<br />
| storage = NAND (max 2 * 32GB), SD Card 3.0<br />
| usb = 2 (1 HOST, 1 OTG)<br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/en/clq/processora/A13.html Product Page]<br />
}}<br />
<br />
[[Allwinner]] '''A13''' is SoC with build-in ARM Cortex A8 CPU ARM Mali 400 GPU and Allwinner Cedar Engine VPU<br />
<br />
=Overview=<br />
==Main components of the A13:==<br />
* CPU: [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8 1GHz (ARM v7) Processor] which have both [[Vector Floating Point Unit|VFPv3]] and [[NEON]] co-processors: <br />
** FPU: [[Vector Floating Point Unit]] (standard ARM VFPv3 FPU Floating Point Unit)<br />
** SIMD: [[NEON]] (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
<br />
The A13 is a cheaper version of the A10 which lacks HDMI-transmitter and SATA-controller, as it is primarily targeted towards tablets. The A13 also lacks G2D and therefor needs to rely on NEON code for 2d acceleration.<br />
<br />
= Documentation =<br />
* [[Media:A13 Datasheet.pdf|A13 Datasheet]]<br />
* [http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf Allwinner A13 Manual v1.2] <small>(PDF, 409 pages, 2013-01-08)</small><br />
* [http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf Allwinner A13 Datasheet v1.12] <small>(PDF, 60 pages, 2012-03-29)</small><br />
* [http://dl.linux-sunxi.org/A13/A13%20brief.pdf Allwinner A13 Brief] <small>(PDF, 2 pages, 2011)</small><br />
* [http://service.awbase.com:8000/faq/index.php/A13_DDR%E5%88%97%E8%A1%A8 A13 Supported DDR list]<br />
* [http://service.awbase.com:8000/faq/index.php/A13_NAND%E5%88%97%E8%A1%A8 A13 Supported NAND list]<br />
* [http://service.awbase.com:8000/faq/index.php/A13_LCD%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A13 Supported LCD modules list]<br />
* [http://service.awbase.com:8000/faq/index.php/A13_C-TOUCH%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A13 Supported Capacitive touch sensor list]<br />
* [http://service.awbase.com:8000/faq/index.php/A13_Camera%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A13 Supported Camera devices list]<br />
= Register Guide =<br />
[[A13 Register guide]]<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A13 Devices</categorytree><br />
= Links =<br />
* [http://allwinnertech.com/en/clq/processora/A13.html Product Page] <small>(Allwinner Tech)</small><br />
* [https://www.olimex.com/Products/Components/IC/A13-AXP209/ Olimex product page]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A10s&diff=17519
A10s
2016-06-06T19:25:06Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = 55''nm''<br />
| cpu = ARM Cortex-A8 @ 1Ghz<br />
| ltwo = 256KB<br />
| extensions = NEON, VFPv3<br />
| memory = DDR2, DDR3 (max 2GB @ DDR800)<br />
| gpu = [[Mali400|Mali 400 MP1]] <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = HDMI, LCD<br />
| audio = I2S, AC97<br />
| network = Ethernet 10/100<br />
| storage = NAND (max 64GB), SD Card 3.0<br />
| usb = 2 <br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/product/A10s.html Product Page]<br />
}}<br />
<br />
<br />
The [[Allwinner]] '''A10s''' is a Cortex-A8 of 55nm with [[Mali400]] GPU and [[Cedar Engine]] VPU.<br />
<br />
=Overview=<br />
==Main components of the A10s:==<br />
* CPU: [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8 1GHz (ARM v7) Processor] which have both VFPv3 and NEON co-processors: <br />
** FPU: standard ARM VFPv3 FPU Floating Point Unit<br />
** SIMD: NEON (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
* HDMI-transmitter: HDMI CEC (Consumer Electronics Control)<br />
<br />
The A10s is a cheaper version of the [[A10]] which lacks SATA-controller, as it is primarily targeted towards HDMI plug PC.<br />
<br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A10s Devices</categorytree><br />
= See Also =<br />
* [[A10]]<br />
* [[A13]]<br />
* [[A10s/PIO]]<br />
* [http://olimex.wordpress.com/2012/04/24/cortex-a8-in-tqfp-sure-allwinner-a13/ Olimex blog: "Cortex A8 in TQFP? sure Allwinner A13"]<br />
<br />
== External ==<br />
* [http://www.allwinnertech.com/product/A10s.html Product Page] <small>(Allwinner Tech)</small><br />
* [https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A10S-PDFs Brief datasheet etc]<br />
* [https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A10S-OLinuXino-MICRO A10S-OLinuXino-MICRO Board schematics by Olimex]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=A10&diff=17518
A10
2016-06-06T19:24:19Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>{{Infobox SoC<br />
| image = <br />
| manufacturer = Allwinner<br />
| process = 55''nm''<br />
| cpu = ARM Cortex-A8 @ 1Ghz<br />
| ltwo = 256KB<br />
| extensions = NEON, VFPv3<br />
| memory = DDR2, DDR3 (max 2GB @ DDR800)<br />
| gpu = [[Mali400|Mali 400 MP]] <br />
| vpu = [[Cedar Engine]]<br />
| apu = <br />
| video = HDMI, LCD<br />
| audio = I2S, SPDIF, AC97<br />
| network = Ethernet 10/100<br />
| storage = NAND (max 64GB) SATA II, SD Card 3.0<br />
| usb = 3 <br />
| other = <br />
| release_date =<br />
| website = [http://www.allwinnertech.com/product/A10.html Product Page]<br />
}}<br />
<br />
<br />
The [[Allwinner]] '''A10''' (aka ''sun4i'') is a Cortex-A8 of 55nm with [[Mali400]] GPU and [[Cedar Engine]] VPU.<br />
<br />
=Overview=<br />
==Main components of the A10 ==<br />
* CPU: [http://en.wikipedia.org/wiki/ARM_Cortex-A8 Cortex-A8 1GHz (ARM v7) Processor] which have both VFPv3 and NEON co-processors: <br />
** FPU: standard ARM VFPv3 FPU Floating Point Unit<br />
** SIMD: NEON (ARM's extended general-purpose SIMD vector processing extension engine)<br />
* GPU: [[Mali400]]<br />
* VPU: [[Cedar Engine]] (Video Processor Unit for audio and video hardware decoding or encoding)<br />
* HDMI-transmitter: HDMI CEC (Consumer Electronics Control)<br />
<br />
<br />
Contrary what mis-marketing would like people to believe, the Allwinner A10 does only seldomly clocks beyond 1008MHz. Usually, the marketing info likes to state 1.2GHz, which is definitely not possible.<br />
<br />
= Documentation =<br />
* [http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf Allwinner A10 User Manual v1.20] <small>(PDF 495 pages, 2012-04-09)</small><br />
* [http://dl.linux-sunxi.org/A10/A10%20Transport%20Stream%20Controller%20V1.00%2020120917.pdf A10 Transport Stream Controller V1.0]<br />
* [http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf Allwinner A10 Datasheet v1.21] <small>(PDF, 83 pages, 2012-04-06)</small><br />
* [http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.00%20%282011-08-22%29.pdf Allwinner A10 Datasheet v1.00] <small>(PDF, 72 pages, 2011-08-22)</small><br />
* [http://dl.linux-sunxi.org/A10/A1X%20Brief--2011.9.2Rev6.pdf Allwinner A10 Brief] <small>(PDF, 2 pages, 2011-09-02)</small><br />
* [http://service.awbase.com:8000/faq/index.php/A10_DDR%E5%88%97%E8%A1%A8 A10 Supported DDR list]<br />
* [http://service.awbase.com:8000/faq/index.php/A10_NAND%E5%88%97%E8%A1%A8 A10 Supported NAND list]<br />
* [http://service.awbase.com:8000/faq/index.php/A10_LCD%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A10 Supported LCD modules list]<br />
* [http://service.awbase.com:8000/faq/index.php/C-TOUCH%E6%A8%A1%E7%BB%84%E6%94%AF%E6%8C%81%E5%88%97%E8%A1%A8 A10 Supported Capacitive touch sensor list]<br />
* [http://service.awbase.com:8000/faq/index.php/A10_Camera%E6%A8%A1%E7%BB%84%E5%88%97%E8%A1%A8 A10 Supported Camera devices list]<br />
= Register guide =<br />
<categorytree mode=pages hideroot=on depth=1>A10_Register_guide</categorytree><br />
= Devices =<br />
<categorytree mode=pages hideroot=on depth=1>A10 Devices</categorytree><br />
= Links =<br />
* [http://allwinnertech.com/en/clq/processora/A10.html Product Page] <small>(Allwinner Tech)</small><br />
* [http://wikipedia.org/wiki/Allwinner%20a10 Wikipedia Entry]<br />
* [https://www.olimex.com/Products/Components/IC/A10-AXP209/ Olimex product page]<br />
<br />
= See Also =<br />
* [[Media:A10 Datasheet.pdf|A10 Datasheet]]<br />
<br />
* [[Fex Guide]]<br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=F20&diff=17517
F20
2016-06-06T19:22:51Z
<p>Nove: Use cedar engine as the name of the video engine hardware (aka VPU).</p>
<hr />
<div>== Specifications ==<br />
* ARM926T<br />
* [[Cedar Engine]] VPU<br />
<br />
== See also ==<br />
* [[Media:F20 Datasheet.pdf|F20 Datasheet]]<br />
* [[A10]]/[[A13]]<br />
<br />
== External ==<br />
<br />
* [https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.4/arch/arm/mach-sun3i kernel sources]<br />
* [http://dl.linux-sunxi.org/F20/F20%20Datasheet%20-%20v1.01%20%282010-12-12%29.pdf Allwinner/Boxchip F20 Datasheet v1.01] <small>(PDF, 111 pages, 2010-12-12)</small><br />
* [http://www.allwinnertech.com/product/F20.html Product Page] <small>(Allwinner Tech)</small><br />
<br />
[[Category:System on Chip]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedar_Engine&diff=17515
Cedar Engine
2016-06-06T19:03:37Z
<p>Nove: Redirected page to Video Engine</p>
<hr />
<div>#REDIRECT [[Video Engine]]</div>
Nove
https://linux-sunxi.org/index.php?title=Cedar_Engine&diff=17514
Cedar Engine
2016-06-06T19:02:25Z
<p>Nove: Created page with "# REDIRECT Video Engine"</p>
<hr />
<div># REDIRECT [[Video Engine]]</div>
Nove
https://linux-sunxi.org/index.php?title=Video_Engine&diff=17513
Video Engine
2016-06-06T18:57:12Z
<p>Nove: Redirected page to Category:Video Engine</p>
<hr />
<div>#REDIRECT [[:Category:Video Engine]]</div>
Nove
https://linux-sunxi.org/index.php?title=Category:Video_Engine&diff=17512
Category:Video Engine
2016-06-06T18:48:37Z
<p>Nove: H3 and A64 datasheet/user manual naming.</p>
<hr />
<div>Video Engine is the plain name used by Allwinner for the hardware block responsible with the task of decoding and encoding video formats.<br />
<br />
== Naming ==<br />
There is some confusion around how to name this video engine, with the principal reason been the non-existent clear branding by Allwinner.<br />
<br />
* '''CedarX'''<br />
: The name given to the proprietary software libraries for video and audio (CedarV + CedarA). As for audio, the hardware ACE (Audio Codec Engine) appear to only exist in A10 and older SoCs.<br />
<br />
* '''Cedar Engine'''<br />
: As found in the kernel driver (/dev/cedar_dev) [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L52 source code] where it has been directly referred to as "cedar engine" in [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L360 error/information messages] and [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L105 internal variables]. Take note that this is the kernel driver that was made for the proprietary libraries that already existed in Melis OS, were the media player application goes by the name [http://4pda.ru/forum/index.php?showtopic=287496&st=280#entry11738725 "cedar"].<br />
<br />
* '''MACC''' - '''M'''edia '''ACC'''elerate video engine<br />
: Also found in the kernel driver and [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.h#L116 respective headers], where the [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L89 mmio area (registers)] is referenced by ''macc'' as a prefix for the definition of the [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.h#L123 register base address].<br />
<br />
* '''VE''' - Video Engine<br />
: This is the most common name used in all the places for this hardware block. It is believed that '''VE''' is a short form of '''VCE''' (Video Codec Engine) to be in accordance with ACE (Audio Codec Engine) and is also the best generic name to describe this type of hardware block.<br />
<br />
==== Naming in the datasheets and user manuals. ====<br />
{| class="wikitable" style="text-align:center;"<br />
! SOC !! features label !! block diagram !! related registers<br />
|-<br />
| A10 || VPU || VE || VE<br />
|-<br />
| A10s || VPU || VPU || VE<br />
|-<br />
| A13 || VPU || VPU || VE<br />
|-<br />
| A20 || Video Engine (Phoenix 3.0) || Video Engine || VE<br />
|-<br />
| A23 || Video Engine || Video Engine || VE<br />
|-<br />
| A31 || Video Engine || Video Engine || VE<br />
|-<br />
| A31s || Video Engine || Video Engine || VE<br />
|-<br />
| A33 || Video Engine || Video Engine || VE<br />
|-<br />
| A80 || Video Engine || Video Engine || VE<br />
|-<br />
| A83T || Video Engine || ''claims decoder/encoder is part of the GPU block'' || VE<br />
|-<br />
| H3 || Video Engine || Video Engine || VE<br />
|-<br />
| A64 || Video Engine || Video Engine || VE<br />
|}</div>
Nove
https://linux-sunxi.org/index.php?title=Category:Video_Engine&diff=17511
Category:Video Engine
2016-06-06T18:39:04Z
<p>Nove: Reference in how the hardware is named in the kernel driver source code.</p>
<hr />
<div>Video Engine is the plain name used by Allwinner for the hardware block responsible with the task of decoding and encoding video formats.<br />
<br />
== Naming ==<br />
There is some confusion around how to name this video engine, with the principal reason been the non-existent clear branding by Allwinner.<br />
<br />
* '''CedarX'''<br />
: The name given to the proprietary software libraries for video and audio (CedarV + CedarA). As for audio, the hardware ACE (Audio Codec Engine) appear to only exist in A10 and older SoCs.<br />
<br />
* '''Cedar Engine'''<br />
: As found in the kernel driver (/dev/cedar_dev) [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L52 source code] where it has been directly referred to as "cedar engine" in [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L360 error/information messages] and [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L105 internal variables]. Take note that this is the kernel driver that was made for the proprietary libraries that already existed in Melis OS, were the media player application goes by the name [http://4pda.ru/forum/index.php?showtopic=287496&st=280#entry11738725 "cedar"].<br />
<br />
* '''MACC''' - '''M'''edia '''ACC'''elerate video engine<br />
: Also found in the kernel driver and [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.h#L116 respective headers], where the [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.c#L89 mmio area (registers)] is referenced by ''macc'' as a prefix for the definition of the [https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/media/video/sunxi/sunxi_cedar.h#L123 register base address].<br />
<br />
* '''VE''' - Video Engine<br />
: This is the most common name used in all the places for this hardware block. It is believed that '''VE''' is a short form of '''VCE''' (Video Codec Engine) to be in accordance with ACE (Audio Codec Engine) and is also the best generic name to describe this type of hardware block.<br />
<br />
==== Naming in the datasheets and user manuals. ====<br />
{| class="wikitable" style="text-align:center;"<br />
! SOC !! features label !! block diagram !! related registers<br />
|-<br />
| A10 || VPU || VE || VE<br />
|-<br />
| A10s || VPU || VPU || VE<br />
|-<br />
| A13 || VPU || VPU || VE<br />
|-<br />
| A20 || Video Engine (Phoenix 3.0) || Video Engine || VE<br />
|-<br />
| A23 || Video Engine || Video Engine || VE<br />
|-<br />
| A31 || Video Engine || Video Engine || VE<br />
|-<br />
| A31s || Video Engine || Video Engine || VE<br />
|-<br />
| A33 || Video Engine || Video Engine || VE<br />
|-<br />
| A80 || Video Engine || Video Engine || VE<br />
|-<br />
| A83T || Video Engine || ''claims decoder/encoder is part of the GPU block'' || VE<br />
|}</div>
Nove
https://linux-sunxi.org/index.php?title=Cedrus/Supported_Codec_Feature_Matrix&diff=17405
Cedrus/Supported Codec Feature Matrix
2016-05-31T21:24:29Z
<p>Nove: Explain why there are codecs that are still not reverse engineered.</p>
<hr />
<div>In this colorful table is represented what is understood and supported by hardware in the '''left side''', the designation VE+Number are the video engine hardware version and above are the SoCs were found. Here are only SoCs and hardware versions which was confirmed or reported, the ones that aren't here should and are expected to be very equal in mode.<br />
<br />
The '''right side''' represents the state of software. Take notice about the PoC (Prof of Concept) in which only exists for demonstration the correct understanding about the working of the hardware, sometimes the creation of this PoC is skipped.<br />
<br />
{| border="1px" cellpadding="4px" style="border-collapse:collapse; border: 0px solid #A44444; text-align: center;"<br />
|colspan=" 3" style="border: 0px;"| <br />
|A10/A20 || A13 || A31s || A80 || A33 || H3 || A64 <br />
|rowspan="99" style="border: 0px; min-width: 10px"| ||colspan="2" style="border: 0px"| Software Support<br />
|-<br />
!style="border: 0px"| !! subengine !! codec <br />
! VE1623 !! VE1625 !! VE1633 !! VE1639 !! VE1667 !! VE1680 !! VE1689 <br />
! PoC !! libvdpau-sunxi <br />
|-style="background-color: #77FF77"<br />
|rowspan="18"| decoder ||rowspan="11"| [[VE_Register_guide#MPEG_Engine_Registers|0x100]] || JPEG/MJPEG <br />
|colspan="7"| baseline profile only<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| MPEG1 <br />
|colspan="7"|<br />
| ||<br />
|-style="background-color: #77FF77"<br />
| MPEG2 <br />
|colspan="7"|<br />
| ||<br />
|-style="background-color: #FFFF77"<br />
| MPEG4 <br />
|colspan="7"|<br />
|style="background-color:#FFFFFF"| ||<br />
|-style="background-color: #FFFF77"<br />
| MS-MPEG4 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||rowspan="3" style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #FF7777"<br />
| WMV1 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FF7777"<br />
| WMV2 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FFFF77"<br />
| DIVX <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #FFFF77"<br />
| XDIV <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||rowspan="5" style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #FF7777"<br />
| H263 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #FF7777"<br />
| VP6 <br />
|colspan="7"|<br />
|<br />
|-style="background-color: #CCCCCC"<br />
| rowspan=" 2"| ? || Sorenson <br />
|colspan="7"| Unconfirmed<br />
|<br />
|-style="background-color: #CCCCCC"<br />
| AVS <br />
|colspan="7"| Unconfirmed<br />
|<br />
|-style="background-color: #77FF77"<br />
| rowspan=" 2"| [[VE_Register_guide#H264_Engine_Registers|0x200]] || H264 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #77FF77"<br />
| VP8 <br />
|colspan="7"|<br />
| ||style="background-color: #FFFFFF"| n.a.<br />
|-style="background-color: #FF7777"<br />
| rowspan=" 1"| [[VE_Register_guide#VC1_Engine_Registers|0x300]] || VC1/WMV9 <br />
|colspan="7"|<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #CCCCCC"<br />
| rowspan=" 1"| [[VE_Register_guide#RMVB_Engine_Registers|0x400]] || RMVB<br />
|colspan="7"| Unconfirmed<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| rowspan=" 1"| [[VE_Register_guide#HEVC_Engine_Registers|0x500]] || H265 <br />
|colspan="5" style="background-color: #FFFFFF"| ||colspan="2"|8bits<br />
|style="background-color: #FFFFFF"| ||<br />
|-style="background-color: #77FF77"<br />
|rowspan=" 2"|encoder <br />
|rowspan=" 2"| [[VE_Register_guide#ISP_Engine_Registers|0xa00]]</br>[[VE_Register_guide#AVC_Encoder_Engine_Registers|0xb00]]<br />
| JPEG/MJPEG<br />
|colspan="2"|baseline profile only||colspan="5" style="background-color: #FFAA77"| Untested<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #77FF77"<br />
| H264 <br />
|colspan="2"|baseline profile only||colspan="5" style="background-color: #FFAA77"| Untested<br />
|No B frames ||style="background-color: #FFFFFF"|n.a.<br />
|-style="background-color: #CCCCCC"<br />
|rowspan=" 1"|decoder ||rowspan=" 1"| 0xe00 || JPEG<br />
|colspan="5" style="background-color: #FFFFFF"| ||colspan="2"| Unconfirmed<br />
| ||style="background-color: #FFFFFF"|n.a.<br />
|-<br />
|}<br />
<br />
<br />
As can be seen in this table with the color of green, the most used video codecs are already fully reversed engineered. The codecs that are still missing are too old or/and obsolete and aren't used anymore for the creation of new video content. The content (video files) that exists encoded in this codecs is in the great majority not beyond standard definition, meaning that the task of decoding is easy done with just software decode by cpu.<br />
For this reason this codecs aren't a priority to work on.<br />
<br />
If anyone has a need for a yet to be support codec, please contact the people involved in the cedrus project to find what can be arranged.</div>
Nove
https://linux-sunxi.org/index.php?title=VE_Planning&diff=17404
VE Planning
2016-05-31T20:14:25Z
<p>Nove: media request api RFC version 2</p>
<hr />
<div>This is a page for planning the effort of the writing of a driver for the video engine in the right way (well, in the best possible way).<br />
<br />
__NOTOC__<br />
<br />
== V4L2 codec interface ==<br />
<br />
The only existent kernel framework suited for this type of hardware device is the video-for-linux [http://linuxtv.org/downloads/v4l-dvb-apis/codec.html codec interface]. However not without a few obstacles.<br />
([[VE/V4L2_mem2mem/Others|Other users]] of this same framework.)<br />
<br />
==== Tile format ====<br />
* For the tile format specific to this video engine, V4l2 doesn't have (yet) this pixel format. Until then, as in v4l2, the pixel formats are represented as fourcc identifiers in an u32 value. It will be sufficient to define this custom tile format in the driver and user headers. [http://lxr.free-electrons.com/ident?i=IPU_PIX_FMT_GBR24 Example.]<br />
<br />
==== 256MiB limit ====<br />
* This video engine requires contiguous physical memory buffers to be located in the lower 256MiB of memory.<br />
: ideally if possible instead of having a fixed memory region, all should be available for allocation<br />
:* videobuf2-dma-contig, allocates physical contiguous buffers, but to restrit to low 256M, requires ''dma_declare_coherent_memory'' to be called. [http://lxr.free-electrons.com/source/drivers/media/platform/s5p-mfc/s5p_mfc.c?v=3.17#L1021 Example.] The declared memory region must be reserved using the generic [http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt /reserved-memory] node.<br />
:* from outside mainline there exists also [https://android.googlesource.com/kernel/exynos.git/+/android-exynos-3.4/drivers/media/video/videobuf2-cma-phys.c videobuf2-cma-phys] and [https://android.googlesource.com/kernel/exynos.git/+/android-exynos-3.4/drivers/media/video/videobuf2-ion.c videobuf2-ion]<br />
<br />
==== Decoder batching ====<br />
* decoder will work notably faster when frames are batched (not one shoot mode).<br />
<br />
==== Device nodes ====<br />
* not all combination of the aggregated pixel formats (from isp subengine, encoder, decoder) are possible.<br />
: From this [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/82907/focus=82918 example], we can see that multiple device nodes is preferred. The use of three device nodes appears to be the most suited.<br />
<pre><br />
/dev/videoW<br />
isp subengine - raw pixel formats => raw pixel formats subset<br />
<br />
/dev/videoX<br />
encoder - raw pixel formats => bitstream formats<br />
<br />
/dev/videoY<br />
decoder - bitstream formats => raw pixel format<br />
</pre><br />
<br />
==== No parsing in kernel ====<br />
* this video engine is a fixed function engine, this is a advantage by its simplicity, but in other ways this means that bitstream parsing can't be done by a firmware. Bitstream parsing in the kernel is not allowed.<br />
<br />
:* More information from a[http://linuxtv.org/news.php?entry=2013-11-30.mchehab Linux Kernel Media Workshop] where this matter was discussed, copied here for easyness.<br />
<br />
<pre><br />
13: Hugues Fruchet: Video codecs<br />
<br />
There's a need to parse bitstream fields for those codecs, but that requires complex code (10K lines). Moving it to kernel could make it unstable, as it is harsh to write those parsers without any risk of causing crashes.<br />
It seems to be better to put those parsers inside libv4l, using an open source license.<br />
<br />
Results:<br />
<br />
Drivers that require proprietary user space components should stay out of mainline<br />
Multi-format buffers could be useful here<br />
The hardware/firmware needs a lot of data extracted from the bitstream next to the bitstream itself. This is a custom format, so it is OK to add a new pixelformat for each of those formats. Such complex parsing should be done in userspace in libv4l2.<br />
If very little parsing is required (MPEG), then that can be done in the kernel instead.<br />
Recommendation is to start simple with e.g. just an MPEG implementation.<br />
</pre><br />
<br />
:* [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/97350 '''Request API'''], is a newer still experimental addition to V4L2 and Media Controller framework. In resume, any number of controls (configuration data) can be packed in a object called ''request'', and if attached to a buffer, the driver can apply this configuration to the hardware when processing said buffer.<br />
::* [http://blogs.s-osg.org/planning-future-media-linux-linux-kernel-summit-media-workshop-seoul-south-korea/ Linux Kernel Summit Media WorkShop - Planning Out the Future of Media on Linux]<br />
::* [https://openiotelc2016.sched.org/event/6DAG/v4l2-on-steroids-the-request-api-laurent-pinchart V4L2 on steroids: The Request API] ([https://www.youtube.com/watch?v=W35u-hU22hY Video.])<br />
::* [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/101993 Media Request API (RFC patches)] [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/102395 v2]<br />
<br />
== Way to go forward. ==<br />
* initial we can ignore that bitstream parsing is been done in the kernel, and first aim to have a working driver.<br />
:* other option can be to split the driver in a common part that can be mainlined, and for each codec do as a submodule that can compiled out of tree. This also allows the distributions to choose which codecs to include.<br />
* this means that initially we will not worry about working for the inclusion in the mainline kernel (because the bitstream parsing will be rejected.)<br />
* using libv4l2 as suggested above to do the bitstream parsing in user space.<br />
:* in this [http://git.linuxtv.org/cgit.cgi/v4l-utils.git/tree/lib/libv4l2/libv4l2.c?id=56676348e48648146250aaf2770b2f8a6bd796cd#n21 paragraph] is explained that libv4l2 can transparently convert between formats, when the requested format mismatch the formats supported by the hardware driver. As in V4L2 a codec bitstream is considered as in equal mode to an image format, it should be possible to also convert bitstream format to a pre-parsed bitstream format compatible with the specificities of this video engine.<br />
:* there is also [http://git.linuxtv.org/cgit.cgi/v4l-utils.git/commit/lib/libv4l2/v4l2-plugin.c libv4l2 plugins], in which could offer a possible way to do this transparent bitstream conversion.<br />
:* perpendicular [http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/91865/focus=92195 discussion] that reaffirms the place for bitstream parsers.<br />
<br />
== Progress status ==<br />
<i>Detail of the conclusion of each step for each target kernel version (sunxi-3.4 / distro kernel / mainline).</i><br />
<br />
== User Land ==<br />
* Will aim to preserve the compatibility with similar users of v4l2 codec interfaces. Within its limits.<br />
* By the motive of the numerous video codecs apis in existence and equal mode the number of media players, the implementation of the support is outside the scope of this effort.<br />
* Only will be written simple programs for testing and example in how to use.<br />
<br />
==== gstreamer ====<br />
* already includes [http://cgit.freedesktop.org/gstreamer/gst-plugins-good/tree/sys/v4l2/gstv4l2videodec.c support] for v4l2 mem2mem ''decoder'' devices. [http://gstconf.ubicast.tv/videos/the-development-of-video4linux-decoder-support/ the development of video4linux decoder support]<br />
<br />
* ''encoder'' is '''''work in progress''''' [https://bugzilla.gnome.org/show_bug.cgi?id=728438 Bug 728438 - v4l2: Implement a v4l2 video encoder ]<br />
<br />
==== ffmpeg ====<br />
<br />
* there were some [http://thread.gmane.org/gmane.comp.video.ffmpeg.devel/185764 patches] but they didn't go forward.<br />
<br />
[[Category:Cedrus]]</div>
Nove