PWM Controller Register Guide

= PWM = There are two 16-bit up counters in the A10 SoC. Counters will reset when PWM_CH0_PERIOD/PWM_CH1_PERIOD has been reached. On initialization PWM_OUT is active high and starts counting from 0x0000.

The PWM divisor devides the 24MHz clock by 1-4096 depending on the PWM_CTRL register.

There are two output modes, cycle mode and pulse mode which are either, a square waveform or a postive/negative pulse, based on the frequency in the PWM_CH0_PERIOD/PWM_CH1_PERIOD register.

Info
PWM Base address: 0x01c20e00

PWM_CTRL
Default value: 0x00000000

Offset: 0x00

PWM_CH0_PERIOD
Default value: 0x00000000

Offset: 0x04

PWM_CH1_PERIOD
Default value: 0x00000000

Offset: 0x08

default map
md 0x01c20e00 3 01c20e00: 00000000 00000000 00000000   ...........

all to 1
mw 0x01c20e00 0xffffffff 3

md 0x01c20e00 3 01c20e00: 007f80ff 00ff00ff 00ff00ff   ............

all to 0
mw 0x01c20e00 0x00 3

md 0x01c20c00 3 01c20c00: 00000000 00000000 00000000   ............