Clock Control Module

= Clock Control Module =

Overview
Allwinner's A10 has 10 timing or clock sources. 7 Phase Locking Loop's (PLL's), a 24MHz main crystal oscillator, an RC based internal on chip based oscillator and a low-power 32kHz crystal oscillator.

The 24MHz crystal oscillator is mandatory and is responsible for supplying a clock source for the PLL. The 32kHz crystal oscillator is connected only to the RTC to ensure proper time is kept.

Many devices being driving by any of these clocks have often 2 clocks connected to them. One of the clocks drives the chip itself, the other clock matches the bus to whatever it is connected (usually the CPU).

Clock generation
All PLL's are fed from the 24 MHz reference clock.

Timer Registers
Timer Base address: 0x01c20000

CCM_PLL1_CFG
Default value: 0x21005000

Offset: 0x0000

CCM_PLL1_TUN
Default value: unknown

Offset: 0x0004

CCM_PLL1_TUN2
Default value: unknown

Offset: 0x0038

CCM_PLL2_CFG
Default value: 0x81000010

Offset: 0x0008

CCM_PLL2_TUN
Default value: 0x00000000

Offset: 0x000c

CCM_PLL3_CFG
Default value: 0x0010d063

Offset: 0x0010

CCM_PLL4_CFG
Default value: 0x21081000

Offset: 0x0018

CCM_PLL5_CFG
Default value: 0x11049280

Offset: 0x0020

CCM_PLL5_TUN
Default value: unknown

Offset: 0x0024

CCM_PLL5_TUN2
Default value: 0x00000000

Offset: 0x003c

CCM_PLL6_CFG
Default value: 0x21009911

Offset: 0x0028

CCM_PLL6_TUN
Default value: unknown

Offset: 0x002c

CCM_PLL7_CFG
Default value: 0x0010d063

Offset: 0x0030

CCM_OSC24M_CFG
Default value: 0x001380133

Offset: 0x0050

CCM_CPU_AXI_AHB_APB0_CFG
Default value: 0x00010010

Offset: 0x0054

CCM_APB1_CLK_DIV_CFG
Default value: 0x00000000

Offset: 0x0058

CCM_AXI_CLK_GATE
Default value: 0x00000000

Offset: 0x005c

CCM_AHB_GATING0
Default value: 0x00000000

Offset: 0x0060

CCM_AHB_GATING1
Default value: 0x00000000

Offset: 0x0064

CCM_APB0_GATING
Default value: 0x00000000

Offset: 0x0068

CCM_APB1_GATING
Default value: 0x00000000

Offset: 0x006c

CCM_NAND_CLK
Default value: 0x00000000

Offset: 0x0080

CCM_MMC0_CLK
Default value: 0x00000000

Offset: 0x0088

CCM_MMC1_CLK
Default value: 0x00000000

Offset: 0x008c

CCM_MMC2_CLK
Default value: 0x00000000

Offset: 0x0090

CCM_MMC3_CLK
Default value: 0x00000000

Offset: 0x0094

CCM_SS_CLK
Default value: 0x00000000

Offset: 0x009c

CCM_SPI0_CLK
Default value: 0x00000000

Offset: 0x00a0

CCM_SPI1_CLK
Default value: 0x00000000

Offset: 0x00a4

CCM_SPI2_CLK
Default value: 0x00000000

Offset: 0x00a8

CCM_SPI3_CLK
Default value: 0x00000000

Offset: 0x00d4

CCM_IR0_CLK
Default value: 0x00000000

Offset: 0x00b0

CCM_IR1_CLK
Default value: 0x00000000

Offset: 0x00b4

CCM_IIS_CLK
Default value: 0x00000000

Offset: 0x00b8

CCM_A97_CLK
Default value: 0x00030000

Offset: 0x00bc

CCM_KPAD_CLK
Default value: 0x0000001f

Offset: 0x00c4

CCM_SATA_CLK
Default value: 0x00000000

Offset: 0x00c8

CCM_USB_CLK
Default value: 0x00000000

Offset: 0x00cc

CCM_GPS_CLK
Default value: 0x00000000

Offset: 0x00d0

CCM_DRAM_CLK
Default value: 0x00000000

Offset: 0x0100

CCM_DE-BE0_CLK
Default value: 0x00000000

Offset: 0x0104

CCM_DE-BE1_CLK
Default value: 0x00000000

Offset: 0x0108

CCM_DE-FE0_CLK
Default value: 0x00000000

Offset: 0x010c

CCM_DE-FE1_CLK
Default value: 0x00000000

Offset: 0x0110

CCM_MP_CLK
Default value: 0x00000000

Offset: 0x0114

CCM_LCD0_CH0_CLK
Default value: 0x00000000

Offset: 0x0118

CCM_LCD0_CH1_CLK
Default value: 0x00000000

Offset: 0x012c

CCM_LCD1_CH0_CLK
Default value: 0x00000000

Offset: 0x011c

CCM_LCD1_CH1_CLK
Default value: 0x00000000

Offset: 0x0130

CCM_CSI-ISP_CLK
Default value: 0x00000000

Offset: 0x0120

CCM_TVD_CLK
Default value: 0x00000000

Offset: 0x0128

CCM_CSI0_CLK
Default value: 0x00000000

Offset: 0x0134

CCM_CSI1_CLK
Default value: 0x00000000

Offset: 0x0138

CCM_VE_CLK
Default value: 0x00000000

Offset: 0x013c

CCM_ADDA_CLK
Default value: 0x00000000

Offset: 0x0140

CCM_AVS_CLK
Default value: 0x00000000

Offset: 0x0144

CCM_ACE_CLK
Default value: 0x00000000

Offset: 0x0148

CCM_LVDS_CLK
Default value: 0x00000000

Offset: 0x014c

CCM_HDMI_CLK
Default value: 0x00000000

Offset: 0x0150

CCM_MALI400_CLK
Default value: 0x00000000

Offset: 0x0154

CCM_MBUS_CTRL
Default value: 0x00000000

Offset: 0x015c

CCM_MBUS_CH2_CTRL
Default value: 0x00000000

Offset: 0x0160

default map
md 0x01c20000 0x56 01c20000: a1005000 0a101010 08100010 00000000   .P.............. 01c20010: 0010d063 00000000 21081000 00000000   c..........!.... 01c20020: b1059491 14888020 21009911 00000000   .... ......!.... 01c20030: 0010d063 00000000 00000000 00000000   c............... 01c20040: 00000000 00000000 00000000 00000000   ................ 01c20050: 00138013 00020010 00000000 00000000   ................ 01c20060: 00004140 00000000 00000020 00010001   @A...... ....... 01c20070: 00000000 00000000 00000000 00000000   ................ 01c20080: 00000000 00000000 82000004 00000000   ................ 01c20090: 00000000 00000000 00000000 00000000   ................ 01c200a0: 00000000 00000000 00000000 00000000   ................ 01c200b0: 00000000 00000000 00000000 00030000   ................ 01c200c0: 00010000 0000001f 00000000 00000000   ................ 01c200d0: 00000000 00000000 00000000 00000000   ................ 01c200e0: 00000000 00000000 00000000 00000000   ................ 01c200f0: 00000000 00000000 00000000 00000000   ................ 01c20100: 00008000 00000000 00000000 00000000   ................ 01c20110: 00000000 00000000 00000000 00000000   ................ 01c20120: 00000000 00000000 00000000 00000000   ................ 01c20130: 00000000 00000000 00000000 00000000   ................ 01c20140: 00000000 00000000 00000000 00000000   ................ 01c20150: 00000000 00000000   ........

Code References
https://github.com/hno/uboot-allwinner/blob/lichee/lichee-dev-mmc/arch/arm/include/asm/arch-sunxi/clock.h https://github.com/amery/linux-allwinner/blob/allwinner-v3.0-android-v2/arch/arm/mach-sun4i/include/mach/ccmu_regs.h