User:Jemk/H3 DRAM delay tests

Created with https://github.com/jemk/u-boot/tree/h3-dram-delaytest

sunxi-fel spl spl/sunxi-spl.bin

4 columns: the 4 bytes (32-bit bus)
8 lines: the 8 data bits
4 blocks: even rising DQS, even falling DQS, odd rising DQS, odd falling DQS

Xunlong Orange Pi Plus (768MHz, 1.5V DDR3)

clk = 768, dqs_shift = 31, mdl = 52 53 53 52

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