H6/PIO

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Allwinner H6 pin multiplex configuration

No multiplexed pins on ports A, B and E

Port Bank C
Port Ball Type MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
PC0 - I/O NAND_WE reserved SPI0_CLK reserved reserved reserved
PC1 - I/O NAND_ALE SDC2_DS reserved reserved reserved reserved
PC2 - I/O NAND_CLE reserved SPI0_MOSI reserved reserved reserved
PC3 - I/O NAND_CE0 reserved SPI0_MISO reserved reserved reserved
PC4 - I/O NAND_RE SDC2_CLK reserved reserved reserved reserved
PC5 - I/O NAND_RB0 SDC2_CMD reserved reserved reserved reserved
PC6 - I/O NAND_DQ0 SDC2_D0 reserved reserved reserved reserved
PC7 - I/O NAND_DQ1 SDC2_D1 reserved reserved reserved reserved
PC8 - I/O NAND_DQ2 SDC2_D2 reserved reserved reserved reserved
PC9 - I/O NAND_DQ3 SDC2_D3 reserved reserved reserved reserved
PC10 - I/O NAND_DQ4 SDC2_D4 reserved reserved reserved reserved
PC11 - I/O NAND_DQ5 SDC2_D5 reserved reserved reserved reserved
PC12 - I/O NAND_DQ6 SDC2_D6 reserved reserved reserved reserved
PC13 - I/O NAND_DQ7 SDC2_D7 reserved reserved reserved reserved
PC14 - I/O NAND_DQS SDC2_RST reserved reserved reserved reserved
PC15 - I/O NAND_CE1 reserved reserved reserved reserved reserved
PC16 - I/O NAND_RB1 reserved reserved reserved reserved reserved
Port Bank D
Port Ball Type MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
PD0 - I/O LCD0_D2 TS0_CLK CSI_PCLK RGMII_RDX3/RMII_NULL reserved reserved
PD1 - I/O LCD0_D3 TS0_ERR CSI_MCLK RGMII_RDX2/RMII_NULL reserved reserved
PD2 - I/O LCD0_D4 TS0_SYNC CSI_HSYNC RGMII_RDX1/RMII_RXD1 reserved reserved
PD3 - I/O LCD0_D5 TS0_DVLD CSI_VSYNC RGMII_RDX0/RMII_RXD0 reserved reserved
PD4 - I/O LCD0_D6 TS0_D0 CSI_D0 RGMII_RXCK/RMII_NULL reserved reserved
PD5 - I/O LCD0_D7 TS0_D1 CSI_D1 RGMII_RXCTL/RMII_CRS_DV reserved reserved
PD6 - I/O LCD0_D10 TS0_D2 CSI_D2 RGMII_NULL/RMII_RXER reserved reserved
PD7 - I/O LCD0_D11 TS0_D3 CSI_D3 RGMII_TDX3/RMII_NULL reserved reserved
PD8 - I/O LCD0_D12 TS0_D4 CSI_D4 RGMII_TDX2/RMII_NULL reserved reserved
PD9 - I/O LCD0_D13 TS0_D5 CSI_D5 RGMII_TDX1/RMII_TXD1 reserved reserved
PD10 - I/O LCD0_D14 TS0_D6 CSI_D6 RGMII_TDX0/RMII_TXD0 reserved reserved
PD11 - I/O LCD0_D15 TS0_D7 CSI_D7 RGMII_TXCK/RMII_TXCK reserved reserved
PD12 - I/O LCD0_D18 TS1_CLK CSI_SCK RGMII_TXCTL/RMII_TXEN reserved reserved
PD13 - I/O LCD0_D19 TS1_ERR CSI_SDA RGMII_CLKIN/RMII_NULL reserved reserved
PD14 - I/O LCD0_D20 TS1_SYNC DMIC_CLK CSI_D8 reserved reserved
PD15 - I/O LCD0_D21 TS1_DVLD DMIC_DATA0 CSI_D9 reserved reserved
PD16 - I/O LCD0_D22 TS1_D0 DMIC_DATA1 reserved reserved reserved
PD17 - I/O LCD0_D23 TS2_CLK DMIC_DATA2 reserved reserved reserved
PD18 - I/O LCD0_CLK TS2_ERR DMIC_DATA3 reserved reserved reserved
PD19 - I/O LCD0_DE TS2_SYNC UART2_TX MDC reserved reserved
PD20 - I/O LCD0_HSYNC TS2_DVLD UART2_RX MDIO reserved reserved
PD21 - I/O LCD0_VSYNC TS2_D0 UART2_RTS reserved reserved reserved
PD22 - I/O PWM0 TS3_CLK UART2_CTS reserved reserved reserved
PD23 - I/O TWI2_SCK TS3_ERR UART3_TX JTAG_MS reserved reserved
PD24 - I/O TWI2_SDA TS3_SYNC UART3_RX JTAG_CK reserved reserved
PD25 - I/O TWI0_SCK TS3_DVLD UART3_RTS JTAG_D0 reserved reserved
PD26 - I/O TWI0_SDA TS3_D0 UART3_CTS JTAG_DI reserved reserved
Port Bank F
Port Ball Type MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
PF0 - I/O SDC0_D1 JTAG_MS1 reserved reserved PF_EINT0 reserved
PF1 - I/O SDC0_D0 JTAG_DI1 reserved reserved PF_EINT1 reserved
PF2 - I/O SDC0_CLK UART0_TX reserved reserved PF_EINT2 reserved
PF3 - I/O SDC0_CMD JTAG_DO1 reserved reserved PF_EINT3 reserved
PF4 - I/O SDC0_D3 UART0_RX reserved reserved PF_EINT4 reserved
PF5 - I/O SDC0_D2 JTAG_CK1 reserved reserved PF_EINT5 reserved
PF6 - I/O reserved reserved reserved reserved PF_EINT6 reserved
Port Bank G
Port Ball Type MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
PG0 - I/O SDC1_CLK reserved reserved reserved PG_EINT0 reserved
PG1 - I/O SDC1_CMD reserved reserved reserved PG_EINT1 reserved
PG2 - I/O SDC1_D0 reserved reserved reserved PG_EINT2 reserved
PG3 - I/O SDC1_D1 reserved reserved reserved PG_EINT3 reserved
PG4 - I/O SDC1_D2 reserved reserved reserved PG_EINT4 reserved
PG5 - I/O SDC1_D3 reserved reserved reserved PG_EINT5 reserved
PG6 - I/O UART1_TX reserved reserved reserved PG_EINT6 reserved
PG7 - I/O UART1_RX reserved reserved reserved PG_EINT7 reserved
PG8 - I/O UART1_RTS reserved SIM0_VPPEN reserved PG_EINT8 reserved
PG9 - I/O UART1_CTS reserved SIM0_VPPPP reserved PG_EINT9 reserved
PG10 - I/O PCM2_SYNC H_PCM2_SYNC SIM0_PWREN reserved PG_EINT10 reserved
PG11 - I/O PCM2_CLK H_PCM2_CLK SIM0_CLK reserved PG_EINT11 reserved
PG12 - I/O PCM2_DOUT H_PCM2_DOUT SIM0_DATA reserved PG_EINT12 reserved
PG13 - I/O PCM2_DIN H_PCM2_DIN SIM0_RST reserved PG_EINT13 reserved
PG14 - I/O PCM2_MCLK H_PCM2_MCLK SIM0_DET reserved PG_EINT14 reserved
Port Bank H
Port Ball Type MUX 2 MUX 3 MUX 4 MUX 5 MUX 6 MUX 7
PH0 - I/O UART0_TX PCM0_SYNC H_PCM0_SYNC SIM1_VPPEN PH_EINT0 reserved
PH1 - I/O UART0_RX PCM0_CLK H_PCM0_CLK SIM1_VPPPP PH_EINT1 reserved
PH2 - I/O CIR_TX PCM0_DOUT H_PCM0_DOUT SIM1_PWREN PH_EINT2 reserved
PH3 - I/O SPI1_CS PCM0_DIN H_PCM0_DIN SIM1_CLK PH_EINT3 reserved
PH4 - I/O SPI1_CLK PCM0_MCLK H_PCM0_MCLK SIM1_DATA PH_EINT4 reserved
PH5 - I/O SPI1_MOSI OWA_MCLK TWI1_SCK SIM1_RST PH_EINT5 reserved
PH6 - I/O SPI1_MISO OWA_IN TWI1_SDA SIM1_DET PH_EINT6 reserved
PH7 - I/O reserved OWA_OUT reserved reserved PH_EINT7 reserved
PH8 - I/O HSCL reserved reserved reserved PH_EINT8 reserved
PH9 - I/O HSDA reserved reserved reserved PH_EINT9 reserved
PH10 - I/O HCEC reserved reserved reserved PH_EINT10 reserved
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